diff options
| author | Ronald Cron <ronald.cron@arm.com> | 2014-08-19 13:29:52 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2014-08-19 13:29:52 +0000 |
| commit | 3402aac7d985bf8a9f9d3c639f3fe93609380513 (patch) | |
| tree | 67b11334dc45181581aaaac236243fe72c7f614c /ArmPkg/Library/ArmLib/Arm11 | |
| parent | 62d441fb17d59958bf00c4a1f3b52bf6a0b40b24 (diff) | |
| download | edk2-platforms-3402aac7d985bf8a9f9d3c639f3fe93609380513.tar.xz | |
ARM Packages: Removed trailing spaces
Trailing spaces create issue/warning when generating/applying patches.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <ronald.cron@arm.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15833 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Library/ArmLib/Arm11')
| -rw-r--r-- | ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c | 2 | ||||
| -rw-r--r-- | ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf | 6 | ||||
| -rw-r--r-- | ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c | 14 | ||||
| -rw-r--r-- | ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf | 6 | ||||
| -rw-r--r-- | ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf | 4 | ||||
| -rw-r--r-- | ArmPkg/Library/ArmLib/Arm11/Arm11Support.S | 22 | ||||
| -rw-r--r-- | ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm | 20 |
7 files changed, 37 insertions, 37 deletions
diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c b/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c index 1f353d477f..8c54b6cc8f 100644 --- a/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c +++ b/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c @@ -2,7 +2,7 @@ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
-
+
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf b/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf index 5f24ffaf3c..32d9299629 100644 --- a/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf +++ b/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf @@ -25,11 +25,11 @@ ../Common/Arm/ArmLibSupport.S | GCC
../Common/Arm/ArmLibSupport.asm | RVCT
../Common/ArmLib.c
-
+
Arm11Support.S | GCC
Arm11Support.asm | RVCT
- Arm11Lib.c
+ Arm11Lib.c
Arm11LibMem.c
../Arm9/Arm9CacheInformation.c
@@ -39,7 +39,7 @@ [LibraryClasses]
MemoryAllocationLib
-
+
[Protocols]
gEfiCpuArchProtocolGuid
diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c b/ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c index 6b94c41862..0f89801525 100644 --- a/ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c +++ b/ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c @@ -2,7 +2,7 @@ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.
-
+
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -29,7 +29,7 @@ FillTranslationTable ( UINTN Index;
UINT32 Attributes;
UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
-
+
switch (MemoryRegion->Attributes) {
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
@@ -53,10 +53,10 @@ FillTranslationTable ( Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
break;
}
-
+
Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
Sections = ((( MemoryRegion->Length - 1 ) / TT_DESCRIPTOR_SECTION_SIZE ) + 1 );
-
+
for (Index = 0; Index < Sections; Index++)
{
*Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
@@ -84,7 +84,7 @@ ArmConfigureMmu ( if (TranslationTableBase != NULL) {
*TranslationTableBase = TranslationTable;
}
-
+
if (TranslationTableBase != NULL) {
*TranslationTableSize = TRANSLATION_TABLE_SIZE;
}
@@ -109,7 +109,7 @@ ArmConfigureMmu ( }
ArmSetTTBR0(TranslationTable);
-
+
ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
DOMAIN_ACCESS_CONTROL_NONE(14) |
DOMAIN_ACCESS_CONTROL_NONE(13) |
@@ -126,7 +126,7 @@ ArmConfigureMmu ( DOMAIN_ACCESS_CONTROL_NONE( 2) |
DOMAIN_ACCESS_CONTROL_NONE( 1) |
DOMAIN_ACCESS_CONTROL_MANAGER(0));
-
+
ArmEnableInstructionCache();
ArmEnableDataCache();
ArmEnableMmu();
diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf b/ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf index 7239aceaf9..94dd03d82c 100644 --- a/ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf +++ b/ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf @@ -25,11 +25,11 @@ ../Common/Arm/ArmLibSupport.S | GCC
../Common/Arm/ArmLibSupport.asm | RVCT
../Common/ArmLib.c
-
+
Arm11Support.S | GCC
Arm11Support.asm | RVCT
- Arm11Lib.c
+ Arm11Lib.c
Arm11LibMem.c
../Arm9/Arm9CacheInformation.c
@@ -39,7 +39,7 @@ [LibraryClasses]
PrePiLib
-
+
[Protocols]
gEfiCpuArchProtocolGuid
diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf b/ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf index e693c46dc4..69763ed4ff 100644 --- a/ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf +++ b/ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf @@ -25,10 +25,10 @@ ../Common/Arm/ArmLibSupport.S | GCC
../Common/Arm/ArmLibSupport.asm | RVCT
../Common/ArmLib.c
-
+
Arm11Support.S | GCC
Arm11Support.asm | RVCT
-
+
Arm11Lib.c
../Arm9/Arm9CacheInformation.c
diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S index 2f4be7e93f..7fb454c3dd 100644 --- a/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S +++ b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S @@ -1,4 +1,4 @@ -#------------------------------------------------------------------------------
+#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2011, ARM Limited. All rights reserved.
@@ -73,12 +73,12 @@ ASM_PFX(ArmInvalidateInstructionAndDataTlb): bx lr
ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
- mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
+ mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
bx lr
ASM_PFX(ArmCleanDataCacheEntryByMVA):
- mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
+ mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
bx lr
@@ -135,7 +135,7 @@ ASM_PFX(ArmEnableDataCache): orr R0,R0,R1 @Set C bit
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
-
+
ASM_PFX(ArmDisableDataCache):
LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
@@ -149,7 +149,7 @@ ASM_PFX(ArmEnableInstructionCache): orr R0,R0,R1 @Set I bit
mcr p15,0,r0,c1,c0,0 @Write control register configuration data
bx LR
-
+
ASM_PFX(ArmDisableInstructionCache):
ldr R1,=IC_ON
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
@@ -171,17 +171,17 @@ ASM_PFX(ArmDisableBranchPrediction): ASM_PFX(ArmDataMemoryBarrier):
mov R0, #0
- mcr P15, #0, R0, C7, C10, #5
+ mcr P15, #0, R0, C7, C10, #5
bx LR
-
+
ASM_PFX(ArmDataSyncronizationBarrier):
mov R0, #0
- mcr P15, #0, R0, C7, C10, #4
+ mcr P15, #0, R0, C7, C10, #4
bx LR
-
+
ASM_PFX(ArmInstructionSynchronizationBarrier):
mov R0, #0
- mcr P15, #0, R0, C7, C5, #4
+ mcr P15, #0, R0, C7, C5, #4
bx LR
ASM_PFX(ArmSetLowVectors):
@@ -206,7 +206,7 @@ ASM_PFX(ArmIsMpCore): cmp r0, r1
movne r0, #0
pop { r1 }
- bx lr
+ bx lr
ASM_PFX(ArmCallWFI):
wfi
diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm index 8c27093045..53283d1eea 100644 --- a/ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm +++ b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm @@ -1,4 +1,4 @@ -//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
@@ -43,12 +43,12 @@ XP_ON EQU ( 0x1:SHL:23 ) ArmInvalidateDataCacheEntryByMVA
- mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
+ mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
bx lr
ArmCleanDataCacheEntryByMVA
- mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
+ mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
bx lr
@@ -105,7 +105,7 @@ ArmEnableDataCache ORR R0,R0,R1 ;Set C bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
BX LR
-
+
ArmDisableDataCache
LDR R1,=DC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
@@ -119,7 +119,7 @@ ArmEnableInstructionCache ORR R0,R0,R1 ;Set I bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
BX LR
-
+
ArmDisableInstructionCache
LDR R1,=IC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
@@ -141,17 +141,17 @@ ArmDisableBranchPrediction ASM_PFX(ArmDataMemoryBarrier):
mov R0, #0
- mcr P15, #0, R0, C7, C10, #5
+ mcr P15, #0, R0, C7, C10, #5
bx LR
-
+
ASM_PFX(ArmDataSyncronizationBarrier):
mov R0, #0
- mcr P15, #0, R0, C7, C10, #4
+ mcr P15, #0, R0, C7, C10, #4
bx LR
-
+
ASM_PFX(ArmInstructionSynchronizationBarrier):
MOV R0, #0
- MCR P15, #0, R0, C7, C5, #4
+ MCR P15, #0, R0, C7, C5, #4
bx LR
END
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