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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-04-16 12:57:04 +0200 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-04-26 19:05:05 +0200 |
| commit | 6c816b0e41758c4a75d0367afa7324bddf8151df (patch) | |
| tree | 18e72f2a8fb7bd9908f553aebf55c81ce847be02 /Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl | |
| parent | ed9be80fa9521edc2ef959d493904d4800e64ca1 (diff) | |
| download | edk2-platforms-6c816b0e41758c4a75d0367afa7324bddf8151df.tar.xz | |
Silicon/Socionext/SynQuacer: update PHY reference clock rate
As reported by Kojima-san, the PHY reference clock value we use in our
ACPI and DT descriptions is out of sync with the hardware. Replace
125 MHz with 250 MHz throughout.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl')
| -rw-r--r-- | Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl index b6f6c43600..3f73c191d4 100644 --- a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl @@ -162,7 +162,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "SNI", "SYNQUACR", Package (2) { "phy-channel", FixedPcdGet32 (PcdNetsecPhyAddress) },
Package (2) { "max-speed", 1000 },
Package (2) { "max-frame-size", 9000 },
- Package (2) { "socionext,phy-clock-frequency", 125000000 },
+ Package (2) { "socionext,phy-clock-frequency", 250000000 },
}
})
}
|