diff options
| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-10-27 21:24:34 +0100 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-11-17 18:48:12 +0000 |
| commit | 0cac7372c16c7d6755060a6264257f856f7fcf09 (patch) | |
| tree | 6ecb9c433418ffe026cd07fa66cf629a2b6a0822 /Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts | |
| parent | 92093e026f61bc45bddc612c14ceaede404cfdbf (diff) | |
| download | edk2-platforms-0cac7372c16c7d6755060a6264257f856f7fcf09.tar.xz | |
Silicon/SynQuacer: add description of GPIO block to device tree
Add a description of the SoCs GPIO controller as well as a description
of DIP switch block #3, which is wired to GPIOs 0 - 7, both on the
evaluation board as well as the Developer Box.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts')
| -rw-r--r-- | Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts b/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts index 9e0acd5933..6ae7d5f300 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts +++ b/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts @@ -19,3 +19,14 @@ model = "Socionext Developer Box";
compatible = "socionext,developer-box", "socionext,synquacer";
};
+
+&gpio {
+ gpio-line-names = "DSW3-PIN1", "DSW3-PIN2", "DSW3-PIN3", "DSW3-PIN4",
+ "DSW3-PIN5", "DSW3-PIN6", "DSW3-PIN7", "DSW3-PIN8",
+ "PSIN#", "PWROFF#", "GPIO-A", "GPIO-B",
+ "GPIO-C", "GPIO-D", "PCIE1EXTINT", "PCIE0EXTINT",
+ "PHY2-INT#", "PHY1-INT#", "GPIO-E", "GPIO-F",
+ "GPIO-G", "GPIO-H", "GPIO-I", "GPIO-J",
+ "GPIO-K", "GPIO-L", "PEC-PD26", "PEC-PD27",
+ "PEC-PD28", "PEC-PD29", "PEC-PD30", "PEC-PD31";
+};
|