Silicon/SynQuacer: add description of GPIO block to device tree

Add a description of the SoCs GPIO controller as well as a description
of DIP switch block #3, which is wired to GPIOs 0 - 7, both on the
evaluation board as well as the Developer Box.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

1 files changed, 12 insertions, 0 deletions

diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
index f89e722219..966952b9a2 100644
--- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
+++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
@@ -21,6 +21,9 @@
 #define IRQ_TYPE_LEVEL_HIGH     4

 #define IRQ_TYPE_LEVEL_LOW      8

 

+#define GPIO_ACTIVE_HIGH        0

+#define GPIO_ACTIVE_LOW         1

+

 / {

     #address-cells = <2>;

     #size-cells = <2>;

@@ -511,4 +514,13 @@
         msi-map = <0x0 &its 0x10000 0x7f00>;

         dma-coherent;

     };

+

+    gpio: gpio@51000000 {

+        compatible = "socionext,synquacer-gpio", "fujitsu,mb86s70-gpio";

+        reg = <0x0 0x51000000 0x0 0x100>;

+        gpio-controller;

+        #gpio-cells = <2>;

+        clocks = <&clk_apb>;

+        base = <0>;

+    };

 };