diff options
| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-03-08 15:13:24 +0000 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-03-15 20:32:18 +0000 |
| commit | ca11ac71980cdb4c1bd3b4c2c6549b90fc47b4cc (patch) | |
| tree | 73dce23ff2357d079ffd4600254aca0c8f18738c /Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | |
| parent | f8acbb73fae68638ae57afd776802728b99a5901 (diff) | |
| download | edk2-platforms-ca11ac71980cdb4c1bd3b4c2c6549b90fc47b4cc.tar.xz | |
Silicon/SynQuacer: add cache topology information to device tree
Add a DT description of the size and geometry of the various levels
of caches that are present in the SynQuacer SoC.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi')
| -rw-r--r-- | Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index fdaccb9844..6e93c6ae16 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -1,5 +1,5 @@ /** @file
- * Copyright (c) 2017, Linaro Limited. All rights reserved.
+ * Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved.
*
* This program and the accompanying materials are licensed and made
* available under the terms and conditions of the BSD License which
@@ -575,3 +575,5 @@ #size-cells = <0>;
};
};
+
+#include "SynQuacerCaches.dtsi"
|