Silicon/SynQuacer: enable coherent DMA for NETSEC and eMMC

As it turns out, it is surprisingly easy to configure both the NETSEC
and eMMC devices as cache coherent for DMA, given that they are both
behind the same SMMU which is already configured in passthrough mode
by the firmware running on the SCP.

So update the static SMMU configuration to make memory accesses performed
by these devices inner shareable inner/outer writeback cacheable, which
makes them cache coherent with the CPUs.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

1 files changed, 2 insertions, 0 deletions

diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
index 5e663c59ef..ec784c70af 100644
--- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
+++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
@@ -456,6 +456,7 @@
             max-speed = <1000>;

             max-frame-size = <9000>;

             phy-handle = <&ethphy0>;

+            dma-coherent;

 

             #address-cells = <1>;

             #size-cells = <0>;

@@ -557,6 +558,7 @@
         fujitsu,cmd-dat-delay-select;

         clocks = <&clk_alw_c_0 &clk_alw_b_0>;

         clock-names = "core", "iface";

+        dma-coherent;

         status = "disabled";

     };

 };