Silicon/SynQuacer: enable coherent DMA for NETSEC and eMMC

As it turns out, it is surprisingly easy to configure both the NETSEC
and eMMC devices as cache coherent for DMA, given that they are both
behind the same SMMU which is already configured in passthrough mode
by the firmware running on the SCP.

So update the static SMMU configuration to make memory accesses performed
by these devices inner shareable inner/outer writeback cacheable, which
makes them cache coherent with the CPUs.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

1 files changed, 23 insertions, 0 deletions

diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c
index 070e6be92e..6432891312 100644
--- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c
+++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c
@@ -130,6 +130,27 @@ FreeDevice:
   return Status;

 }

 

+#define SMMU_SCR0                         0x0

+#define SMMU_SCR0_SHCFG_INNER             (0x2 << 22)

+#define SMMU_SCR0_MTCFG                   (0x1 << 20)

+#define SMMU_SCR0_MEMATTR_INNER_OUTER_WB  (0xf << 16)

+

+STATIC

+VOID

+SmmuEnableCoherentDma (

+  VOID

+  )

+{

+  //

+  // The SCB SMMU (MMU-500) is shared between the NETSEC and eMMC devices, and

+  // is configured in passthrough mode by default. Let's set the global memory

+  // type override as well, so that all memory accesses by these devices are

+  // inner shareable inner/outer writeback cacheable.

+  //

+  MmioOr32 (SYNQUACER_SCB_SMMU_BASE + SMMU_SCR0,

+    SMMU_SCR0_SHCFG_INNER | SMMU_SCR0_MTCFG | SMMU_SCR0_MEMATTR_INNER_OUTER_WB);

+}

+

 EFI_STATUS

 EFIAPI

 PlatformDxeEntryPoint (

@@ -178,5 +199,7 @@ PlatformDxeEntryPoint (
              &Handle);

   ASSERT_EFI_ERROR (Status);

 

+  SmmuEnableCoherentDma ();

+

   return EFI_SUCCESS;

 }