summaryrefslogtreecommitdiff
path: root/Silicon/Socionext/SynQuacer/Library
diff options
context:
space:
mode:
authorArd Biesheuvel <ard.biesheuvel@linaro.org>2017-12-07 13:34:49 +0000
committerArd Biesheuvel <ard.biesheuvel@linaro.org>2017-12-07 13:36:01 +0000
commitce95ec196da05885844afb79bd2570c5cd9f6b27 (patch)
tree7d1a2553bb54a57a7129a2576f343fe78e0d42c2 /Silicon/Socionext/SynQuacer/Library
parent23488946946f9cfb6296b4cf591ef6b86498921f (diff)
downloadedk2-platforms-ce95ec196da05885844afb79bd2570c5cd9f6b27.tar.xz
Silicon/SynQuacer: enable coherent DMA for NETSEC and eMMC
As it turns out, it is surprisingly easy to configure both the NETSEC and eMMC devices as cache coherent for DMA, given that they are both behind the same SMMU which is already configured in passthrough mode by the firmware running on the SCP. So update the static SMMU configuration to make memory accesses performed by these devices inner shareable inner/outer writeback cacheable, which makes them cache coherent with the CPUs. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Silicon/Socionext/SynQuacer/Library')
-rw-r--r--Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
index a640b3e0c0..1402ecafce 100644
--- a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
+++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
@@ -115,6 +115,9 @@ STATIC CONST ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[] = {
FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize)),
ARM_DEVICE_REGION (FixedPcdGet32 (PcdFlashNvStorageFtwSpareBase),
FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize)),
+
+ // NETSEC/eMMC SMMU
+ ARM_DEVICE_REGION (SYNQUACER_SCB_SMMU_BASE, SYNQUACER_SCB_SMMU_SIZE),
};
STATIC