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authorYao, Jiewen <jiewen.yao@intel.com>2015-11-30 19:57:45 +0000
committerHao Wu <hao.a.wu@intel.com>2016-02-25 09:13:25 +0800
commitf48825541ade03c576ecc2357b5fc9ca2db83e71 (patch)
treebc8d4973ee35d06b40ba70244e36dde8c8c9999e /UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
parentcd5e29959f602cddd8e4b42b207f2101b6e92e89 (diff)
downloadedk2-platforms-f48825541ade03c576ecc2357b5fc9ca2db83e71.tar.xz
UefiCpuPkg/PiSmmCpu: Always set WP in CR0
So that we can use write-protection for code later. It is REPOST. It includes suggestion from Michael Kinney <michael.d.kinney@intel.com>: - "For IA32 assembly, can we combine into a single OR instruction that sets both page enable and WP?" - "For X64, does it make sense to use single OR instruction instead of 2 BTS instructions as well?" Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> Suggested-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Cc: "Fan, Jeff" <jeff.fan@intel.com> Cc: "Kinney, Michael D" <michael.d.kinney@intel.com> Cc: "Laszlo Ersek" <lersek@redhat.com> Cc: "Paolo Bonzini" <pbonzini@redhat.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19068 6f19259b-4bc3-4df7-8a09-765794883524 (cherry picked from commit 53ba3fb8aaf91df4a65244480deb6fa60968c146)
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S')
-rw-r--r--UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
index b488b74b70..7e9ac58cb2 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
@@ -144,7 +144,7 @@ Base:
orb $1,%ah
wrmsr
movq %cr0, %rbx
- btsl $31, %ebx
+ orl $0x080010000, %ebx # enable paging + WP
movq %rbx, %cr0
retf
LongMode: # long mode (64-bit code) starts here