UefiCpuPkg/Msr: Add CPUID signature check MACROs

All model-specific MSRs are related to processor signatures that are defined in
each section in Chapter 35 Model-Specific-Registers (MSR), Intel(R) 64 and
IA-32 Architectures Software Developer's Manual, Volume 3, September 2016.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>

20 files changed, 365 insertions, 20 deletions

diff --git a/UefiCpuPkg/Include/Register/Msr/AtomMsr.h b/UefiCpuPkg/Include/Register/Msr/AtomMsr.h
index c314195820..b2764690f5 100644
--- a/UefiCpuPkg/Include/Register/Msr/AtomMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/AtomMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not

   provided for that MSR.

 

-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

   which accompanies this distribution.  The full text of the license may be found at

@@ -27,6 +27,26 @@
 #include <Register/ArchitecturalMsr.h>

 

 /**

+  Is Intel(R) Atom(TM) Processor Family?

+

+  @param   DisplayFamily  Display Family ID

+  @param   DisplayModel   Display Model ID

+

+  @retval  TRUE   Yes, it is.

+  @retval  FALSE  No, it isn't.

+**/

+#define IS_ATOM_PROCESSOR(DisplayFamily, DisplayModel) \

+  (DisplayFamily == 0x06 && \

+   (                        \

+    DisplayModel == 0x1C || \

+    DisplayModel == 0x26 || \

+    DisplayModel == 0x27 || \

+    DisplayModel == 0x35 || \

+    DisplayModel == 0x36    \

+    )                       \

+   )

+

+/**

   Shared. Model Specific Platform ID (R).

 

   @param  ECX  MSR_ATOM_PLATFORM_ID (0x00000017)

diff --git a/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
index 1c3c2dc474..90bd523c99 100644
--- a/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not

   provided for that MSR.

 

-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

   which accompanies this distribution.  The full text of the license may be found at

@@ -27,6 +27,25 @@
 #include <Register/ArchitecturalMsr.h>

 

 /**

+  Is Intel processors based on the Broadwell microarchitecture?

+

+  @param   DisplayFamily  Display Family ID

+  @param   DisplayModel   Display Model ID

+

+  @retval  TRUE   Yes, it is.

+  @retval  FALSE  No, it isn't.

+**/

+#define IS_BROADWELL_PROCESSOR(DisplayFamily, DisplayModel) \

+  (DisplayFamily == 0x06 && \

+   (                        \

+    DisplayModel == 0x3D || \

+    DisplayModel == 0x47 || \

+    DisplayModel == 0x4F || \

+    DisplayModel == 0x56    \

+    )                       \

+   )

+

+/**

   Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control

   Facilities.".

 

diff --git a/UefiCpuPkg/Include/Register/Msr/Core2Msr.h b/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
index 9f0e7900c9..9ebca5e9b5 100644
--- a/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not

   provided for that MSR.

 

-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

   which accompanies this distribution.  The full text of the license may be found at

@@ -27,6 +27,23 @@
 #include <Register/ArchitecturalMsr.h>

 

 /**

+  Is Intel(R) Core(TM) 2 Processor Family?

+

+  @param   DisplayFamily  Display Family ID

+  @param   DisplayModel   Display Model ID

+

+  @retval  TRUE   Yes, it is.

+  @retval  FALSE  No, it isn't.

+**/

+#define IS_CORE2_PROCESSOR(DisplayFamily, DisplayModel) \

+  (DisplayFamily == 0x06 && \

+   (                        \

+    DisplayModel == 0x0F || \

+    DisplayModel == 0x17    \

+    )                       \

+   )

+

+/**

   Shared. Model Specific Platform ID (R).

 

   @param  ECX  MSR_CORE2_PLATFORM_ID (0x00000017)

diff --git a/UefiCpuPkg/Include/Register/Msr/CoreMsr.h b/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
index 0902aa94d4..4897c74d5a 100644
--- a/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not

   provided for that MSR.

 

-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

   which accompanies this distribution.  The full text of the license may be found at

@@ -27,6 +27,22 @@
 #include <Register/ArchitecturalMsr.h>

 

 /**

+  Is Intel Core Solo and Intel Core Duo Processors?

+

+  @param   DisplayFamily  Display Family ID

+  @param   DisplayModel   Display Model ID

+

+  @retval  TRUE   Yes, it is.

+  @retval  FALSE  No, it isn't.

+**/

+#define IS_CORE_PROCESSOR(DisplayFamily, DisplayModel) \

+  (DisplayFamily == 0x06 && \

+   ( \

+    DisplayModel == 0x0E \

+    ) \

+   )

+

+/**

   Unique. See Section 35.22, "MSRs in Pentium Processors," and see Table 35-2.

 

   @param  ECX  MSR_CORE_P5_MC_ADDR (0x00000000)

diff --git a/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h b/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
index 58b9c5709a..5730918ec6 100644
--- a/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not

   provided for that MSR.

 

-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

   which accompanies this distribution.  The full text of the license may be found at

@@ -27,6 +27,22 @@
 #include <Register/ArchitecturalMsr.h>

 

 /**

+  Is Intel Atom processors based on the Goldmont microarchitecture?

+

+  @param   DisplayFamily  Display Family ID

+  @param   DisplayModel   Display Model ID

+

+  @retval  TRUE   Yes, it is.

+  @retval  FALSE  No, it isn't.

+**/

+#define IS_GOLDMONT_PROCESSOR(DisplayFamily, DisplayModel) \

+  (DisplayFamily == 0x06 && \

+   (                        \

+    DisplayModel == 0x5C    \

+    )                       \

+   )

+

+/**

   Core. Control Features in Intel 64Processor (R/W).

 

   @param  ECX  MSR_GOLDMONT_FEATURE_CONTROL (0x0000003A)

diff --git a/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h b/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
index 7b190b51f1..b737a9e4b8 100644
--- a/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not

   provided for that MSR.

 

-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

   which accompanies this distribution.  The full text of the license may be found at

@@ -27,6 +27,22 @@
 #include <Register/ArchitecturalMsr.h>

 

 /**

+  Is Intel processors based on the Haswell-E microarchitecture?

+

+  @param   DisplayFamily  Display Family ID

+  @param   DisplayModel   Display Model ID

+

+  @retval  TRUE   Yes, it is.

+  @retval  FALSE  No, it isn't.

+**/

+#define IS_HASWELL_E_PROCESSOR(DisplayFamily, DisplayModel) \

+  (DisplayFamily == 0x06 && \

+   (                        \

+    DisplayModel == 0x3F    \

+    )                       \

+   )

+

+/**

   Package. Configured State of Enabled Processor Core Count and Logical

   Processor Count (RO) -  After a Power-On RESET, enumerates factory

   configuration of the number of processor cores and logical processors in the

diff --git a/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h b/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
index 8bf2c38a40..3cd15846b4 100644
--- a/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not

   provided for that MSR.

 

-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

   which accompanies this distribution.  The full text of the license may be found at

@@ -27,6 +27,24 @@
 #include <Register/ArchitecturalMsr.h>

 

 /**

+  Is Intel processors based on the Haswell microarchitecture?

+

+  @param   DisplayFamily  Display Family ID

+  @param   DisplayModel   Display Model ID

+

+  @retval  TRUE   Yes, it is.

+  @retval  FALSE  No, it isn't.

+**/

+#define IS_HASWELL_PROCESSOR(DisplayFamily, DisplayModel) \

+  (DisplayFamily == 0x06 && \

+   (                        \

+    DisplayModel == 0x3C || \

+    DisplayModel == 0x45 || \

+    DisplayModel == 0x46    \

+    )                       \

+   )

+

+/**

   Package.

 

   @param  ECX  MSR_HASWELL_PLATFORM_INFO (0x000000CE)

diff --git a/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h b/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
index 41cbd2ec61..9eb07994ec 100644
--- a/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not

   provided for that MSR.

 

-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

   which accompanies this distribution.  The full text of the license may be found at

@@ -27,6 +27,22 @@
 #include <Register/ArchitecturalMsr.h>

 

 /**

+  Is Intel processors based on the Ivy Bridge microarchitecture?

+

+  @param   DisplayFamily  Display Family ID

+  @param   DisplayModel   Display Model ID

+

+  @retval  TRUE   Yes, it is.

+  @retval  FALSE  No, it isn't.

+**/

+#define IS_IVY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \

+  (DisplayFamily == 0x06 && \

+   (                        \

+    DisplayModel == 0x3A    \

+    )                       \

+   )

+

+/**

   Package. See http://biosbits.org.

 

   @param  ECX  MSR_IVY_BRIDGE_PLATFORM_INFO (0x000000CE)

diff --git a/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h b/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
index 20e60df204..94aebba4d1 100644
--- a/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not

   provided for that MSR.

 

-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

   which accompanies this distribution.  The full text of the license may be found at

@@ -27,6 +27,25 @@
 #include <Register/ArchitecturalMsr.h>

 

 /**

+  Is Intel processors based on the Nehalem microarchitecture?

+

+  @param   DisplayFamily  Display Family ID

+  @param   DisplayModel   Display Model ID

+

+  @retval  TRUE   Yes, it is.

+  @retval  FALSE  No, it isn't.

+**/

+#define IS_NEHALEM_PROCESSOR(DisplayFamily, DisplayModel) \

+  (DisplayFamily == 0x06 && \

+   (                        \

+    DisplayModel == 0x1A || \

+    DisplayModel == 0x1E || \

+    DisplayModel == 0x1F || \

+    DisplayModel == 0x2E    \

+    )                       \

+   )

+

+/**

   Package. Model Specific Platform ID (R).

 

   @param  ECX  MSR_NEHALEM_PLATFORM_ID (0x00000017)

diff --git a/UefiCpuPkg/Include/Register/Msr/P6Msr.h b/UefiCpuPkg/Include/Register/Msr/P6Msr.h
index ef908001c1..aec2e2c868 100644
--- a/UefiCpuPkg/Include/Register/Msr/P6Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/P6Msr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not

   provided for that MSR.

 

-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

   which accompanies this distribution.  The full text of the license may be found at

@@ -27,6 +27,27 @@
 #include <Register/ArchitecturalMsr.h>

 

 /**

+  Is P6 Family Processors?

+

+  @param   DisplayFamily  Display Family ID

+  @param   DisplayModel   Display Model ID

+

+  @retval  TRUE   Yes, it is.

+  @retval  FALSE  No, it isn't.

+**/

+#define IS_P6_PROCESSOR(DisplayFamily, DisplayModel) \

+  (DisplayFamily == 0x06 && \

+   (                        \

+    DisplayModel == 0x03 || \

+    DisplayModel == 0x05 || \

+    DisplayModel == 0x07 || \

+    DisplayModel == 0x08 || \

+    DisplayModel == 0x0A || \

+    DisplayModel == 0x0B \

+    ) \

+   )

+

+/**

   See Section 35.22, "MSRs in Pentium Processors.".

 

   @param  ECX  MSR_P6_P5_MC_ADDR (0x00000000)

diff --git a/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h b/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
index 6cf68b24b3..8922d56e2f 100644
--- a/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not

   provided for that MSR.

 

-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

   which accompanies this distribution.  The full text of the license may be found at

@@ -27,6 +27,19 @@
 #include <Register/ArchitecturalMsr.h>

 

 /**

+  Is Pentium(R) 4 Processors?

+

+  @param   DisplayFamily  Display Family ID

+  @param   DisplayModel   Display Model ID

+

+  @retval  TRUE   Yes, it is.

+  @retval  FALSE  No, it isn't.

+**/

+#define IS_PENTIUM_4_PROCESSOR(DisplayFamily, DisplayModel) \

+  (DisplayFamily == 0x0F \

+   )

+

+/**

   3, 4, 6. Shared. See Section 8.10.5, "Monitor/Mwait Address Range

   Determination.".

 

diff --git a/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h b/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
index 294a381120..70d54c81ee 100644
--- a/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not

   provided for that MSR.

 

-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

   which accompanies this distribution.  The full text of the license may be found at

@@ -27,6 +27,22 @@
 #include <Register/ArchitecturalMsr.h>

 

 /**

+  Is Pentium M Processors?

+

+  @param   DisplayFamily  Display Family ID

+  @param   DisplayModel   Display Model ID

+

+  @retval  TRUE   Yes, it is.

+  @retval  FALSE  No, it isn't.

+**/

+#define IS_PENTIUM_M_PROCESSOR(DisplayFamily, DisplayModel) \

+  (DisplayFamily == 0x06 && \

+   ( \

+    DisplayModel == 0x0D \

+    ) \

+   )

+

+/**

   See Section 35.22, "MSRs in Pentium Processors.".

 

   @param  ECX  MSR_PENTIUM_M_P5_MC_ADDR (0x00000000)

diff --git a/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h b/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
index cd846ea373..9b2578bac8 100644
--- a/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not

   provided for that MSR.

 

-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

   which accompanies this distribution.  The full text of the license may be found at

@@ -27,6 +27,24 @@
 #include <Register/ArchitecturalMsr.h>

 

 /**

+  Is Pentium Processors?

+

+  @param   DisplayFamily  Display Family ID

+  @param   DisplayModel   Display Model ID

+

+  @retval  TRUE   Yes, it is.

+  @retval  FALSE  No, it isn't.

+**/

+#define IS_PENTIUM_PROCESSOR(DisplayFamily, DisplayModel) \

+  (DisplayFamily == 0x05 && \

+   (                        \

+    DisplayModel == 0x01 || \

+    DisplayModel == 0x02 || \

+    DisplayModel == 0x04    \

+    )                       \

+   )

+

+/**

   See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".

 

   @param  ECX  MSR_PENTIUM_P5_MC_ADDR (0x00000000)

diff --git a/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h b/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
index 1819ecb66c..c8a0b971d3 100644
--- a/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not

   provided for that MSR.

 

-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

   which accompanies this distribution.  The full text of the license may be found at

@@ -27,6 +27,23 @@
 #include <Register/ArchitecturalMsr.h>

 

 /**

+  Is Intel processors based on the Sandy Bridge microarchitecture?

+

+  @param   DisplayFamily  Display Family ID

+  @param   DisplayModel   Display Model ID

+

+  @retval  TRUE   Yes, it is.

+  @retval  FALSE  No, it isn't.

+**/

+#define IS_SANDY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \

+  (DisplayFamily == 0x06 && \

+   (                        \

+    DisplayModel == 0x2A || \

+    DisplayModel == 0x2D    \

+    )                       \

+   )

+

+/**

   Thread. SMI Counter (R/O).

 

   @param  ECX  MSR_SANDY_BRIDGE_SMI_COUNT (0x00000034)

diff --git a/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h b/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
index b3b6b76f58..ec09bf3c13 100644
--- a/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not

   provided for that MSR.

 

-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

   which accompanies this distribution.  The full text of the license may be found at

@@ -27,6 +27,26 @@
 #include <Register/ArchitecturalMsr.h>

 

 /**

+  Is Intel processors based on the Silvermont microarchitecture?

+

+  @param   DisplayFamily  Display Family ID

+  @param   DisplayModel   Display Model ID

+

+  @retval  TRUE   Yes, it is.

+  @retval  FALSE  No, it isn't.

+**/

+#define IS_SILVERMONT_PROCESSOR(DisplayFamily, DisplayModel) \

+  (DisplayFamily == 0x06 && \

+   (                        \

+    DisplayModel == 0x37 || \

+    DisplayModel == 0x4A || \

+    DisplayModel == 0x4D || \

+    DisplayModel == 0x5A || \

+    DisplayModel == 0x5D    \

+    )                       \

+   )

+

+/**

   Module. Model Specific Platform ID (R).

 

   @param  ECX  MSR_SILVERMONT_PLATFORM_ID (0x00000017)

diff --git a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
index 23ca3e1b85..7166e5f9e0 100644
--- a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not

   provided for that MSR.

 

-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

   which accompanies this distribution.  The full text of the license may be found at

@@ -27,6 +27,23 @@
 #include <Register/ArchitecturalMsr.h>

 

 /**

+  Is Intel processors based on the Skylake microarchitecture?

+

+  @param   DisplayFamily  Display Family ID

+  @param   DisplayModel   Display Model ID

+

+  @retval  TRUE   Yes, it is.

+  @retval  FALSE  No, it isn't.

+**/

+#define IS_SKYLAKE_PROCESSOR(DisplayFamily, DisplayModel) \

+  (DisplayFamily == 0x06 && \

+   (                        \

+    DisplayModel == 0x4E || \

+    DisplayModel == 0x5E    \

+    )                       \

+   )

+

+/**

   Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,

   RW if MSR_PLATFORM_INFO.[28] = 1.

 

diff --git a/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h b/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
index ea22e22be9..ad7128ae95 100644
--- a/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not

   provided for that MSR.

 

-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

   which accompanies this distribution.  The full text of the license may be found at

@@ -27,6 +27,23 @@
 #include <Register/ArchitecturalMsr.h>

 

 /**

+  Is Intel(R) Xeon(R) Processor Series 5600?

+

+  @param   DisplayFamily  Display Family ID

+  @param   DisplayModel   Display Model ID

+

+  @retval  TRUE   Yes, it is.

+  @retval  FALSE  No, it isn't.

+**/

+#define IS_XEON_5600_PROCESSOR(DisplayFamily, DisplayModel) \

+  (DisplayFamily == 0x06 && \

+   (                        \

+    DisplayModel == 0x25 || \

+    DisplayModel == 0x2C    \

+    )                       \

+   )

+

+/**

   Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP

   handler to handle unsuccessful read of this MSR.

 

diff --git a/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h b/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
index 5e7e13aa8e..7b31288a35 100644
--- a/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not

   provided for that MSR.

 

-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

   which accompanies this distribution.  The full text of the license may be found at

@@ -27,6 +27,23 @@
 #include <Register/ArchitecturalMsr.h>

 

 /**

+  Is Intel(R) Xeon(R) Processor D product Family?

+

+  @param   DisplayFamily  Display Family ID

+  @param   DisplayModel   Display Model ID

+

+  @retval  TRUE   Yes, it is.

+  @retval  FALSE  No, it isn't.

+**/

+#define IS_XEON_D_PROCESSOR(DisplayFamily, DisplayModel) \

+  (DisplayFamily == 0x06 && \

+   (                        \

+    DisplayModel == 0x4F || \

+    DisplayModel == 0x56    \

+    )                       \

+   )

+

+/**

   Package. Protected Processor Inventory Number Enable Control (R/W).

 

   @param  ECX  MSR_XEON_D_PPIN_CTL (0x0000004E)

diff --git a/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h b/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
index d14ef21d6f..d509660c52 100644
--- a/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not

   provided for that MSR.

 

-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

   which accompanies this distribution.  The full text of the license may be found at

@@ -27,6 +27,22 @@
 #include <Register/ArchitecturalMsr.h>

 

 /**

+  Is Intel(R) Xeon(R) Processor E7 Family?

+

+  @param   DisplayFamily  Display Family ID

+  @param   DisplayModel   Display Model ID

+

+  @retval  TRUE   Yes, it is.

+  @retval  FALSE  No, it isn't.

+**/

+#define IS_XEON_E7_PROCESSOR(DisplayFamily, DisplayModel) \

+  (DisplayFamily == 0x06 && \

+   (                        \

+    DisplayModel == 0x2F    \

+    )                       \

+   )

+

+/**

   Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP

   handler to handle unsuccessful read of this MSR.

 

diff --git a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
index 853d83bfc5..43354d15c9 100644
--- a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not

   provided for that MSR.

 

-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>

   This program and the accompanying materials

   are licensed and made available under the terms and conditions of the BSD License

   which accompanies this distribution.  The full text of the license may be found at

@@ -27,6 +27,22 @@
 #include <Register/ArchitecturalMsr.h>

 

 /**

+  Is Intel(R) Xeon(R) Phi(TM) processor Family?

+

+  @param   DisplayFamily  Display Family ID

+  @param   DisplayModel   Display Model ID

+

+  @retval  TRUE   Yes, it is.

+  @retval  FALSE  No, it isn't.

+**/

+#define IS_XEON_PHI_PROCESSOR(DisplayFamily, DisplayModel) \

+  (DisplayFamily == 0x06 && \

+   (                        \

+    DisplayModel == 0x57    \

+    )                       \

+   )

+

+/**

   Thread. SMI Counter (R/O).

 

   @param  ECX  MSR_XEON_PHI_SMI_COUNT (0x00000034)