37 files changed, 0 insertions, 5937 deletions
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64ArchTimer.c b/ArmPkg/Library/ArmLib/AArch64/AArch64ArchTimer.c
deleted file mode 100644
index 63ce1978c0..0000000000
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64ArchTimer.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/** @file
-*
-*  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
-*
-*  This program and the accompanying materials
-*  are licensed and made available under the terms and conditions of the BSD License
-*  which accompanies this distribution.  The full text of the license may be found at
-*  http://opensource.org/licenses/bsd-license.php
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Uefi.h>
-#include <Chipset/AArch64.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/ArmLib.h>
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-#include "AArch64Lib.h"
-#include "ArmLibPrivate.h"
-#include <Library/ArmArchTimer.h>
-
-VOID
-EFIAPI
-ArmArchTimerReadReg (
-    IN   ARM_ARCH_TIMER_REGS   Reg,
-    OUT  VOID                  *DstBuf
-    )
-{
-  // Check if the Generic/Architecture timer is implemented
-  if (ArmIsArchTimerImplemented ()) {
-
-    switch (Reg) {
-
-    case CntFrq:
-      *((UINTN *)DstBuf) = ArmReadCntFrq ();
-      break;
-
-    case CntPct:
-      *((UINT64 *)DstBuf) = ArmReadCntPct ();
-      break;
-
-    case CntkCtl:
-      *((UINTN *)DstBuf) = ArmReadCntkCtl();
-      break;
-
-    case CntpTval:
-      *((UINTN *)DstBuf) = ArmReadCntpTval ();
-      break;
-
-    case CntpCtl:
-      *((UINTN *)DstBuf) = ArmReadCntpCtl ();
-      break;
-
-    case CntvTval:
-      *((UINTN *)DstBuf) = ArmReadCntvTval ();
-      break;
-
-    case CntvCtl:
-      *((UINTN *)DstBuf) = ArmReadCntvCtl ();
-      break;
-
-    case CntvCt:
-      *((UINT64 *)DstBuf) = ArmReadCntvCt ();
-      break;
-
-    case CntpCval:
-      *((UINT64 *)DstBuf) = ArmReadCntpCval ();
-      break;
-
-    case CntvCval:
-      *((UINT64 *)DstBuf) = ArmReadCntvCval ();
-      break;
-
-    case CntvOff:
-      *((UINT64 *)DstBuf) = ArmReadCntvOff ();
-      break;
-
-    case CnthCtl:
-    case CnthpTval:
-    case CnthpCtl:
-    case CnthpCval:
-    DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));
-      break;
-
-    default:
-      DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));
-    }
-  } else {
-    DEBUG ((EFI_D_ERROR, "Attempt to read ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));
-    ASSERT (0);
-  }
-}
-
-VOID
-EFIAPI
-ArmArchTimerWriteReg (
-    IN   ARM_ARCH_TIMER_REGS   Reg,
-    IN   VOID                  *SrcBuf
-    )
-{
-  // Check if the Generic/Architecture timer is implemented
-  if (ArmIsArchTimerImplemented ()) {
-
-    switch (Reg) {
-
-    case CntFrq:
-      ArmWriteCntFrq (*((UINTN *)SrcBuf));
-      break;
-
-    case CntPct:
-      DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTPCT \n"));
-      break;
-
-    case CntkCtl:
-      ArmWriteCntkCtl (*((UINTN *)SrcBuf));
-      break;
-
-    case CntpTval:
-      ArmWriteCntpTval (*((UINTN *)SrcBuf));
-      break;
-
-    case CntpCtl:
-      ArmWriteCntpCtl (*((UINTN *)SrcBuf));
-      break;
-
-    case CntvTval:
-      ArmWriteCntvTval (*((UINTN *)SrcBuf));
-      break;
-
-    case CntvCtl:
-      ArmWriteCntvCtl (*((UINTN *)SrcBuf));
-      break;
-
-    case CntvCt:
-      DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTVCT \n"));
-      break;
-
-    case CntpCval:
-      ArmWriteCntpCval (*((UINT64 *)SrcBuf) );
-      break;
-
-    case CntvCval:
-      ArmWriteCntvCval (*((UINT64 *)SrcBuf) );
-      break;
-
-    case CntvOff:
-      ArmWriteCntvOff (*((UINT64 *)SrcBuf));
-      break;
-
-    case CnthCtl:
-    case CnthpTval:
-    case CnthpCtl:
-    case CnthpCval:
-      DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));
-      break;
-
-    default:
-      DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));
-    }
-  } else {
-    DEBUG ((EFI_D_ERROR, "Attempt to write to ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));
-    ASSERT (0);
-  }
-}
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64ArchTimerSupport.S b/ArmPkg/Library/ArmLib/AArch64/AArch64ArchTimerSupport.S
deleted file mode 100644
index 3944d8bcb4..0000000000
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64ArchTimerSupport.S
+++ /dev/null
@@ -1,140 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution.  The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
-
-.text
-.align 2
-
-GCC_ASM_EXPORT(ArmReadCntFrq)
-GCC_ASM_EXPORT(ArmWriteCntFrq)
-GCC_ASM_EXPORT(ArmReadCntPct)
-GCC_ASM_EXPORT(ArmReadCntkCtl)
-GCC_ASM_EXPORT(ArmWriteCntkCtl)
-GCC_ASM_EXPORT(ArmReadCntpTval)
-GCC_ASM_EXPORT(ArmWriteCntpTval)
-GCC_ASM_EXPORT(ArmReadCntpCtl)
-GCC_ASM_EXPORT(ArmWriteCntpCtl)
-GCC_ASM_EXPORT(ArmReadCntvTval)
-GCC_ASM_EXPORT(ArmWriteCntvTval)
-GCC_ASM_EXPORT(ArmReadCntvCtl)
-GCC_ASM_EXPORT(ArmWriteCntvCtl)
-GCC_ASM_EXPORT(ArmReadCntvCt)
-GCC_ASM_EXPORT(ArmReadCntpCval)
-GCC_ASM_EXPORT(ArmWriteCntpCval)
-GCC_ASM_EXPORT(ArmReadCntvCval)
-GCC_ASM_EXPORT(ArmWriteCntvCval)
-GCC_ASM_EXPORT(ArmReadCntvOff)
-GCC_ASM_EXPORT(ArmWriteCntvOff)
-
-ASM_PFX(ArmReadCntFrq):
-  mrs   x0, cntfrq_el0           // Read CNTFRQ
-  ret
-
-
-# NOTE - Can only write while at highest implemented EL level (EL3 on model). Else ReadOnly (EL2, EL1, EL0)
-ASM_PFX(ArmWriteCntFrq):
-  msr   cntfrq_el0, x0           // Write to CNTFRQ
-  ret
-
-
-ASM_PFX(ArmReadCntPct):
-  mrs   x0, cntpct_el0           // Read CNTPCT (Physical counter register)
-  ret
-
-
-ASM_PFX(ArmReadCntkCtl):
-  mrs   x0, cntkctl_el1          // Read CNTK_CTL (Timer PL1 Control Register)
-  ret
-
-
-ASM_PFX(ArmWriteCntkCtl):
-  msr   cntkctl_el1, x0          // Write to CNTK_CTL (Timer PL1 Control Register)
-  ret
-
-
-ASM_PFX(ArmReadCntpTval):
-  mrs   x0, cntp_tval_el0        // Read CNTP_TVAL (PL1 physical timer value register)
-  ret
-
-
-ASM_PFX(ArmWriteCntpTval):
-  msr   cntp_tval_el0, x0        // Write to CNTP_TVAL (PL1 physical timer value register)
-  ret
-
-
-ASM_PFX(ArmReadCntpCtl):
-  mrs   x0, cntp_ctl_el0         // Read CNTP_CTL (PL1 Physical Timer Control Register)
-  ret
-
-
-ASM_PFX(ArmWriteCntpCtl):
-  msr   cntp_ctl_el0, x0         // Write to  CNTP_CTL (PL1 Physical Timer Control Register)
-  ret
-
-
-ASM_PFX(ArmReadCntvTval):
-  mrs   x0, cntv_tval_el0        // Read CNTV_TVAL (Virtual Timer Value register)
-  ret
-
-
-ASM_PFX(ArmWriteCntvTval):
-  msr   cntv_tval_el0, x0        // Write to CNTV_TVAL (Virtual Timer Value register)
-  ret
-
-
-ASM_PFX(ArmReadCntvCtl):
-  mrs   x0, cntv_ctl_el0         // Read CNTV_CTL (Virtual Timer Control Register)
-  ret
-
-
-ASM_PFX(ArmWriteCntvCtl):
-  msr   cntv_ctl_el0, x0         // Write to CNTV_CTL (Virtual Timer Control Register)
-  ret
-
-
-ASM_PFX(ArmReadCntvCt):
-  mrs  x0, cntvct_el0            // Read CNTVCT  (Virtual Count Register)
-  ret
-
-
-ASM_PFX(ArmReadCntpCval):
-  mrs   x0, cntp_cval_el0        // Read CNTP_CTVAL (Physical Timer Compare Value Register)
-  ret
-
-
-ASM_PFX(ArmWriteCntpCval):
-  msr   cntp_cval_el0, x0        // Write to CNTP_CTVAL (Physical Timer Compare Value Register)
-  ret
-
-
-ASM_PFX(ArmReadCntvCval):
-  mrs   x0, cntv_cval_el0        // Read CNTV_CTVAL (Virtual Timer Compare Value Register)
-  ret
-
-
-ASM_PFX(ArmWriteCntvCval):
-  msr   cntv_cval_el0, x0        // write to  CNTV_CTVAL (Virtual Timer Compare Value Register)
-  ret
-
-
-ASM_PFX(ArmReadCntvOff):
-  mrs   x0, cntvoff_el2          // Read CNTVOFF (virtual Offset register)
-  ret
-
-
-ASM_PFX(ArmWriteCntvOff):
-  msr   cntvoff_el2, x0          // Write to CNTVOFF (Virtual Offset register)
-  ret
-
-
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
deleted file mode 100644
index a4e1f20ad9..0000000000
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
+++ /dev/null
@@ -1,267 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-  Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Uefi.h>
-#include <Chipset/AArch64.h>
-#include <Library/ArmLib.h>
-#include <Library/BaseLib.h>
-#include <Library/IoLib.h>
-#include "AArch64Lib.h"
-#include "ArmLibPrivate.h"
-
-ARM_CACHE_TYPE
-EFIAPI
-ArmCacheType (
-  VOID
-  )
-{
-  return ARM_CACHE_TYPE_WRITE_BACK;
-}
-
-ARM_CACHE_ARCHITECTURE
-EFIAPI
-ArmCacheArchitecture (
-  VOID
-  )
-{
-  UINT32 CLIDR = ReadCLIDR ();
-
-  return (ARM_CACHE_ARCHITECTURE)CLIDR; // BugBug Fix Me
-}
-
-BOOLEAN
-EFIAPI
-ArmDataCachePresent (
-  VOID
-  )
-{
-  UINT32 CLIDR = ReadCLIDR ();
-
-  if ((CLIDR & 0x2) == 0x2) {
-    // Instruction cache exists
-    return TRUE;
-  }
-  if ((CLIDR & 0x7) == 0x4) {
-    // Unified cache
-    return TRUE;
-  }
-
-  return FALSE;
-}
-
-UINTN
-EFIAPI
-ArmDataCacheSize (
-  VOID
-  )
-{
-  UINT32 NumSets;
-  UINT32 Associativity;
-  UINT32 LineSize;
-  UINT32 CCSIDR = ReadCCSIDR (0);
-
-  LineSize      = (1 << ((CCSIDR & 0x7) + 2));
-  Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
-  NumSets       = ((CCSIDR >> 13) & 0x7fff) + 1;
-
-  // LineSize is in words (4 byte chunks)
-  return  NumSets * Associativity * LineSize * 4;
-}
-
-UINTN
-EFIAPI
-ArmDataCacheAssociativity (
-  VOID
-  )
-{
-  UINT32 CCSIDR = ReadCCSIDR (0);
-
-  return ((CCSIDR >> 3) & 0x3ff) + 1;
-}
-
-UINTN
-ArmDataCacheSets (
-  VOID
-  )
-{
-  UINT32 CCSIDR = ReadCCSIDR (0);
-
-  return ((CCSIDR >> 13) & 0x7fff) + 1;
-}
-
-UINTN
-EFIAPI
-ArmDataCacheLineLength (
-  VOID
-  )
-{
-  UINT32 CCSIDR = ReadCCSIDR (0) & 7;
-
-  // * 4 converts to bytes
-  return (1 << (CCSIDR + 2)) * 4;
-}
-
-BOOLEAN
-EFIAPI
-ArmInstructionCachePresent (
-  VOID
-  )
-{
-  UINT32 CLIDR = ReadCLIDR ();
-
-  if ((CLIDR & 1) == 1) {
-    // Instruction cache exists
-    return TRUE;
-  }
-  if ((CLIDR & 0x7) == 0x4) {
-    // Unified cache
-    return TRUE;
-  }
-
-  return FALSE;
-}
-
-UINTN
-EFIAPI
-ArmInstructionCacheSize (
-  VOID
-  )
-{
-  UINT32 NumSets;
-  UINT32 Associativity;
-  UINT32 LineSize;
-  UINT32 CCSIDR = ReadCCSIDR (1);
-
-  LineSize      = (1 << ((CCSIDR & 0x7) + 2));
-  Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
-  NumSets       = ((CCSIDR >> 13) & 0x7fff) + 1;
-
-  // LineSize is in words (4 byte chunks)
-  return  NumSets * Associativity * LineSize * 4;
-}
-
-UINTN
-EFIAPI
-ArmInstructionCacheAssociativity (
-  VOID
-  )
-{
-  UINT32 CCSIDR = ReadCCSIDR (1);
-
-  return ((CCSIDR >> 3) & 0x3ff) + 1;
-}
-
-UINTN
-EFIAPI
-ArmInstructionCacheSets (
-  VOID
-  )
-{
-  UINT32 CCSIDR = ReadCCSIDR (1);
-
-  return ((CCSIDR >> 13) & 0x7fff) + 1;
-}
-
-UINTN
-EFIAPI
-ArmInstructionCacheLineLength (
-  VOID
-  )
-{
-  UINT32 CCSIDR = ReadCCSIDR (1) & 7;
-
-  // * 4 converts to bytes
-  return (1 << (CCSIDR + 2)) * 4;
-}
-
-
-VOID
-AArch64DataCacheOperation (
-  IN  AARCH64_CACHE_OPERATION  DataCacheOperation
-  )
-{
-  UINTN     SavedInterruptState;
-
-  SavedInterruptState = ArmGetInterruptState ();
-  ArmDisableInterrupts();
-
-  AArch64AllDataCachesOperation (DataCacheOperation);
-
-  ArmDrainWriteBuffer ();
-
-  if (SavedInterruptState) {
-    ArmEnableInterrupts ();
-  }
-}
-
-
-VOID
-AArch64PoUDataCacheOperation (
-  IN  AARCH64_CACHE_OPERATION  DataCacheOperation
-  )
-{
-  UINTN     SavedInterruptState;
-
-  SavedInterruptState = ArmGetInterruptState ();
-  ArmDisableInterrupts ();
-
-  AArch64PerformPoUDataCacheOperation (DataCacheOperation);
-
-  ArmDrainWriteBuffer ();
-
-  if (SavedInterruptState) {
-    ArmEnableInterrupts ();
-  }
-}
-
-VOID
-EFIAPI
-ArmInvalidateDataCache (
-  VOID
-  )
-{
-  ArmDrainWriteBuffer ();
-  AArch64DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);
-}
-
-VOID
-EFIAPI
-ArmCleanInvalidateDataCache (
-  VOID
-  )
-{
-  ArmDrainWriteBuffer ();
-  AArch64DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);
-}
-
-VOID
-EFIAPI
-ArmCleanDataCache (
-  VOID
-  )
-{
-  ArmDrainWriteBuffer ();
-  AArch64DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
-}
-
-VOID
-EFIAPI
-ArmCleanDataCacheToPoU (
-  VOID
-  )
-{
-  ArmDrainWriteBuffer ();
-  AArch64PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);
-}
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h
deleted file mode 100644
index c8bb84365b..0000000000
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-  Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __AARCH64_LIB_H__
-#define __AARCH64_LIB_H__
-
-typedef VOID (*AARCH64_CACHE_OPERATION)(UINTN);
-
-
-VOID
-AArch64PerformPoUDataCacheOperation (
-  IN  AARCH64_CACHE_OPERATION  DataCacheOperation
-  );
-
-VOID
-AArch64AllDataCachesOperation (
-  IN  AARCH64_CACHE_OPERATION  DataCacheOperation
-  );
-
-#endif // __AARCH64_LIB_H__
-
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf
deleted file mode 100644
index dd585dea91..0000000000
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf
+++ /dev/null
@@ -1,43 +0,0 @@
-#/** @file
-#
-# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-# Portions copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution. The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = AArch64Lib
-  FILE_GUID                      = ef20ddf5-b334-47b3-94cf-52ff44c29138
-  MODULE_TYPE                    = DXE_DRIVER
-  VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = ArmLib
-
-[Sources.AARCH64]
-  AArch64Lib.c
-  AArch64Mmu.c
-  AArch64ArchTimer.c
-  ArmLibSupportV8.S
-  AArch64Support.S
-  AArch64ArchTimerSupport.S
-
-  ../Common/AArch64/ArmLibSupport.S
-  ../Common/ArmLib.c
-
-[Packages]
-  ArmPkg/ArmPkg.dec
-  MdePkg/MdePkg.dec
-
-[LibraryClasses]
-  MemoryAllocationLib
-
-[Protocols]
-  gEfiCpuArchProtocolGuid
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64LibPrePi.inf b/ArmPkg/Library/ArmLib/AArch64/AArch64LibPrePi.inf
deleted file mode 100644
index 23fbe86731..0000000000
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64LibPrePi.inf
+++ /dev/null
@@ -1,45 +0,0 @@
-#/** @file
-#
-#  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-#  Portions copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR>
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution. The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = AArch64LibPrePi
-  FILE_GUID                      = fd72688d-dbd8-4cf2-91a3-15171dea7816
-  MODULE_TYPE                    = BASE
-  VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = ArmLib
-
-[Sources.common]
-  ArmLibSupportV8.S
-  AArch64Support.S
-
-  ../Common/AArch64/ArmLibSupport.S
-  ../Common/ArmLib.c
-
-  AArch64Lib.c
-  AArch64Mmu.c
-
-  AArch64ArchTimer.c
-  AArch64ArchTimerSupport.S
-
-[Packages]
-  ArmPkg/ArmPkg.dec
-  MdePkg/MdePkg.dec
-
-[LibraryClasses]
-  PrePiLib
-
-[Protocols]
-  gEfiCpuArchProtocolGuid
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf b/ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf
deleted file mode 100644
index 302c09af49..0000000000
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf
+++ /dev/null
@@ -1,40 +0,0 @@
-#/* @file
-#
-#  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#*/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = AArch64Lib
-  FILE_GUID                      = eb7441e4-3ddf-48b8-a009-14f428b19e49
-  MODULE_TYPE                    = BASE
-  VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = ArmLib
-
-[Sources.common]
-  ArmLibSupportV8.S
-  AArch64Support.S
-
-  ../Common/AArch64/ArmLibSupport.S
-  ../Common/ArmLib.c
-
-  AArch64Lib.c
-
-  AArch64ArchTimer.c
-  AArch64ArchTimerSupport.S
-
-[Packages]
-  ArmPkg/ArmPkg.dec
-  MdePkg/MdePkg.dec
-
-[Protocols]
-  gEfiCpuArchProtocolGuid
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
deleted file mode 100644
index f215fe9275..0000000000
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
+++ /dev/null
@@ -1,701 +0,0 @@
-/** @file
-*  File managing the MMU for ARMv8 architecture
-*
-*  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
-*
-*  This program and the accompanying materials
-*  are licensed and made available under the terms and conditions of the BSD License
-*  which accompanies this distribution.  The full text of the license may be found at
-*  http://opensource.org/licenses/bsd-license.php
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Uefi.h>
-#include <Chipset/AArch64.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/ArmLib.h>
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-#include "AArch64Lib.h"
-#include "ArmLibPrivate.h"
-
-// We use this index definition to define an invalid block entry
-#define TT_ATTR_INDX_INVALID    ((UINT32)~0)
-
-STATIC
-UINT64
-ArmMemoryAttributeToPageAttribute (
-  IN ARM_MEMORY_REGION_ATTRIBUTES  Attributes
-  )
-{
-  switch (Attributes) {
-  case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
-    return TT_ATTR_INDX_MEMORY_WRITE_BACK;
-  case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
-    return TT_ATTR_INDX_MEMORY_WRITE_THROUGH;
-  case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
-    return TT_ATTR_INDX_DEVICE_MEMORY;
-  case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
-    return TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
-  case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
-    return TT_ATTR_INDX_MEMORY_WRITE_BACK;
-  case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
-    return TT_ATTR_INDX_MEMORY_WRITE_THROUGH;
-  case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
-    return TT_ATTR_INDX_DEVICE_MEMORY;
-  case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
-    return TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
-  default:
-    ASSERT(0);
-    return TT_ATTR_INDX_DEVICE_MEMORY;
-  }
-}
-
-UINT64
-PageAttributeToGcdAttribute (
-  IN UINT64 PageAttributes
-  )
-{
-  UINT64  GcdAttributes;
-
-  switch (PageAttributes & TT_ATTR_INDX_MASK) {
-  case TT_ATTR_INDX_DEVICE_MEMORY:
-    GcdAttributes = EFI_MEMORY_UC;
-    break;
-  case TT_ATTR_INDX_MEMORY_NON_CACHEABLE:
-    GcdAttributes = EFI_MEMORY_WC;
-    break;
-  case TT_ATTR_INDX_MEMORY_WRITE_THROUGH:
-    GcdAttributes = EFI_MEMORY_WT;
-    break;
-  case TT_ATTR_INDX_MEMORY_WRITE_BACK:
-    GcdAttributes = EFI_MEMORY_WB;
-    break;
-  default:
-    DEBUG ((EFI_D_ERROR, "PageAttributeToGcdAttribute: PageAttributes:0x%lX not supported.\n", PageAttributes));
-    ASSERT (0);
-    // The Global Coherency Domain (GCD) value is defined as a bit set.
-    // Returning 0 means no attribute has been set.
-    GcdAttributes = 0;
-  }
-
-  // Determine protection attributes
-  if (((PageAttributes & TT_AP_MASK) == TT_AP_NO_RO) || ((PageAttributes & TT_AP_MASK) == TT_AP_RO_RO)) {
-    // Read only cases map to write-protect
-    GcdAttributes |= EFI_MEMORY_WP;
-  }
-
-  // Process eXecute Never attribute
-  if ((PageAttributes & (TT_PXN_MASK | TT_UXN_MASK)) != 0 ) {
-    GcdAttributes |= EFI_MEMORY_XP;
-  }
-
-  return GcdAttributes;
-}
-
-UINT64
-GcdAttributeToPageAttribute (
-  IN UINT64 GcdAttributes
-  )
-{
-  UINT64  PageAttributes;
-
-  switch (GcdAttributes & 0xFF) {
-  case EFI_MEMORY_UC:
-    PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY;
-    break;
-  case EFI_MEMORY_WC:
-    PageAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
-    break;
-  case EFI_MEMORY_WT:
-    PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH;
-    break;
-  case EFI_MEMORY_WB:
-    PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK;
-    break;
-  default:
-    DEBUG ((EFI_D_ERROR, "GcdAttributeToPageAttribute: 0x%X attributes is not supported.\n", GcdAttributes));
-    ASSERT (0);
-    // If no match has been found then we mark the memory as device memory.
-    // The only side effect of using device memory should be a slow down in the performance.
-    PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY;
-  }
-
-  // Determine protection attributes
-  if (GcdAttributes & EFI_MEMORY_WP) {
-    // Read only cases map to write-protect
-    PageAttributes |= TT_AP_RO_RO;
-  }
-
-  // Process eXecute Never attribute
-  if (GcdAttributes & EFI_MEMORY_XP) {
-    PageAttributes |= (TT_PXN_MASK | TT_UXN_MASK);
-  }
-
-  return PageAttributes;
-}
-
-ARM_MEMORY_REGION_ATTRIBUTES
-GcdAttributeToArmAttribute (
-  IN UINT64 GcdAttributes
-  )
-{
-  switch (GcdAttributes & 0xFF) {
-  case EFI_MEMORY_UC:
-    return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
-  case EFI_MEMORY_WC:
-    return ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
-  case EFI_MEMORY_WT:
-    return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH;
-  case EFI_MEMORY_WB:
-    return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
-  default:
-    DEBUG ((EFI_D_ERROR, "GcdAttributeToArmAttribute: 0x%lX attributes is not supported.\n", GcdAttributes));
-    ASSERT (0);
-    return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
-  }
-}
-
-// Describe the T0SZ values for each translation table level
-typedef struct {
-  UINTN     MinT0SZ;
-  UINTN     MaxT0SZ;
-  UINTN     LargestT0SZ; // Generally (MaxT0SZ == LargestT0SZ) but at the Level3 Table
-                         // the MaxT0SZ is not at the boundary of the table
-} T0SZ_DESCRIPTION_PER_LEVEL;
-
-// Map table for the corresponding Level of Table
-STATIC CONST T0SZ_DESCRIPTION_PER_LEVEL T0SZPerTableLevel[] = {
-    { 16, 24, 24 }, // Table Level 0
-    { 25, 33, 33 }, // Table Level 1
-    { 34, 39, 42 }  // Table Level 2
-};
-
-VOID
-GetRootTranslationTableInfo (
-  IN UINTN     T0SZ,
-  OUT UINTN   *TableLevel,
-  OUT UINTN   *TableEntryCount
-  )
-{
-  UINTN Index;
-
-  // Identify the level of the root table from the given T0SZ
-  for (Index = 0; Index < sizeof (T0SZPerTableLevel) / sizeof (T0SZ_DESCRIPTION_PER_LEVEL); Index++) {
-    if (T0SZ <= T0SZPerTableLevel[Index].MaxT0SZ) {
-      break;
-    }
-  }
-
-  // If we have not found the corresponding maximum T0SZ then we use the last one
-  if (Index == sizeof (T0SZPerTableLevel) / sizeof (T0SZ_DESCRIPTION_PER_LEVEL)) {
-    Index--;
-  }
-
-  // Get the level of the root table
-  if (TableLevel) {
-    *TableLevel = Index;
-  }
-
-  // The Size of the Table is 2^(T0SZ-LargestT0SZ)
-  if (TableEntryCount) {
-    *TableEntryCount = 1 << (T0SZPerTableLevel[Index].LargestT0SZ - T0SZ + 1);
-  }
-}
-
-STATIC
-VOID
-LookupAddresstoRootTable (
-  IN  UINT64  MaxAddress,
-  OUT UINTN  *T0SZ,
-  OUT UINTN  *TableEntryCount
-  )
-{
-  UINTN TopBit;
-
-  // Check the parameters are not NULL
-  ASSERT ((T0SZ != NULL) && (TableEntryCount != NULL));
-
-  // Look for the highest bit set in MaxAddress
-  for (TopBit = 63; TopBit != 0; TopBit--) {
-    if ((1ULL << TopBit) & MaxAddress) {
-      // MaxAddress top bit is found
-      TopBit = TopBit + 1;
-      break;
-    }
-  }
-  ASSERT (TopBit != 0);
-
-  // Calculate T0SZ from the top bit of the MaxAddress
-  *T0SZ = 64 - TopBit;
-
-  // Get the Table info from T0SZ
-  GetRootTranslationTableInfo (*T0SZ, NULL, TableEntryCount);
-}
-
-STATIC
-UINT64*
-GetBlockEntryListFromAddress (
-  IN  UINT64       *RootTable,
-  IN  UINT64        RegionStart,
-  OUT UINTN        *TableLevel,
-  IN OUT UINT64    *BlockEntrySize,
-  IN OUT UINT64   **LastBlockEntry
-  )
-{
-  UINTN   RootTableLevel;
-  UINTN   RootTableEntryCount;
-  UINT64 *TranslationTable;
-  UINT64 *BlockEntry;
-  UINT64 *SubTableBlockEntry;
-  UINT64  BlockEntryAddress;
-  UINTN   BaseAddressAlignment;
-  UINTN   PageLevel;
-  UINTN   Index;
-  UINTN   IndexLevel;
-  UINTN   T0SZ;
-  UINT64  Attributes;
-  UINT64  TableAttributes;
-
-  // Initialize variable
-  BlockEntry = NULL;
-
-  // Ensure the parameters are valid
-  if (!(TableLevel && BlockEntrySize && LastBlockEntry)) {
-    ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
-    return NULL;
-  }
-
-  // Ensure the Region is aligned on 4KB boundary
-  if ((RegionStart & (SIZE_4KB - 1)) != 0) {
-    ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
-    return NULL;
-  }
-
-  // Ensure the required size is aligned on 4KB boundary
-  if ((*BlockEntrySize & (SIZE_4KB - 1)) != 0) {
-    ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
-    return NULL;
-  }
-
-  //
-  // Calculate LastBlockEntry from T0SZ - this is the last block entry of the root Translation table
-  //
-  T0SZ = ArmGetTCR () & TCR_T0SZ_MASK;
-  // Get the Table info from T0SZ
-  GetRootTranslationTableInfo (T0SZ, &RootTableLevel, &RootTableEntryCount);
-  // The last block of the root table depends on the number of entry in this table
-  *LastBlockEntry = TT_LAST_BLOCK_ADDRESS(RootTable, RootTableEntryCount);
-
-  // If the start address is 0x0 then we use the size of the region to identify the alignment
-  if (RegionStart == 0) {
-    // Identify the highest possible alignment for the Region Size
-    for (BaseAddressAlignment = 0; BaseAddressAlignment < 64; BaseAddressAlignment++) {
-      if ((1 << BaseAddressAlignment) & *BlockEntrySize) {
-        break;
-      }
-    }
-  } else {
-    // Identify the highest possible alignment for the Base Address
-    for (BaseAddressAlignment = 0; BaseAddressAlignment < 64; BaseAddressAlignment++) {
-      if ((1 << BaseAddressAlignment) & RegionStart) {
-        break;
-      }
-    }
-  }
-
-  // Identify the Page Level the RegionStart must belongs to
-  PageLevel = 3 - ((BaseAddressAlignment - 12) / 9);
-
-  // If the required size is smaller than the current block size then we need to go to the page below.
-  // The PageLevel was calculated on the Base Address alignment but did not take in account the alignment
-  // of the allocation size
-  if (*BlockEntrySize < TT_BLOCK_ENTRY_SIZE_AT_LEVEL (PageLevel)) {
-    // It does not fit so we need to go a page level above
-    PageLevel++;
-  }
-
-  // Expose the found PageLevel to the caller
-  *TableLevel = PageLevel;
-
-  // Now, we have the Table Level we can get the Block Size associated to this table
-  *BlockEntrySize = TT_BLOCK_ENTRY_SIZE_AT_LEVEL (PageLevel);
-
-  //
-  // Get the Table Descriptor for the corresponding PageLevel. We need to decompose RegionStart to get appropriate entries
-  //
-
-  TranslationTable = RootTable;
-  for (IndexLevel = RootTableLevel; IndexLevel <= PageLevel; IndexLevel++) {
-    BlockEntry = (UINT64*)TT_GET_ENTRY_FOR_ADDRESS (TranslationTable, IndexLevel, RegionStart);
-
-    if ((IndexLevel != 3) && ((*BlockEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY)) {
-      // Go to the next table
-      TranslationTable = (UINT64*)(*BlockEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE);
-
-      // If we are at the last level then update the output
-      if (IndexLevel == PageLevel) {
-        // And get the appropriate BlockEntry at the next level
-        BlockEntry = (UINT64*)TT_GET_ENTRY_FOR_ADDRESS (TranslationTable, IndexLevel + 1, RegionStart);
-
-        // Set the last block for this new table
-        *LastBlockEntry = TT_LAST_BLOCK_ADDRESS(TranslationTable, TT_ENTRY_COUNT);
-      }
-    } else if ((*BlockEntry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY) {
-      // If we are not at the last level then we need to split this BlockEntry
-      if (IndexLevel != PageLevel) {
-        // Retrieve the attributes from the block entry
-        Attributes = *BlockEntry & TT_ATTRIBUTES_MASK;
-
-        // Convert the block entry attributes into Table descriptor attributes
-        TableAttributes = TT_TABLE_AP_NO_PERMISSION;
-        if (Attributes & TT_PXN_MASK) {
-          TableAttributes = TT_TABLE_PXN;
-        }
-        if (Attributes & TT_UXN_MASK) {
-          TableAttributes = TT_TABLE_XN;
-        }
-        if (Attributes & TT_NS) {
-          TableAttributes = TT_TABLE_NS;
-        }
-
-        // Get the address corresponding at this entry
-        BlockEntryAddress = RegionStart;
-        BlockEntryAddress = BlockEntryAddress >> TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel);
-        // Shift back to right to set zero before the effective address
-        BlockEntryAddress = BlockEntryAddress << TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel);
-
-        // Set the correct entry type for the next page level
-        if ((IndexLevel + 1) == 3) {
-          Attributes |= TT_TYPE_BLOCK_ENTRY_LEVEL3;
-        } else {
-          Attributes |= TT_TYPE_BLOCK_ENTRY;
-        }
-
-        // Create a new translation table
-        TranslationTable = (UINT64*)AllocatePages (EFI_SIZE_TO_PAGES((TT_ENTRY_COUNT * sizeof(UINT64)) + TT_ALIGNMENT_DESCRIPTION_TABLE));
-        if (TranslationTable == NULL) {
-          return NULL;
-        }
-        TranslationTable = (UINT64*)((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE);
-
-        // Populate the newly created lower level table
-        SubTableBlockEntry = TranslationTable;
-        for (Index = 0; Index < TT_ENTRY_COUNT; Index++) {
-          *SubTableBlockEntry = Attributes | (BlockEntryAddress + (Index << TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel + 1)));
-          SubTableBlockEntry++;
-        }
-
-        // Fill the BlockEntry with the new TranslationTable
-        *BlockEntry = ((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE) | TableAttributes | TT_TYPE_TABLE_ENTRY;
-        // Update the last block entry with the newly created translation table
-        *LastBlockEntry = TT_LAST_BLOCK_ADDRESS(TranslationTable, TT_ENTRY_COUNT);
-
-        // Block Entry points at the beginning of the Translation Table
-        BlockEntry = TranslationTable;
-      }
-    } else {
-      if (IndexLevel != PageLevel) {
-        //
-        // Case when we have an Invalid Entry and we are at a page level above of the one targetted.
-        //
-
-        // Create a new translation table
-        TranslationTable = (UINT64*)AllocatePages (EFI_SIZE_TO_PAGES((TT_ENTRY_COUNT * sizeof(UINT64)) + TT_ALIGNMENT_DESCRIPTION_TABLE));
-        if (TranslationTable == NULL) {
-          return NULL;
-        }
-        TranslationTable = (UINT64*)((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE);
-
-        ZeroMem (TranslationTable, TT_ENTRY_COUNT * sizeof(UINT64));
-
-        // Fill the new BlockEntry with the TranslationTable
-        *BlockEntry = ((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE) | TT_TYPE_TABLE_ENTRY;
-        // Update the last block entry with the newly created translation table
-        *LastBlockEntry = TT_LAST_BLOCK_ADDRESS(TranslationTable, TT_ENTRY_COUNT);
-      } else {
-        //
-        // Case when the new region is part of an existing page table
-        //
-        *LastBlockEntry = TT_LAST_BLOCK_ADDRESS(TranslationTable, TT_ENTRY_COUNT);
-      }
-    }
-  }
-
-  return BlockEntry;
-}
-
-STATIC
-RETURN_STATUS
-FillTranslationTable (
-  IN  UINT64                        *RootTable,
-  IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryRegion
-  )
-{
-  UINT64  Attributes;
-  UINT32  Type;
-  UINT64  RegionStart;
-  UINT64  RemainingRegionLength;
-  UINT64 *BlockEntry;
-  UINT64 *LastBlockEntry;
-  UINT64  BlockEntrySize;
-  UINTN   TableLevel;
-
-  // Ensure the Length is aligned on 4KB boundary
-  if ((MemoryRegion->Length == 0) || ((MemoryRegion->Length & (SIZE_4KB - 1)) != 0)) {
-    ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
-    return RETURN_INVALID_PARAMETER;
-  }
-
-  // Variable initialization
-  Attributes = ArmMemoryAttributeToPageAttribute (MemoryRegion->Attributes) | TT_AF;
-  RemainingRegionLength = MemoryRegion->Length;
-  RegionStart = MemoryRegion->VirtualBase;
-
-  do {
-    // Get the first Block Entry that matches the Virtual Address and also the information on the Table Descriptor
-    // such as the the size of the Block Entry and the address of the last BlockEntry of the Table Descriptor
-    BlockEntrySize = RemainingRegionLength;
-    BlockEntry = GetBlockEntryListFromAddress (RootTable, RegionStart, &TableLevel, &BlockEntrySize, &LastBlockEntry);
-    if (BlockEntry == NULL) {
-      // GetBlockEntryListFromAddress() return NULL when it fails to allocate new pages from the Translation Tables
-      return RETURN_OUT_OF_RESOURCES;
-    }
-
-    if (TableLevel != 3) {
-      Type = TT_TYPE_BLOCK_ENTRY;
-    } else {
-      Type = TT_TYPE_BLOCK_ENTRY_LEVEL3;
-    }
-
-    do {
-      // Fill the Block Entry with attribute and output block address
-      *BlockEntry = (RegionStart & TT_ADDRESS_MASK_BLOCK_ENTRY) | Attributes | Type;
-
-      // Go to the next BlockEntry
-      RegionStart += BlockEntrySize;
-      RemainingRegionLength -= BlockEntrySize;
-      BlockEntry++;
-    } while ((RemainingRegionLength >= BlockEntrySize) && (BlockEntry <= LastBlockEntry));
-  } while (RemainingRegionLength != 0);
-
-  return RETURN_SUCCESS;
-}
-
-RETURN_STATUS
-SetMemoryAttributes (
-  IN EFI_PHYSICAL_ADDRESS      BaseAddress,
-  IN UINT64                    Length,
-  IN UINT64                    Attributes,
-  IN EFI_PHYSICAL_ADDRESS      VirtualMask
-  )
-{
-  RETURN_STATUS                Status;
-  ARM_MEMORY_REGION_DESCRIPTOR MemoryRegion;
-  UINT64                      *TranslationTable;
-
-  MemoryRegion.PhysicalBase = BaseAddress;
-  MemoryRegion.VirtualBase = BaseAddress;
-  MemoryRegion.Length = Length;
-  MemoryRegion.Attributes = GcdAttributeToArmAttribute (Attributes);
-
-  TranslationTable = ArmGetTTBR0BaseAddress ();
-
-  Status = FillTranslationTable (TranslationTable, &MemoryRegion);
-  if (RETURN_ERROR (Status)) {
-    return Status;
-  }
-
-  // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks
-  // flush and invalidate pages
-  ArmCleanInvalidateDataCache ();
-
-  ArmInvalidateInstructionCache ();
-
-  // Invalidate all TLB entries so changes are synced
-  ArmInvalidateTlb ();
-
-  return RETURN_SUCCESS;
-}
-
-RETURN_STATUS
-EFIAPI
-ArmConfigureMmu (
-  IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,
-  OUT VOID                         **TranslationTableBase OPTIONAL,
-  OUT UINTN                         *TranslationTableSize OPTIONAL
-  )
-{
-  VOID*                         TranslationTable;
-  UINTN                         TranslationTablePageCount;
-  UINT32                        TranslationTableAttribute;
-  ARM_MEMORY_REGION_DESCRIPTOR *MemoryTableEntry;
-  UINT64                        MaxAddress;
-  UINT64                        TopAddress;
-  UINTN                         T0SZ;
-  UINTN                         RootTableEntryCount;
-  UINT64                        TCR;
-  RETURN_STATUS                 Status;
-
-  if(MemoryTable == NULL) {
-    ASSERT (MemoryTable != NULL);
-    return RETURN_INVALID_PARAMETER;
-  }
-
-  // Identify the highest address of the memory table
-  MaxAddress = MemoryTable->PhysicalBase + MemoryTable->Length - 1;
-  MemoryTableEntry = MemoryTable;
-  while (MemoryTableEntry->Length != 0) {
-    TopAddress = MemoryTableEntry->PhysicalBase + MemoryTableEntry->Length - 1;
-    if (TopAddress > MaxAddress) {
-      MaxAddress = TopAddress;
-    }
-    MemoryTableEntry++;
-  }
-
-  // Lookup the Table Level to get the information
-  LookupAddresstoRootTable (MaxAddress, &T0SZ, &RootTableEntryCount);
-
-  //
-  // Set TCR that allows us to retrieve T0SZ in the subsequent functions
-  //
-  // Ideally we will be running at EL2, but should support EL1 as well.
-  // UEFI should not run at EL3.
-  if (ArmReadCurrentEL () == AARCH64_EL2) {
-    //Note: Bits 23 and 31 are reserved(RES1) bits in TCR_EL2
-    TCR = T0SZ | (1UL << 31) | (1UL << 23) | TCR_TG0_4KB;
-
-    // Set the Physical Address Size using MaxAddress
-    if (MaxAddress < SIZE_4GB) {
-      TCR |= TCR_PS_4GB;
-    } else if (MaxAddress < SIZE_64GB) {
-      TCR |= TCR_PS_64GB;
-    } else if (MaxAddress < SIZE_1TB) {
-      TCR |= TCR_PS_1TB;
-    } else if (MaxAddress < SIZE_4TB) {
-      TCR |= TCR_PS_4TB;
-    } else if (MaxAddress < SIZE_16TB) {
-      TCR |= TCR_PS_16TB;
-    } else if (MaxAddress < SIZE_256TB) {
-      TCR |= TCR_PS_256TB;
-    } else {
-      DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress));
-      ASSERT (0); // Bigger than 48-bit memory space are not supported
-      return RETURN_UNSUPPORTED;
-    }
-  } else if (ArmReadCurrentEL () == AARCH64_EL1) {
-    TCR = T0SZ | TCR_TG0_4KB;
-
-    // Set the Physical Address Size using MaxAddress
-    if (MaxAddress < SIZE_4GB) {
-      TCR |= TCR_IPS_4GB;
-    } else if (MaxAddress < SIZE_64GB) {
-      TCR |= TCR_IPS_64GB;
-    } else if (MaxAddress < SIZE_1TB) {
-      TCR |= TCR_IPS_1TB;
-    } else if (MaxAddress < SIZE_4TB) {
-      TCR |= TCR_IPS_4TB;
-    } else if (MaxAddress < SIZE_16TB) {
-      TCR |= TCR_IPS_16TB;
-    } else if (MaxAddress < SIZE_256TB) {
-      TCR |= TCR_IPS_256TB;
-    } else {
-      DEBUG ((EFI_D_ERROR, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress));
-      ASSERT (0); // Bigger than 48-bit memory space are not supported
-      return RETURN_UNSUPPORTED;
-    }
-  } else {
-    ASSERT (0); // UEFI is only expected to run at EL2 and EL1, not EL3.
-    return RETURN_UNSUPPORTED;
-  }
-
-  // Set TCR
-  ArmSetTCR (TCR);
-
-  // Allocate pages for translation table
-  TranslationTablePageCount = EFI_SIZE_TO_PAGES((RootTableEntryCount * sizeof(UINT64)) + TT_ALIGNMENT_DESCRIPTION_TABLE);
-  TranslationTable = AllocatePages (TranslationTablePageCount);
-  if (TranslationTable == NULL) {
-    return RETURN_OUT_OF_RESOURCES;
-  }
-  TranslationTable = (VOID*)((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE);
-  // We set TTBR0 just after allocating the table to retrieve its location from the subsequent
-  // functions without needing to pass this value across the functions. The MMU is only enabled
-  // after the translation tables are populated.
-  ArmSetTTBR0 (TranslationTable);
-
-  if (TranslationTableBase != NULL) {
-    *TranslationTableBase = TranslationTable;
-  }
-
-  if (TranslationTableSize != NULL) {
-    *TranslationTableSize = RootTableEntryCount * sizeof(UINT64);
-  }
-
-  ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64));
-
-  // Disable MMU and caches. ArmDisableMmu() also invalidates the TLBs
-  ArmDisableMmu ();
-  ArmDisableDataCache ();
-  ArmDisableInstructionCache ();
-
-  // Make sure nothing sneaked into the cache
-  ArmCleanInvalidateDataCache ();
-  ArmInvalidateInstructionCache ();
-
-  TranslationTableAttribute = TT_ATTR_INDX_INVALID;
-  while (MemoryTable->Length != 0) {
-    // Find the memory attribute for the Translation Table
-    if (((UINTN)TranslationTable >= MemoryTable->PhysicalBase) &&
-        ((UINTN)TranslationTable <= MemoryTable->PhysicalBase - 1 + MemoryTable->Length)) {
-      TranslationTableAttribute = MemoryTable->Attributes;
-    }
-
-    Status = FillTranslationTable (TranslationTable, MemoryTable);
-    if (RETURN_ERROR (Status)) {
-      goto FREE_TRANSLATION_TABLE;
-    }
-    MemoryTable++;
-  }
-
-  // Translate the Memory Attributes into Translation Table Register Attributes
-  if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) ||
-      (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) {
-    TCR |= TCR_SH_NON_SHAREABLE | TCR_RGN_OUTER_NON_CACHEABLE | TCR_RGN_INNER_NON_CACHEABLE;
-  } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||
-      (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {
-    TCR |= TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WRITE_BACK_ALLOC | TCR_RGN_INNER_WRITE_BACK_ALLOC;
-  } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) ||
-      (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) {
-    TCR |= TCR_SH_NON_SHAREABLE | TCR_RGN_OUTER_WRITE_THROUGH | TCR_RGN_INNER_WRITE_THROUGH;
-  } else {
-    // If we failed to find a mapping that contains the root translation table then it probably means the translation table
-    // is not mapped in the given memory map.
-    ASSERT (0);
-    Status = RETURN_UNSUPPORTED;
-    goto FREE_TRANSLATION_TABLE;
-  }
-
-  // Set again TCR after getting the Translation Table attributes
-  ArmSetTCR (TCR);
-
-  ArmSetMAIR (MAIR_ATTR(TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY) |                      // mapped to EFI_MEMORY_UC
-              MAIR_ATTR(TT_ATTR_INDX_MEMORY_NON_CACHEABLE, MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE) | // mapped to EFI_MEMORY_WC
-              MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_THROUGH, MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH) | // mapped to EFI_MEMORY_WT
-              MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK));       // mapped to EFI_MEMORY_WB
-
-  ArmDisableAlignmentCheck ();
-  ArmEnableInstructionCache ();
-  ArmEnableDataCache ();
-
-  ArmEnableMmu ();
-  return RETURN_SUCCESS;
-
-FREE_TRANSLATION_TABLE:
-  FreePages (TranslationTable, TranslationTablePageCount);
-  return Status;
-}
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
deleted file mode 100644
index bdede48724..0000000000
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
+++ /dev/null
@@ -1,498 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution.  The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
-
-#include <Chipset/AArch64.h>
-#include <AsmMacroIoLibV8.h>
-
-.text
-.align 3
-
-GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
-GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
-GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
-GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
-GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
-GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
-GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)
-GCC_ASM_EXPORT (ArmDrainWriteBuffer)
-GCC_ASM_EXPORT (ArmEnableMmu)
-GCC_ASM_EXPORT (ArmDisableMmu)
-GCC_ASM_EXPORT (ArmDisableCachesAndMmu)
-GCC_ASM_EXPORT (ArmMmuEnabled)
-GCC_ASM_EXPORT (ArmEnableDataCache)
-GCC_ASM_EXPORT (ArmDisableDataCache)
-GCC_ASM_EXPORT (ArmEnableInstructionCache)
-GCC_ASM_EXPORT (ArmDisableInstructionCache)
-GCC_ASM_EXPORT (ArmDisableAlignmentCheck)
-GCC_ASM_EXPORT (ArmEnableAlignmentCheck)
-GCC_ASM_EXPORT (ArmEnableBranchPrediction)
-GCC_ASM_EXPORT (ArmDisableBranchPrediction)
-GCC_ASM_EXPORT (AArch64AllDataCachesOperation)
-GCC_ASM_EXPORT (AArch64PerformPoUDataCacheOperation)
-GCC_ASM_EXPORT (ArmDataMemoryBarrier)
-GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)
-GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
-GCC_ASM_EXPORT (ArmWriteVBar)
-GCC_ASM_EXPORT (ArmReadVBar)
-GCC_ASM_EXPORT (ArmEnableVFP)
-GCC_ASM_EXPORT (ArmCallWFI)
-GCC_ASM_EXPORT (ArmReadMpidr)
-GCC_ASM_EXPORT (ArmReadTpidrurw)
-GCC_ASM_EXPORT (ArmWriteTpidrurw)
-GCC_ASM_EXPORT (ArmIsArchTimerImplemented)
-GCC_ASM_EXPORT (ArmReadIdPfr0)
-GCC_ASM_EXPORT (ArmReadIdPfr1)
-GCC_ASM_EXPORT (ArmWriteHcr)
-GCC_ASM_EXPORT (ArmReadCurrentEL)
-
-.set CTRL_M_BIT,      (1 << 0)
-.set CTRL_A_BIT,      (1 << 1)
-.set CTRL_C_BIT,      (1 << 2)
-.set CTRL_I_BIT,      (1 << 12)
-.set CTRL_V_BIT,      (1 << 12)
-.set CPACR_VFP_BITS,  (3 << 20)
-
-ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
-  dc      ivac, x0    // Invalidate single data cache line
-  dsb     sy
-  isb
-  ret
-
-
-ASM_PFX(ArmCleanDataCacheEntryByMVA):
-  dc      cvac, x0    // Clean single data cache line
-  dsb     sy
-  isb
-  ret
-
-
-ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
-  dc      civac, x0   // Clean and invalidate single data cache line
-  dsb     sy
-  isb
-  ret
-
-
-ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
-  dc      isw, x0     // Invalidate this line
-  dsb     sy
-  isb
-  ret
-
-
-ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
-  dc      cisw, x0    // Clean and Invalidate this line
-  dsb     sy
-  isb
-  ret
-
-
-ASM_PFX(ArmCleanDataCacheEntryBySetWay):
-  dc      csw, x0     // Clean this line
-  dsb     sy
-  isb
-  ret
-
-
-ASM_PFX(ArmInvalidateInstructionCache):
-  ic      iallu       // Invalidate entire instruction cache
-  dsb     sy
-  isb
-  ret
-
-
-ASM_PFX(ArmEnableMmu):
-   EL1_OR_EL2_OR_EL3(x1)
-1: mrs     x0, sctlr_el1       // Read System control register EL1
-   b       4f
-2: mrs     x0, sctlr_el2       // Read System control register EL2
-   b       4f
-3: mrs     x0, sctlr_el3       // Read System control register EL3
-4: orr     x0, x0, #CTRL_M_BIT // Set MMU enable bit
-   EL1_OR_EL2_OR_EL3(x1)
-1: tlbi    vmalle1
-   isb
-   msr     sctlr_el1, x0       // Write back
-   b       4f
-2: tlbi    alle2
-   isb
-   msr     sctlr_el2, x0       // Write back
-   b       4f
-3: tlbi    alle3
-   isb
-   msr     sctlr_el3, x0       // Write back
-4: dsb     sy
-   isb
-   ret
-
-
-ASM_PFX(ArmDisableMmu):
-   EL1_OR_EL2_OR_EL3(x1)
-1: mrs     x0, sctlr_el1        // Read System Control Register EL1
-   b       4f
-2: mrs     x0, sctlr_el2        // Read System Control Register EL2
-   b       4f
-3: mrs     x0, sctlr_el3        // Read System Control Register EL3
-4: and     x0, x0, #~CTRL_M_BIT  // Clear MMU enable bit
-   EL1_OR_EL2_OR_EL3(x1)
-1: msr     sctlr_el1, x0        // Write back
-   tlbi    vmalle1
-   b       4f
-2: msr     sctlr_el2, x0        // Write back
-   tlbi    alle2
-   b       4f
-3: msr     sctlr_el3, x0        // Write back
-   tlbi    alle3
-4: dsb     sy
-   isb
-   ret
-
-
-ASM_PFX(ArmDisableCachesAndMmu):
-   EL1_OR_EL2_OR_EL3(x1)
-1: mrs     x0, sctlr_el1        // Get control register EL1
-   b       4f
-2: mrs     x0, sctlr_el2        // Get control register EL2
-   b       4f
-3: mrs     x0, sctlr_el3        // Get control register EL3
-4: mov     x1, #~(CTRL_M_BIT | CTRL_C_BIT | CTRL_I_BIT)  // Disable MMU, D & I caches
-   and     x0, x0, x1
-   EL1_OR_EL2_OR_EL3(x1)
-1: msr     sctlr_el1, x0        // Write back control register
-   b       4f
-2: msr     sctlr_el2, x0        // Write back control register
-   b       4f
-3: msr     sctlr_el3, x0        // Write back control register
-4: dsb     sy
-   isb
-   ret
-
-
-ASM_PFX(ArmMmuEnabled):
-   EL1_OR_EL2_OR_EL3(x1)
-1: mrs     x0, sctlr_el1        // Get control register EL1
-   b       4f
-2: mrs     x0, sctlr_el2        // Get control register EL2
-   b       4f
-3: mrs     x0, sctlr_el3        // Get control register EL3
-4: and     x0, x0, #CTRL_M_BIT
-   ret
-
-
-ASM_PFX(ArmEnableDataCache):
-   EL1_OR_EL2_OR_EL3(x1)
-1: mrs     x0, sctlr_el1        // Get control register EL1
-   b       4f
-2: mrs     x0, sctlr_el2        // Get control register EL2
-   b       4f
-3: mrs     x0, sctlr_el3        // Get control register EL3
-4: orr     x0, x0, #CTRL_C_BIT  // Set C bit
-   EL1_OR_EL2_OR_EL3(x1)
-1: msr     sctlr_el1, x0        // Write back control register
-   b       4f
-2: msr     sctlr_el2, x0        // Write back control register
-   b       4f
-3: msr     sctlr_el3, x0        // Write back control register
-4: dsb     sy
-   isb
-   ret
-
-
-ASM_PFX(ArmDisableDataCache):
-   EL1_OR_EL2_OR_EL3(x1)
-1: mrs     x0, sctlr_el1        // Get control register EL1
-   b       4f
-2: mrs     x0, sctlr_el2        // Get control register EL2
-   b       4f
-3: mrs     x0, sctlr_el3        // Get control register EL3
-4: and     x0, x0, #~CTRL_C_BIT  // Clear C bit
-   EL1_OR_EL2_OR_EL3(x1)
-1: msr     sctlr_el1, x0        // Write back control register
-   b       4f
-2: msr     sctlr_el2, x0        // Write back control register
-   b       4f
-3: msr     sctlr_el3, x0        // Write back control register
-4: dsb     sy
-   isb
-   ret
-
-
-ASM_PFX(ArmEnableInstructionCache):
-   EL1_OR_EL2_OR_EL3(x1)
-1: mrs     x0, sctlr_el1        // Get control register EL1
-   b       4f
-2: mrs     x0, sctlr_el2        // Get control register EL2
-   b       4f
-3: mrs     x0, sctlr_el3        // Get control register EL3
-4: orr     x0, x0, #CTRL_I_BIT  // Set I bit
-   EL1_OR_EL2_OR_EL3(x1)
-1: msr     sctlr_el1, x0        // Write back control register
-   b       4f
-2: msr     sctlr_el2, x0        // Write back control register
-   b       4f
-3: msr     sctlr_el3, x0        // Write back control register
-4: dsb     sy
-   isb
-   ret
-
-
-ASM_PFX(ArmDisableInstructionCache):
-   EL1_OR_EL2_OR_EL3(x1)
-1: mrs     x0, sctlr_el1        // Get control register EL1
-   b       4f
-2: mrs     x0, sctlr_el2        // Get control register EL2
-   b       4f
-3: mrs     x0, sctlr_el3        // Get control register EL3
-4: and     x0, x0, #~CTRL_I_BIT  // Clear I bit
-   EL1_OR_EL2_OR_EL3(x1)
-1: msr     sctlr_el1, x0        // Write back control register
-   b       4f
-2: msr     sctlr_el2, x0        // Write back control register
-   b       4f
-3: msr     sctlr_el3, x0        // Write back control register
-4: dsb     sy
-   isb
-   ret
-
-
-ASM_PFX(ArmEnableAlignmentCheck):
-   EL1_OR_EL2(x1)
-1: mrs     x0, sctlr_el1        // Get control register EL1
-   b       3f
-2: mrs     x0, sctlr_el2        // Get control register EL2
-3: orr     x0, x0, #CTRL_A_BIT  // Set A (alignment check) bit
-   EL1_OR_EL2(x1)
-1: msr     sctlr_el1, x0        // Write back control register
-   b       3f
-2: msr     sctlr_el2, x0        // Write back control register
-3: dsb     sy
-   isb
-   ret
-
-
-ASM_PFX(ArmDisableAlignmentCheck):
-   EL1_OR_EL2_OR_EL3(x1)
-1: mrs     x0, sctlr_el1        // Get control register EL1
-   b       4f
-2: mrs     x0, sctlr_el2        // Get control register EL2
-   b       4f
-3: mrs     x0, sctlr_el3        // Get control register EL3
-4: and     x0, x0, #~CTRL_A_BIT  // Clear A (alignment check) bit
-   EL1_OR_EL2_OR_EL3(x1)
-1: msr     sctlr_el1, x0        // Write back control register
-   b       4f
-2: msr     sctlr_el2, x0        // Write back control register
-   b       4f
-3: msr     sctlr_el3, x0        // Write back control register
-4: dsb     sy
-   isb
-   ret
-
-
-// Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now
-ASM_PFX(ArmEnableBranchPrediction):
-  ret
-
-
-// Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now.
-ASM_PFX(ArmDisableBranchPrediction):
-  ret
-
-
-ASM_PFX(AArch64AllDataCachesOperation):
-// We can use regs 0-7 and 9-15 without having to save/restore.
-// Save our link register on the stack. - The stack must always be quad-word aligned
-  str   x30, [sp, #-16]!
-  mov   x1, x0                  // Save Function call in x1
-  mrs   x6, clidr_el1           // Read EL1 CLIDR
-  and   x3, x6, #0x7000000      // Mask out all but Level of Coherency (LoC)
-  lsr   x3, x3, #23             // Left align cache level value - the level is shifted by 1 to the
-                                // right to ease the access to CSSELR and the Set/Way operation.
-  cbz   x3, L_Finished          // No need to clean if LoC is 0
-  mov   x10, #0                 // Start clean at cache level 0
-  b     Loop1
-
-ASM_PFX(AArch64PerformPoUDataCacheOperation):
-// We can use regs 0-7 and 9-15 without having to save/restore.
-// Save our link register on the stack. - The stack must always be quad-word aligned
-  str   x30, [sp, #-16]!
-  mov   x1, x0                  // Save Function call in x1
-  mrs   x6, clidr_el1           // Read EL1 CLIDR
-  and   x3, x6, #0x38000000     // Mask out all but Point of Unification (PoU)
-  lsr   x3, x3, #26             // Left align cache level value - the level is shifted by 1 to the
-                                // right to ease the access to CSSELR and the Set/Way operation.
-  cbz   x3, L_Finished          // No need to clean if LoC is 0
-  mov   x10, #0                 // Start clean at cache level 0
-
-Loop1:
-  add   x2, x10, x10, lsr #1    // Work out 3x cachelevel for cache info
-  lsr   x12, x6, x2             // bottom 3 bits are the Cache type for this level
-  and   x12, x12, #7            // get those 3 bits alone
-  cmp   x12, #2                 // what cache at this level?
-  b.lt  L_Skip                  // no cache or only instruction cache at this level
-  msr   csselr_el1, x10         // write the Cache Size selection register with current level (CSSELR)
-  isb                           // isb to sync the change to the CacheSizeID reg
-  mrs   x12, ccsidr_el1         // reads current Cache Size ID register (CCSIDR)
-  and   x2, x12, #0x7           // extract the line length field
-  add   x2, x2, #4              // add 4 for the line length offset (log2 16 bytes)
-  mov   x4, #0x400
-  sub   x4, x4, #1
-  and   x4, x4, x12, lsr #3     // x4 is the max number on the way size (right aligned)
-  clz   w5, w4                  // w5 is the bit position of the way size increment
-  mov   x7, #0x00008000
-  sub   x7, x7, #1
-  and   x7, x7, x12, lsr #13    // x7 is the max number of the index size (right aligned)
-
-Loop2:
-  mov   x9, x4                  // x9 working copy of the max way size (right aligned)
-
-Loop3:
-  lsl   x11, x9, x5
-  orr   x0, x10, x11            // factor in the way number and cache number
-  lsl   x11, x7, x2
-  orr   x0, x0, x11             // factor in the index number
-
-  blr   x1                      // Goto requested cache operation
-
-  subs  x9, x9, #1              // decrement the way number
-  b.ge  Loop3
-  subs  x7, x7, #1              // decrement the index
-  b.ge  Loop2
-L_Skip:
-  add   x10, x10, #2            // increment the cache number
-  cmp   x3, x10
-  b.gt  Loop1
-
-L_Finished:
-  dsb   sy
-  isb
-  ldr   x30, [sp], #0x10
-  ret
-
-
-ASM_PFX(ArmDataMemoryBarrier):
-  dmb   sy
-  ret
-
-
-ASM_PFX(ArmDataSyncronizationBarrier):
-ASM_PFX(ArmDrainWriteBuffer):
-  dsb   sy
-  ret
-
-
-ASM_PFX(ArmInstructionSynchronizationBarrier):
-  isb
-  ret
-
-
-ASM_PFX(ArmWriteVBar):
-   EL1_OR_EL2_OR_EL3(x1)
-1: msr   vbar_el1, x0            // Set the Address of the EL1 Vector Table in the VBAR register
-   b     4f
-2: msr   vbar_el2, x0            // Set the Address of the EL2 Vector Table in the VBAR register
-   b     4f
-3: msr   vbar_el3, x0            // Set the Address of the EL3 Vector Table in the VBAR register
-4: isb
-   ret
-
-ASM_PFX(ArmReadVBar):
-   EL1_OR_EL2_OR_EL3(x1)
-1: mrs   x0, vbar_el1            // Set the Address of the EL1 Vector Table in the VBAR register
-   ret
-2: mrs   x0, vbar_el2            // Set the Address of the EL2 Vector Table in the VBAR register
-   ret
-3: mrs   x0, vbar_el3            // Set the Address of the EL3 Vector Table in the VBAR register
-   ret
-
-
-ASM_PFX(ArmEnableVFP):
-  // Check whether floating-point is implemented in the processor.
-  mov   x1, x30                 // Save LR
-  bl    ArmReadIdPfr0           // Read EL1 Processor Feature Register (PFR0)
-  mov   x30, x1                 // Restore LR
-  ands  x0, x0, #AARCH64_PFR0_FP// Extract bits indicating VFP implementation
-  cmp   x0, #0                  // VFP is implemented if '0'.
-  b.ne  4f                      // Exit if VFP not implemented.
-  // FVP is implemented.
-  // Make sure VFP exceptions are not trapped (to any exception level).
-  mrs   x0, cpacr_el1           // Read EL1 Coprocessor Access Control Register (CPACR)
-  orr   x0, x0, #CPACR_VFP_BITS // Disable FVP traps to EL1
-  msr   cpacr_el1, x0           // Write back EL1 Coprocessor Access Control Register (CPACR)
-  mov   x1, #AARCH64_CPTR_TFP   // TFP Bit for trapping VFP Exceptions
-  EL1_OR_EL2_OR_EL3(x2)
-1:ret                           // Not configurable in EL1
-2:mrs   x0, cptr_el2            // Disable VFP traps to EL2
-  bic   x0, x0, x1
-  msr   cptr_el2, x0
-  ret
-3:mrs   x0, cptr_el3            // Disable VFP traps to EL3
-  bic   x0, x0, x1
-  msr   cptr_el3, x0
-4:ret
-
-
-ASM_PFX(ArmCallWFI):
-  wfi
-  ret
-
-
-ASM_PFX(ArmReadMpidr):
-  mrs   x0, mpidr_el1           // read EL1 MPIDR
-  ret
-
-
-// Keep old function names for C compatibilty for now. Change later?
-ASM_PFX(ArmReadTpidrurw):
-  mrs   x0, tpidr_el0           // read tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)
-  ret
-
-
-// Keep old function names for C compatibilty for now. Change later?
-ASM_PFX(ArmWriteTpidrurw):
-  msr   tpidr_el0, x0           // write tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)
-  ret
-
-
-// Arch timers are mandatory on AArch64
-ASM_PFX(ArmIsArchTimerImplemented):
-  mov   x0, #1
-  ret
-
-
-ASM_PFX(ArmReadIdPfr0):
-  mrs   x0, id_aa64pfr0_el1   // Read ID_AA64PFR0 Register
-  ret
-
-
-// Q: id_aa64pfr1_el1 not defined yet. What does this funtion want to access?
-// A: used to setup arch timer. Check if we have security extensions, permissions to set stuff.
-//    See: ArmPkg/Library/ArmArchTimerLib/AArch64/ArmArchTimerLib.c
-//    Not defined yet, but stick in here for now, should read all zeros.
-ASM_PFX(ArmReadIdPfr1):
-  mrs   x0, id_aa64pfr1_el1   // Read ID_PFR1 Register
-  ret
-
-// VOID ArmWriteHcr(UINTN Hcr)
-ASM_PFX(ArmWriteHcr):
-  msr   hcr_el2, x0        // Write the passed HCR value
-  ret
-
-// UINTN ArmReadCurrentEL(VOID)
-ASM_PFX(ArmReadCurrentEL):
-  mrs   x0, CurrentEL
-  ret
-
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S
deleted file mode 100644
index 8fd4194ab2..0000000000
--- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S
+++ /dev/null
@@ -1,127 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution.  The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
-
-#include <AsmMacroIoLibV8.h>
-
-.text
-.align 3
-
-GCC_ASM_EXPORT (ArmIsMpCore)
-GCC_ASM_EXPORT (ArmEnableAsynchronousAbort)
-GCC_ASM_EXPORT (ArmDisableAsynchronousAbort)
-GCC_ASM_EXPORT (ArmEnableIrq)
-GCC_ASM_EXPORT (ArmDisableIrq)
-GCC_ASM_EXPORT (ArmEnableFiq)
-GCC_ASM_EXPORT (ArmDisableFiq)
-GCC_ASM_EXPORT (ArmEnableInterrupts)
-GCC_ASM_EXPORT (ArmDisableInterrupts)
-GCC_ASM_EXPORT (ArmDisableAllExceptions)
-GCC_ASM_EXPORT (ReadCCSIDR)
-GCC_ASM_EXPORT (ReadCLIDR)
-
-#------------------------------------------------------------------------------
-
-.set MPIDR_U_BIT,    (30)
-.set MPIDR_U_MASK,   (1 << MPIDR_U_BIT)
-.set DAIF_FIQ_BIT,   (1 << 0)
-.set DAIF_IRQ_BIT,   (1 << 1)
-.set DAIF_ABORT_BIT, (1 << 2)
-.set DAIF_DEBUG_BIT, (1 << 3)
-.set DAIF_INT_BITS,  (DAIF_FIQ_BIT | DAIF_IRQ_BIT)
-.set DAIF_ALL,       (DAIF_DEBUG_BIT | DAIF_ABORT_BIT | DAIF_INT_BITS)
-
-
-ASM_PFX(ArmIsMpCore):
-  mrs   x0, mpidr_el1         // Read EL1 Mutliprocessor Affinty Reg (MPIDR)
-  and   x0, x0, #MPIDR_U_MASK // U Bit clear, the processor is part of a multiprocessor system
-  lsr   x0, x0, #MPIDR_U_BIT
-  eor   x0, x0, #1
-  ret
-
-
-ASM_PFX(ArmEnableAsynchronousAbort):
-  msr   daifclr, #DAIF_ABORT_BIT
-  isb
-  ret
-
-
-ASM_PFX(ArmDisableAsynchronousAbort):
-  msr   daifset, #DAIF_ABORT_BIT
-  isb
-  ret
-
-
-ASM_PFX(ArmEnableIrq):
-  msr   daifclr, #DAIF_IRQ_BIT
-  isb
-  ret
-
-
-ASM_PFX(ArmDisableIrq):
-  msr   daifset, #DAIF_IRQ_BIT
-  isb
-  ret
-
-
-ASM_PFX(ArmEnableFiq):
-  msr   daifclr, #DAIF_FIQ_BIT
-  isb
-  ret
-
-
-ASM_PFX(ArmDisableFiq):
-  msr   daifset, #DAIF_FIQ_BIT
-  isb
-  ret
-
-
-ASM_PFX(ArmEnableInterrupts):
-  msr   daifclr, #DAIF_INT_BITS
-  isb
-  ret
-
-
-ASM_PFX(ArmDisableInterrupts):
-  msr   daifset, #DAIF_INT_BITS
-  isb
-  ret
-
-
-ASM_PFX(ArmDisableAllExceptions):
-  msr   daifset, #DAIF_ALL
-  isb
-  ret
-
-
-// UINT32
-// ReadCCSIDR (
-//   IN UINT32 CSSELR
-//   )
-ASM_PFX(ReadCCSIDR):
-  msr   csselr_el1, x0        // Write Cache Size Selection Register (CSSELR)
-  isb
-  mrs   x0, ccsidr_el1        // Read current Cache Size ID Register (CCSIDR)
-  ret
-
-
-// UINT32
-// ReadCLIDR (
-//   IN UINT32 CSSELR
-//   )
-ASM_PFX(ReadCLIDR):
-  mrs   x0, clidr_el1         // Read Cache Level ID Register
-  ret
-
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf b/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf
deleted file mode 100644
index e8aa056fbf..0000000000
--- a/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf
+++ /dev/null
@@ -1,43 +0,0 @@
-#/** @file
-# Semihosting  serail port lib
-#
-# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution. The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = Arm9ArmLib
-  FILE_GUID                      = 375D70D3-91E0-4374-A540-68BD959EB184
-  MODULE_TYPE                    = DXE_DRIVER
-  VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = ArmLib
-
-[Sources.common]
-  ../Common/Arm/ArmLibSupport.S    | GCC
-  ../Common/Arm/ArmLibSupport.asm  | RVCT
-  ../Common/ArmLib.c
-
-  Arm9Support.S    | GCC
-  Arm9Support.asm  | RVCT
-
-  Arm9Lib.c
-  Arm9CacheInformation.c
-
-[Packages]
-  ArmPkg/ArmPkg.dec
-  MdePkg/MdePkg.dec
-
-[LibraryClasses]
-  MemoryAllocationLib
-
-[Protocols]
-  gEfiCpuArchProtocolGuid
diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf b/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf
deleted file mode 100644
index 556e3dc5ab..0000000000
--- a/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf
+++ /dev/null
@@ -1,43 +0,0 @@
-#/** @file
-# Semihosting  serail port lib
-#
-# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution. The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = Arm9ArmLibPrePi
-  FILE_GUID                      = e9b6011f-ee15-4e59-ab8f-a819a081fa54
-  MODULE_TYPE                    = DXE_DRIVER
-  VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = ArmLib
-
-[Sources.common]
-  ../Common/Arm/ArmLibSupport.S    | GCC
-  ../Common/Arm/ArmLibSupport.asm  | RVCT
-  ../Common/ArmLib.c
-
-  Arm9Support.S    | GCC
-  Arm9Support.asm  | RVCT
-
-  Arm9Lib.c
-  Arm9CacheInformation.c
-
-[Packages]
-  ArmPkg/ArmPkg.dec
-  MdePkg/MdePkg.dec
-
-[LibraryClasses]
-  PrePiLib
-
-[Protocols]
-  gEfiCpuArchProtocolGuid
diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c b/ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c
deleted file mode 100644
index f0b5060249..0000000000
--- a/ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-  Copyright (c) 2014, ARM Limited. All rights reserved.
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Library/ArmLib.h>
-#include "ArmLibPrivate.h"
-
-ARM_CACHE_TYPE
-EFIAPI
-ArmCacheType (
-  VOID
-  )
-{
-  switch (CACHE_TYPE (ArmCacheInfo ()))
-  {
-    case CACHE_TYPE_WRITE_BACK: return ARM_CACHE_TYPE_WRITE_BACK;
-    default:                    return ARM_CACHE_TYPE_UNKNOWN;
-  }
-}
-
-ARM_CACHE_ARCHITECTURE
-EFIAPI
-ArmCacheArchitecture (
-  VOID
-  )
-{
-  switch (CACHE_ARCHITECTURE (ArmCacheInfo ()))
-  {
-    case CACHE_ARCHITECTURE_UNIFIED:  return ARM_CACHE_ARCHITECTURE_UNIFIED;
-    case CACHE_ARCHITECTURE_SEPARATE: return ARM_CACHE_ARCHITECTURE_SEPARATE;
-    default:                          return ARM_CACHE_ARCHITECTURE_UNKNOWN;
-  }
-}
-
-BOOLEAN
-EFIAPI
-ArmDataCachePresent (
-  VOID
-  )
-{
-  switch (DATA_CACHE_PRESENT (ArmCacheInfo ()))
-  {
-    case CACHE_PRESENT:     return TRUE;
-    case CACHE_NOT_PRESENT: return FALSE;
-    default:                return FALSE;
-  }
-}
-
-UINTN
-EFIAPI
-ArmDataCacheSize (
-  VOID
-  )
-{
-  switch (DATA_CACHE_SIZE (ArmCacheInfo ()))
-  {
-    case CACHE_SIZE_4_KB:   return   4 * 1024;
-    case CACHE_SIZE_8_KB:   return   8 * 1024;
-    case CACHE_SIZE_16_KB:  return  16 * 1024;
-    case CACHE_SIZE_32_KB:  return  32 * 1024;
-    case CACHE_SIZE_64_KB:  return  64 * 1024;
-    case CACHE_SIZE_128_KB: return 128 * 1024;
-    default:                return   0;
-  }
-}
-
-UINTN
-EFIAPI
-ArmDataCacheAssociativity (
-  VOID
-  )
-{
-  switch (DATA_CACHE_ASSOCIATIVITY (ArmCacheInfo ()))
-  {
-    case CACHE_ASSOCIATIVITY_4_WAY:   return 4;
-    case CACHE_ASSOCIATIVITY_DIRECT:  return 1;
-    default:                          return 0;
-  }
-}
-
-UINTN
-EFIAPI
-ArmDataCacheLineLength (
-  VOID
-  )
-{
-  switch (DATA_CACHE_LINE_LENGTH (ArmCacheInfo ()))
-  {
-    case CACHE_LINE_LENGTH_32_BYTES: return 32;
-    default:                         return  0;
-  }
-}
-
-BOOLEAN
-EFIAPI
-ArmInstructionCachePresent (
-  VOID
-  )
-{
-  switch (INSTRUCTION_CACHE_PRESENT (ArmCacheInfo ()))
-  {
-    case CACHE_PRESENT:     return TRUE;
-    case CACHE_NOT_PRESENT: return FALSE;
-    default:                return FALSE;
-  }
-}
-
-UINTN
-EFIAPI
-ArmInstructionCacheSize (
-  VOID
-  )
-{
-  switch (INSTRUCTION_CACHE_SIZE (ArmCacheInfo ()))
-  {
-    case CACHE_SIZE_4_KB:   return   4 * 1024;
-    case CACHE_SIZE_8_KB:   return   8 * 1024;
-    case CACHE_SIZE_16_KB:  return  16 * 1024;
-    case CACHE_SIZE_32_KB:  return  32 * 1024;
-    case CACHE_SIZE_64_KB:  return  64 * 1024;
-    case CACHE_SIZE_128_KB: return 128 * 1024;
-    default:                return   0;
-  }
-}
-
-UINTN
-EFIAPI
-ArmInstructionCacheAssociativity (
-  VOID
-  )
-{
-  switch (INSTRUCTION_CACHE_ASSOCIATIVITY (ArmCacheInfo ()))
-  {
-    case CACHE_ASSOCIATIVITY_8_WAY:   return 8;
-    case CACHE_ASSOCIATIVITY_4_WAY:   return 4;
-    case CACHE_ASSOCIATIVITY_DIRECT:  return 1;
-    default:                          return 0;
-  }
-}
-
-UINTN
-EFIAPI
-ArmInstructionCacheLineLength (
-  VOID
-  )
-{
-  switch (INSTRUCTION_CACHE_LINE_LENGTH (ArmCacheInfo ()))
-  {
-    case CACHE_LINE_LENGTH_32_BYTES: return 32;
-    default:                         return  0;
-  }
-}
-
-
diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9Lib.c b/ArmPkg/Library/ArmLib/Arm9/Arm9Lib.c
deleted file mode 100644
index 7432f7b678..0000000000
--- a/ArmPkg/Library/ArmLib/Arm9/Arm9Lib.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-  Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Chipset/ARM926EJ-S.h>
-#include <Library/ArmLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/DebugLib.h>
-
-VOID
-FillTranslationTable (
-  IN  UINT32                        *TranslationTable,
-  IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryRegion
-  )
-{
-  UINT32  *Entry;
-  UINTN   Sections;
-  UINTN   Index;
-  UINT32  Attributes;
-  UINT32  PhysicalBase = MemoryRegion->PhysicalBase;
-
-  switch (MemoryRegion->Attributes) {
-    case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
-      Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;
-      break;
-    case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
-      Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;
-      break;
-    case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
-      Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;
-      break;
-    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
-    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
-    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
-      ASSERT(0); // Trustzone is not supported on ARMv5
-    default:
-      Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;
-      break;
-  }
-
-  Entry    = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
-  Sections = MemoryRegion->Length / TT_DESCRIPTOR_SECTION_SIZE;
-
-  // The current code does not support memory region size that is not aligned on TT_DESCRIPTOR_SECTION_SIZE boundary
-  ASSERT (MemoryRegion->Length % TT_DESCRIPTOR_SECTION_SIZE == 0);
-
-  for (Index = 0; Index < Sections; Index++)
-  {
-    *Entry++     =  TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
-    PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
-  }
-}
-
-RETURN_STATUS
-EFIAPI
-ArmConfigureMmu (
-  IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,
-  OUT VOID                         **TranslationTableBase OPTIONAL,
-  OUT UINTN                         *TranslationTableSize OPTIONAL
-  )
-{
-  VOID  *TranslationTable;
-
-  // Allocate pages for translation table.
-  TranslationTable = AllocatePages (EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
-  if (TranslationTable == NULL) {
-    return RETURN_OUT_OF_RESOURCES;
-  }
-  TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
-
-  if (TranslationTableBase != NULL) {
-    *TranslationTableBase = TranslationTable;
-  }
-
-  if (TranslationTableBase != NULL) {
-    *TranslationTableSize = TRANSLATION_TABLE_SIZE;
-  }
-
-  ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
-
-  ArmCleanInvalidateDataCache();
-  ArmInvalidateInstructionCache();
-  ArmInvalidateTlb();
-
-  ArmDisableDataCache();
-  ArmDisableInstructionCache();
-  ArmDisableMmu();
-
-  // Make sure nothing sneaked into the cache
-  ArmCleanInvalidateDataCache();
-  ArmInvalidateInstructionCache();
-
-  while (MemoryTable->Length != 0) {
-    FillTranslationTable(TranslationTable, MemoryTable);
-    MemoryTable++;
-  }
-
-  ArmSetTTBR0(TranslationTable);
-
-  ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
-                            DOMAIN_ACCESS_CONTROL_NONE(14) |
-                            DOMAIN_ACCESS_CONTROL_NONE(13) |
-                            DOMAIN_ACCESS_CONTROL_NONE(12) |
-                            DOMAIN_ACCESS_CONTROL_NONE(11) |
-                            DOMAIN_ACCESS_CONTROL_NONE(10) |
-                            DOMAIN_ACCESS_CONTROL_NONE( 9) |
-                            DOMAIN_ACCESS_CONTROL_NONE( 8) |
-                            DOMAIN_ACCESS_CONTROL_NONE( 7) |
-                            DOMAIN_ACCESS_CONTROL_NONE( 6) |
-                            DOMAIN_ACCESS_CONTROL_NONE( 5) |
-                            DOMAIN_ACCESS_CONTROL_NONE( 4) |
-                            DOMAIN_ACCESS_CONTROL_NONE( 3) |
-                            DOMAIN_ACCESS_CONTROL_NONE( 2) |
-                            DOMAIN_ACCESS_CONTROL_NONE( 1) |
-                            DOMAIN_ACCESS_CONTROL_MANAGER(0));
-
-  ArmEnableInstructionCache();
-  ArmEnableDataCache();
-  ArmEnableMmu();
-
-  return RETURN_SUCCESS;
-}
diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9Support.S b/ArmPkg/Library/ArmLib/Arm9/Arm9Support.S
deleted file mode 100644
index c708d212a9..0000000000
--- a/ArmPkg/Library/ArmLib/Arm9/Arm9Support.S
+++ /dev/null
@@ -1,153 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution.  The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
-
-.text
-.align 2
-GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)
-GCC_ASM_EXPORT(ArmCleanDataCache)
-GCC_ASM_EXPORT(ArmInvalidateDataCache)
-GCC_ASM_EXPORT(ArmInvalidateInstructionCache)
-GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)
-GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)
-GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)
-GCC_ASM_EXPORT(ArmEnableMmu)
-GCC_ASM_EXPORT(ArmDisableMmu)
-GCC_ASM_EXPORT(ArmMmuEnabled)
-GCC_ASM_EXPORT(ArmEnableDataCache)
-GCC_ASM_EXPORT(ArmDisableDataCache)
-GCC_ASM_EXPORT(ArmEnableInstructionCache)
-GCC_ASM_EXPORT(ArmDisableInstructionCache)
-GCC_ASM_EXPORT(ArmEnableBranchPrediction)
-GCC_ASM_EXPORT(ArmDisableBranchPrediction)
-GCC_ASM_EXPORT(ArmDataMemoryBarrier)
-GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)
-GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)
-
-
-.set DC_ON, (1<<2)
-.set IC_ON, (1<<12)
-
-#------------------------------------------------------------------------------
-
-ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
-  mcr     p15, 0, r0, c7, c6, 1   @ invalidate single data cache line
-  bx      lr
-
-ASM_PFX(ArmCleanDataCacheEntryByMVA):
-  mcr     p15, 0, r0, c7, c10, 1  @ clean single data cache line
-  bx      lr
-
-ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
-  mcr     p15, 0, r0, c7, c14, 1  @ clean and invalidate single data cache line
-  bx      lr
-
-ASM_PFX(ArmEnableInstructionCache):
-  ldr    r1,=IC_ON
-  mrc    p15,0,r0,c1,c0,0     @Read control register configuration data
-  orr    r0,r0,r1             @Set I bit
-  mcr    p15,0,r0,c1,c0,0     @Write control register configuration data
-  bx     LR
-
-ASM_PFX(ArmDisableInstructionCache):
-  ldr    r1,=IC_ON
-  mrc    p15,0,r0,c1,c0,0     @Read control register configuration data
-  bic    r0,r0,r1             @Clear I bit.
-  mcr    p15,0,r0,c1,c0,0     @Write control register configuration data
-  bx     LR
-
-ASM_PFX(ArmInvalidateInstructionCache):
-  mov     r0,#0
-  mcr     p15,0,r0,c7,c5,0     @Invalidate entire Instruction cache.
-                         @Also flushes the branch target cache.
-  mov     r0,#0
-  mcr     p15,0,r0,c7,c10,4    @Data write buffer
-  bx      LR
-
-ASM_PFX(ArmEnableMmu):
-  mrc     p15,0,R0,c1,c0,0
-  orr     R0,R0,#1
-  mcr     p15,0,R0,c1,c0,0
-  bx      LR
-
-ASM_PFX(ArmMmuEnabled):
-  mrc     p15,0,R0,c1,c0,0
-  and     R0,R0,#1
-  bx      LR
-
-ASM_PFX(ArmDisableMmu):
-  mrc     p15,0,R0,c1,c0,0
-  bic     R0,R0,#1
-  mcr     p15,0,R0,c1,c0,0
-  mov     R0,#0
-  mcr     p15,0,R0,c7,c10,4     @Drain write buffer
-  bx      LR
-
-ASM_PFX(ArmEnableDataCache):
-  ldr     R1,=DC_ON
-  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
-  orr     R0,R0,R1              @Set C bit
-  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
-  bx      LR
-
-ASM_PFX(ArmDisableDataCache):
-  ldr     R1,=DC_ON
-  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
-  bic     R0,R0,R1              @Clear C bit
-  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
-  bx      LR
-
-ASM_PFX(ArmCleanDataCache):
-  mrc     p15,0,r15,c7,c10,3
-  bne     ASM_PFX(ArmCleanDataCache)
-  mov     R0,#0
-  mcr     p15,0,R0,c7,c10,4  @Drain write buffer
-  bx      LR
-
-ASM_PFX(ArmInvalidateDataCache):
-  mov     R0,#0
-  mcr     p15,0,R0,c7,c6,0        @Invalidate entire data cache
-  mov     R0,#0
-  mcr     p15,0,R0,c7,c10,4       @Drain write buffer
-  bx      LR
-
-ASM_PFX(ArmCleanInvalidateDataCache):
-  mrc     p15,0,r15,c7,c14,3
-  bne     ASM_PFX(ArmCleanInvalidateDataCache)
-  mov     R0,#0
-  mcr     p15,0,R0,c7,c10,4        @Drain write buffer
-  bx      LR
-
-ASM_PFX(ArmEnableBranchPrediction):
-  bx      LR                      @Branch prediction is not supported.
-
-ASM_PFX(ArmDisableBranchPrediction):
-  bx      LR                      @Branch prediction is not supported.
-
-ASM_PFX(ArmDataMemoryBarrier):
-  mov R0, #0
-  mcr P15, #0, R0, C7, C10, #5    @ check if this is OK?
-  bx      LR
-
-ASM_PFX(ArmDataSyncronizationBarrier):
-  mov R0, #0
-  mcr P15, #0, R0, C7, C10, #4   @ check if this is OK?
-  bx      LR
-
-ASM_PFX(ArmInstructionSynchronizationBarrier):
-  mov R0, #0
-  mcr P15, #0, R0, C7, C5, #4     @ check if this is OK?
-  bx      LR
-
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED
-
diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm b/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm
deleted file mode 100644
index 4aaa546ca0..0000000000
--- a/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm
+++ /dev/null
@@ -1,153 +0,0 @@
-//------------------------------------------------------------------------------
-//
-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-//
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution.  The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//------------------------------------------------------------------------------
-
-    EXPORT  ArmCleanInvalidateDataCache
-    EXPORT  ArmCleanDataCache
-    EXPORT  ArmInvalidateDataCache
-    EXPORT  ArmInvalidateInstructionCache
-    EXPORT  ArmInvalidateDataCacheEntryByMVA
-    EXPORT  ArmCleanDataCacheEntryByMVA
-    EXPORT  ArmCleanInvalidateDataCacheEntryByMVA
-    EXPORT  ArmEnableMmu
-    EXPORT  ArmDisableMmu
-    EXPORT  ArmMmuEnabled
-    EXPORT  ArmEnableDataCache
-    EXPORT  ArmDisableDataCache
-    EXPORT  ArmEnableInstructionCache
-    EXPORT  ArmDisableInstructionCache
-    EXPORT  ArmEnableBranchPrediction
-    EXPORT  ArmDisableBranchPrediction
-    EXPORT  ArmDataMemoryBarrier
-    EXPORT  ArmDataSyncronizationBarrier
-    EXPORT  ArmInstructionSynchronizationBarrier
-
-
-DC_ON       EQU     ( 0x1:SHL:2 )
-IC_ON       EQU     ( 0x1:SHL:12 )
-
-    AREA    ArmCacheLib, CODE, READONLY
-    PRESERVE8
-
-
-ArmInvalidateDataCacheEntryByMVA
-  MCR     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line
-  BX      lr
-
-
-ArmCleanDataCacheEntryByMVA
-  MCR     p15, 0, r0, c7, c10, 1  ; clean single data cache line
-  BX      lr
-
-
-ArmCleanInvalidateDataCacheEntryByMVA
-  MCR     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line
-  BX      lr
-
-ArmEnableInstructionCache
-  LDR     R1,=IC_ON
-  MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data
-  ORR     R0,R0,R1             ;Set I bit
-  MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data
-  BX      LR
-
-ArmDisableInstructionCache
-  LDR     R1,=IC_ON
-  MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data
-  BIC     R0,R0,R1             ;Clear I bit.
-  MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data
-  BX      LR
-
-ArmInvalidateInstructionCache
-  MOV     R0,#0
-  MCR     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache
-  MOV     R0,#0
-  MCR     p15,0,R0,c7,c10,4     ;Drain write buffer
-  BX      LR
-
-ArmEnableMmu
-  mrc     p15,0,R0,c1,c0,0
-  orr     R0,R0,#1
-  mcr     p15,0,R0,c1,c0,0
-  bx      LR
-
-ArmMmuEnabled
-  mrc     p15,0,R0,c1,c0,0
-  and     R0,R0,#1
-  bx      LR
-
-ArmDisableMmu
-  mrc     p15,0,R0,c1,c0,0
-  bic     R0,R0,#1
-  mcr     p15,0,R0,c1,c0,0
-  mov     R0,#0
-  mcr     p15,0,R0,c7,c10,4     ;Drain write buffer
-  bx      LR
-
-ArmEnableDataCache
-  LDR     R1,=DC_ON
-  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
-  ORR     R0,R0,R1              ;Set C bit
-  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
-  BX      LR
-
-ArmDisableDataCache
-  LDR     R1,=DC_ON
-  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
-  BIC     R0,R0,R1              ;Clear C bit
-  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
-  BX      LR
-
-ArmCleanDataCache
-  MRC     p15,0,r15,c7,c10,3
-  BNE     ArmCleanDataCache
-  MOV     R0,#0
-  MCR     p15,0,R0,c7,c10,4      ;Drain write buffer
-  BX      LR
-
-ArmInvalidateDataCache
-  MOV     R0,#0
-  MCR     p15,0,R0,c7,c6,0      ;Invalidate entire data cache
-  MOV     R0,#0
-  MCR     p15,0,R0,c7,c10,4     ;Drain write buffer
-  BX      LR
-
-ArmCleanInvalidateDataCache
-  MRC     p15,0,r15,c7,c14,3
-  BNE     ArmCleanInvalidateDataCache
-  MOV     R0,#0
-  MCR     p15,0,R0,c7,c10,4      ;Drain write buffer
-  BX      LR
-
-ArmEnableBranchPrediction
-  bx      LR                    ;Branch prediction is not supported.
-
-ArmDisableBranchPrediction
-  bx      LR                    ;Branch prediction is not supported.
-
-ASM_PFX(ArmDataMemoryBarrier):
-  mov R0, #0
-  mcr P15, #0, R0, C7, C10, #5  ; Check to see if this is correct
-  bx      LR
-
-ASM_PFX(ArmDataSyncronizationBarrier):
-  mov R0, #0
-  mcr P15, #0, R0, C7, C10, #4 ; Check to see if this is correct
-  bx      LR
-
-ASM_PFX(ArmInstructionSynchronizationBarrier):
-  MOV R0, #0
-  MCR P15, #0, R0, C7, C5, #4 ; Check to see if this is correct
-  bx      LR
-
-    END
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S
deleted file mode 100644
index b94239f785..0000000000
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S
+++ /dev/null
@@ -1,113 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution.  The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
-
-#include <AsmMacroIoLib.h>
-
-.text
-.align 2
-
-GCC_ASM_EXPORT(ArmIsMpCore)
-GCC_ASM_EXPORT(ArmEnableAsynchronousAbort)
-GCC_ASM_EXPORT(ArmDisableAsynchronousAbort)
-GCC_ASM_EXPORT(ArmEnableIrq)
-GCC_ASM_EXPORT(ArmDisableIrq)
-GCC_ASM_EXPORT(ArmEnableFiq)
-GCC_ASM_EXPORT(ArmDisableFiq)
-GCC_ASM_EXPORT(ArmEnableInterrupts)
-GCC_ASM_EXPORT(ArmDisableInterrupts)
-GCC_ASM_EXPORT(ReadCCSIDR)
-GCC_ASM_EXPORT(ReadCLIDR)
-GCC_ASM_EXPORT(ArmReadNsacr)
-GCC_ASM_EXPORT(ArmWriteNsacr)
-
-#------------------------------------------------------------------------------
-
-ASM_PFX(ArmIsMpCore):
-  mrc     p15,0,R0,c0,c0,5
-  // Get Multiprocessing extension (bit31) & U bit (bit30)
-  and     R0, R0, #0xC0000000
-  // if (bit31 == 1) && (bit30 == 0) then the processor is part of a multiprocessor system
-  cmp     R0, #0x80000000
-  moveq   R0, #1
-  movne   R0, #0
-  bx      LR
-
-ASM_PFX(ArmEnableAsynchronousAbort):
-  cpsie   a
-  isb
-  bx      LR
-
-ASM_PFX(ArmDisableAsynchronousAbort):
-  cpsid   a
-  isb
-  bx      LR
-
-ASM_PFX(ArmEnableIrq):
-  cpsie   i
-  isb
-  bx      LR
-
-ASM_PFX(ArmDisableIrq):
-  cpsid   i
-  isb
-  bx      LR
-
-ASM_PFX(ArmEnableFiq):
-  cpsie   f
-  isb
-  bx      LR
-
-ASM_PFX(ArmDisableFiq):
-  cpsid   f
-  isb
-  bx      LR
-
-ASM_PFX(ArmEnableInterrupts):
-  cpsie   if
-  isb
-  bx      LR
-
-ASM_PFX(ArmDisableInterrupts):
-  cpsid   if
-  isb
-  bx      LR
-
-// UINT32
-// ReadCCSIDR (
-//   IN UINT32 CSSELR
-//   )
-ASM_PFX(ReadCCSIDR):
-  mcr p15,2,r0,c0,c0,0   @ Write Cache Size Selection Register (CSSELR)
-  isb
-  mrc p15,1,r0,c0,c0,0   @ Read current CP15 Cache Size ID Register (CCSIDR)
-  bx  lr
-
-// UINT32
-// ReadCLIDR (
-//   IN UINT32 CSSELR
-//   )
-ASM_PFX(ReadCLIDR):
-  mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
-  bx  lr
-
-ASM_PFX(ArmReadNsacr):
-  mrc     p15, 0, r0, c1, c1, 2
-  bx      lr
-
-ASM_PFX(ArmWriteNsacr):
-  mcr     p15, 0, r0, c1, c1, 2
-  bx      lr
-
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm
deleted file mode 100644
index 82daa3ce16..0000000000
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm
+++ /dev/null
@@ -1,112 +0,0 @@
-//------------------------------------------------------------------------------
-//
-// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-// Copyright (c) 2011-2013, ARM Limited. All rights reserved.
-//
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution.  The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//------------------------------------------------------------------------------
-
-
-    EXPORT  ArmIsMpCore
-    EXPORT  ArmEnableAsynchronousAbort
-    EXPORT  ArmDisableAsynchronousAbort
-    EXPORT  ArmEnableIrq
-    EXPORT  ArmDisableIrq
-    EXPORT  ArmEnableFiq
-    EXPORT  ArmDisableFiq
-    EXPORT  ArmEnableInterrupts
-    EXPORT  ArmDisableInterrupts
-    EXPORT  ReadCCSIDR
-    EXPORT  ReadCLIDR
-    EXPORT  ArmReadNsacr
-    EXPORT  ArmWriteNsacr
-
-    AREA ArmLibSupportV7, CODE, READONLY
-
-
-//------------------------------------------------------------------------------
-
-ArmIsMpCore
-  mrc     p15,0,R0,c0,c0,5
-  // Get Multiprocessing extension (bit31) & U bit (bit30)
-  and     R0, R0, #0xC0000000
-  // if (bit31 == 1) && (bit30 == 0) then the processor is part of a multiprocessor system
-  cmp     R0, #0x80000000
-  moveq   R0, #1
-  movne   R0, #0
-  bx      LR
-
-ArmEnableAsynchronousAbort
-  cpsie   a
-  isb
-  bx      LR
-
-ArmDisableAsynchronousAbort
-  cpsid   a
-  isb
-  bx      LR
-
-ArmEnableIrq
-  cpsie   i
-  isb
-  bx      LR
-
-ArmDisableIrq
-  cpsid   i
-  isb
-  bx      LR
-
-ArmEnableFiq
-  cpsie   f
-  isb
-  bx      LR
-
-ArmDisableFiq
-  cpsid   f
-  isb
-  bx      LR
-
-ArmEnableInterrupts
-  cpsie   if
-  isb
-  bx      LR
-
-ArmDisableInterrupts
-  cpsid   if
-  isb
-  bx      LR
-
-// UINT32
-// ReadCCSIDR (
-//   IN UINT32 CSSELR
-//   )
-ReadCCSIDR
-  mcr p15,2,r0,c0,c0,0   ; Write Cache Size Selection Register (CSSELR)
-  isb
-  mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
-  bx  lr
-
-// UINT32
-// ReadCLIDR (
-//   IN UINT32 CSSELR
-//   )
-ReadCLIDR
-  mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
-  bx  lr
-
-ArmReadNsacr
-  mrc     p15, 0, r0, c1, c1, 2
-  bx      lr
-
-ArmWriteNsacr
-  mcr     p15, 0, r0, c1, c1, 2
-  bx      lr
-
-  END
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimer.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimer.c
deleted file mode 100644
index 49be71bbe0..0000000000
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimer.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/** @file
-*
-*  Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
-*
-*  This program and the accompanying materials
-*  are licensed and made available under the terms and conditions of the BSD License
-*  which accompanies this distribution.  The full text of the license may be found at
-*  http://opensource.org/licenses/bsd-license.php
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Uefi.h>
-#include <Chipset/ArmV7.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/ArmLib.h>
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-#include "ArmV7Lib.h"
-#include "ArmLibPrivate.h"
-#include <Library/ArmArchTimer.h>
-
-VOID
-EFIAPI
-ArmArchTimerReadReg (
-    IN   ARM_ARCH_TIMER_REGS   Reg,
-    OUT  VOID                  *DstBuf
-    )
-{
-  // Check if the Generic/Architecture timer is implemented
-  if (ArmIsArchTimerImplemented ()) {
-    switch (Reg) {
-    case CntFrq:
-      *((UINTN *)DstBuf) = ArmReadCntFrq ();
-      return;
-
-    case CntPct:
-      *((UINT64 *)DstBuf) = ArmReadCntPct ();
-      return;
-
-    case CntkCtl:
-      *((UINTN *)DstBuf) = ArmReadCntkCtl();
-      return;
-
-    case CntpTval:
-      *((UINTN *)DstBuf) = ArmReadCntpTval ();
-      return;
-
-    case CntpCtl:
-      *((UINTN *)DstBuf) = ArmReadCntpCtl ();
-      return;
-
-    case CntvTval:
-      *((UINTN *)DstBuf) = ArmReadCntvTval ();
-      return;
-
-    case CntvCtl:
-      *((UINTN *)DstBuf) = ArmReadCntvCtl ();
-      return;
-
-    case CntvCt:
-      *((UINT64 *)DstBuf) = ArmReadCntvCt ();
-      return;
-
-    case CntpCval:
-      *((UINT64 *)DstBuf) = ArmReadCntpCval ();
-      return;
-
-    case CntvCval:
-      *((UINT64 *)DstBuf) = ArmReadCntvCval ();
-      return;
-
-    case CntvOff:
-      *((UINT64 *)DstBuf) = ArmReadCntvOff ();
-      return;
-
-    case CnthCtl:
-    case CnthpTval:
-    case CnthpCtl:
-    case CnthpCval:
-      DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));
-      break;
-
-    default:
-      DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));
-    }
-  } else {
-    DEBUG ((EFI_D_ERROR, "Attempt to read ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));
-    ASSERT (0);
-  }
-
-  *((UINT64 *)DstBuf) = 0;
-}
-
-VOID
-EFIAPI
-ArmArchTimerWriteReg (
-    IN   ARM_ARCH_TIMER_REGS   Reg,
-    IN   VOID                  *SrcBuf
-    )
-{
-  // Check if the Generic/Architecture timer is implemented
-  if (ArmIsArchTimerImplemented ()) {
-
-    switch (Reg) {
-
-    case CntFrq:
-      ArmWriteCntFrq (*((UINTN *)SrcBuf));
-      break;
-
-    case CntPct:
-      DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTPCT \n"));
-      break;
-
-    case CntkCtl:
-      ArmWriteCntkCtl (*((UINTN *)SrcBuf));
-      break;
-
-    case CntpTval:
-      ArmWriteCntpTval (*((UINTN *)SrcBuf));
-      break;
-
-    case CntpCtl:
-      ArmWriteCntpCtl (*((UINTN *)SrcBuf));
-      break;
-
-    case CntvTval:
-      ArmWriteCntvTval (*((UINTN *)SrcBuf));
-      break;
-
-    case CntvCtl:
-      ArmWriteCntvCtl (*((UINTN *)SrcBuf));
-      break;
-
-    case CntvCt:
-      DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTVCT \n"));
-      break;
-
-    case CntpCval:
-      ArmWriteCntpCval (*((UINT64 *)SrcBuf) );
-      break;
-
-    case CntvCval:
-      ArmWriteCntvCval (*((UINT64 *)SrcBuf) );
-      break;
-
-    case CntvOff:
-      ArmWriteCntvOff (*((UINT64 *)SrcBuf));
-      break;
-
-    case CnthCtl:
-    case CnthpTval:
-    case CnthpCtl:
-    case CnthpCval:
-      DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));
-      break;
-
-    default:
-      DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));
-    }
-  } else {
-    DEBUG ((EFI_D_ERROR, "Attempt to write to ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));
-    ASSERT (0);
-  }
-}
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.S
deleted file mode 100644
index ec4ede5250..0000000000
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.S
+++ /dev/null
@@ -1,119 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (c) 2011, ARM Limited. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution.  The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
-
-.text
-.align 2
-
-GCC_ASM_EXPORT (ArmReadCntFrq)
-GCC_ASM_EXPORT (ArmWriteCntFrq)
-GCC_ASM_EXPORT (ArmReadCntPct)
-GCC_ASM_EXPORT (ArmReadCntkCtl)
-GCC_ASM_EXPORT (ArmWriteCntkCtl)
-GCC_ASM_EXPORT (ArmReadCntpTval)
-GCC_ASM_EXPORT (ArmWriteCntpTval)
-GCC_ASM_EXPORT (ArmReadCntpCtl)
-GCC_ASM_EXPORT (ArmWriteCntpCtl)
-GCC_ASM_EXPORT (ArmReadCntvTval)
-GCC_ASM_EXPORT (ArmWriteCntvTval)
-GCC_ASM_EXPORT (ArmReadCntvCtl)
-GCC_ASM_EXPORT (ArmWriteCntvCtl)
-GCC_ASM_EXPORT (ArmReadCntvCt)
-GCC_ASM_EXPORT (ArmReadCntpCval)
-GCC_ASM_EXPORT (ArmWriteCntpCval)
-GCC_ASM_EXPORT (ArmReadCntvCval)
-GCC_ASM_EXPORT (ArmWriteCntvCval)
-GCC_ASM_EXPORT (ArmReadCntvOff)
-GCC_ASM_EXPORT (ArmWriteCntvOff)
-
-ASM_PFX(ArmReadCntFrq):
-  mrc    p15, 0, r0, c14, c0, 0    @ Read CNTFRQ
-  bx     lr
-
-ASM_PFX(ArmWriteCntFrq):
-  mcr    p15, 0, r0, c14, c0, 0    @ Write to CNTFRQ
-  bx     lr
-
-ASM_PFX(ArmReadCntPct):
-  mrrc   p15, 0, r0, r1, c14       @ Read CNTPT (Physical counter register)
-  bx     lr
-
-ASM_PFX(ArmReadCntkCtl):
-  mrc    p15, 0, r0, c14, c1, 0    @ Read CNTK_CTL (Timer PL1 Control Register)
-  bx     lr
-
-ASM_PFX(ArmWriteCntkCtl):
-  mcr    p15, 0, r0, c14, c1, 0    @ Write to CNTK_CTL (Timer PL1 Control Register)
-  bx     lr
-
-ASM_PFX(ArmReadCntpTval):
-  mrc    p15, 0, r0, c14, c2, 0    @ Read CNTP_TVAL (PL1 physical timer value register)
-  bx     lr
-
-ASM_PFX(ArmWriteCntpTval):
-  mcr    p15, 0, r0, c14, c2, 0    @ Write to CNTP_TVAL (PL1 physical timer value register)
-  bx     lr
-
-ASM_PFX(ArmReadCntpCtl):
-  mrc    p15, 0, r0, c14, c2, 1    @ Read CNTP_CTL (PL1 Physical Timer Control Register)
-  bx     lr
-
-ASM_PFX(ArmWriteCntpCtl):
-  mcr    p15, 0, r0, c14, c2, 1    @ Write to  CNTP_CTL (PL1 Physical Timer Control Register)
-  bx     lr
-
-ASM_PFX(ArmReadCntvTval):
-  mrc    p15, 0, r0, c14, c3, 0    @ Read CNTV_TVAL (Virtual Timer Value register)
-  bx     lr
-
-ASM_PFX(ArmWriteCntvTval):
-  mcr    p15, 0, r0, c14, c3, 0    @ Write to CNTV_TVAL (Virtual Timer Value register)
-  bx     lr
-
-ASM_PFX(ArmReadCntvCtl):
-  mrc    p15, 0, r0, c14, c3, 1    @ Read CNTV_CTL (Virtual Timer Control Register)
-  bx     lr
-
-ASM_PFX(ArmWriteCntvCtl):
-  mcr    p15, 0, r0, c14, c3, 1    @ Write to CNTV_CTL (Virtual Timer Control Register)
-  bx     lr
-
-ASM_PFX(ArmReadCntvCt):
-  mrrc   p15, 1, r0, r1, c14       @ Read CNTVCT  (Virtual Count Register)
-  bx     lr
-
-ASM_PFX(ArmReadCntpCval):
-  mrrc   p15, 2, r0, r1, c14       @ Read CNTP_CTVAL (Physical Timer Compare Value Register)
-  bx     lr
-
-ASM_PFX(ArmWriteCntpCval):
-  mcrr   p15, 2, r0, r1, c14       @ Write to CNTP_CTVAL (Physical Timer Compare Value Register)
-  bx     lr
-
-ASM_PFX(ArmReadCntvCval):
-  mrrc   p15, 3, r0, r1, c14       @ Read CNTV_CTVAL (Virtual Timer Compare Value Register)
-  bx     lr
-
-ASM_PFX(ArmWriteCntvCval):
-  mcrr   p15, 3, r0, r1, c14       @ write to  CNTV_CTVAL (Virtual Timer Compare Value Register)
-  bx     lr
-
-ASM_PFX(ArmReadCntvOff):
-  mrrc   p15, 4, r0, r1, c14       @ Read CNTVOFF (virtual Offset register)
-  bx     lr
-
-ASM_PFX(ArmWriteCntvOff):
-  mcrr   p15, 4, r0, r1, c14       @ Write to CNTVOFF (Virtual Offset register)
-  bx     lr
-
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.asm
deleted file mode 100644
index 514830d28f..0000000000
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimerSupport.asm
+++ /dev/null
@@ -1,119 +0,0 @@
-//------------------------------------------------------------------------------
-//
-// Copyright (c) 2011, ARM Limited. All rights reserved.
-//
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution.  The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//------------------------------------------------------------------------------
-
-    EXPORT  ArmReadCntFrq
-    EXPORT  ArmWriteCntFrq
-    EXPORT  ArmReadCntPct
-    EXPORT  ArmReadCntkCtl
-    EXPORT  ArmWriteCntkCtl
-    EXPORT  ArmReadCntpTval
-    EXPORT  ArmWriteCntpTval
-    EXPORT  ArmReadCntpCtl
-    EXPORT  ArmWriteCntpCtl
-    EXPORT  ArmReadCntvTval
-    EXPORT  ArmWriteCntvTval
-    EXPORT  ArmReadCntvCtl
-    EXPORT  ArmWriteCntvCtl
-    EXPORT  ArmReadCntvCt
-    EXPORT  ArmReadCntpCval
-    EXPORT  ArmWriteCntpCval
-    EXPORT  ArmReadCntvCval
-    EXPORT  ArmWriteCntvCval
-    EXPORT  ArmReadCntvOff
-    EXPORT  ArmWriteCntvOff
-
-    AREA    ArmV7ArchTimerSupport, CODE, READONLY
-    PRESERVE8
-
-ArmReadCntFrq
-  mrc    p15, 0, r0, c14, c0, 0    ; Read CNTFRQ
-  bx     lr
-
-ArmWriteCntFrq
-  mcr    p15, 0, r0, c14, c0, 0    ; Write to CNTFRQ
-  bx     lr
-
-ArmReadCntPct
-  mrrc   p15, 0, r0, r1, c14       ; Read CNTPT (Physical counter register)
-  bx     lr
-
-ArmReadCntkCtl
-  mrc    p15, 0, r0, c14, c1, 0    ; Read CNTK_CTL (Timer PL1 Control Register)
-  bx     lr
-
-ArmWriteCntkCtl
-  mcr    p15, 0, r0, c14, c1, 0    ; Write to CNTK_CTL (Timer PL1 Control Register)
-  bx     lr
-
-ArmReadCntpTval
-  mrc    p15, 0, r0, c14, c2, 0    ; Read CNTP_TVAL (PL1 physical timer value register)
-  bx     lr
-
-ArmWriteCntpTval
-  mcr    p15, 0, r0, c14, c2, 0    ; Write to CNTP_TVAL (PL1 physical timer value register)
-  bx     lr
-
-ArmReadCntpCtl
-  mrc    p15, 0, r0, c14, c2, 1    ; Read CNTP_CTL (PL1 Physical Timer Control Register)
-  bx     lr
-
-ArmWriteCntpCtl
-  mcr    p15, 0, r0, c14, c2, 1    ; Write to  CNTP_CTL (PL1 Physical Timer Control Register)
-  bx     lr
-
-ArmReadCntvTval
-  mrc    p15, 0, r0, c14, c3, 0    ; Read CNTV_TVAL (Virtual Timer Value register)
-  bx     lr
-
-ArmWriteCntvTval
-  mcr    p15, 0, r0, c14, c3, 0    ; Write to CNTV_TVAL (Virtual Timer Value register)
-  bx     lr
-
-ArmReadCntvCtl
-  mrc    p15, 0, r0, c14, c3, 1    ; Read CNTV_CTL (Virtual Timer Control Register)
-  bx     lr
-
-ArmWriteCntvCtl
-  mcr    p15, 0, r0, c14, c3, 1    ; Write to CNTV_CTL (Virtual Timer Control Register)
-  bx     lr
-
-ArmReadCntvCt
-  mrrc   p15, 1, r0, r1, c14       ; Read CNTVCT  (Virtual Count Register)
-  bx     lr
-
-ArmReadCntpCval
-  mrrc   p15, 2, r0, r1, c14       ; Read CNTP_CTVAL (Physical Timer Compare Value Register)
-  bx     lr
-
-ArmWriteCntpCval
-  mcrr   p15, 2, r0, r1, c14       ; Write to CNTP_CTVAL (Physical Timer Compare Value Register)
-  bx     lr
-
-ArmReadCntvCval
-  mrrc   p15, 3, r0, r1, c14       ; Read CNTV_CTVAL (Virtual Timer Compare Value Register)
-  bx     lr
-
-ArmWriteCntvCval
-  mcrr   p15, 3, r0, r1, c14       ; write to  CNTV_CTVAL (Virtual Timer Compare Value Register)
-  bx     lr
-
-ArmReadCntvOff
-  mrrc   p15, 4, r0, r1, c14       ; Read CNTVOFF (virtual Offset register)
-  bx     lr
-
-ArmWriteCntvOff
-  mcrr   p15, 4, r0, r1, c14       ; Write to CNTVOFF (Virtual Offset register)
-  bx     lr
-
- END
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c
deleted file mode 100644
index feb60881bd..0000000000
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c
+++ /dev/null
@@ -1,269 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-  Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-#include <Uefi.h>
-#include <Chipset/ArmV7.h>
-#include <Library/ArmLib.h>
-#include <Library/BaseLib.h>
-#include <Library/IoLib.h>
-#include "ArmV7Lib.h"
-#include "ArmLibPrivate.h"
-
-ARM_CACHE_TYPE
-EFIAPI
-ArmCacheType (
-  VOID
-  )
-{
-  return ARM_CACHE_TYPE_WRITE_BACK;
-}
-
-ARM_CACHE_ARCHITECTURE
-EFIAPI
-ArmCacheArchitecture (
-  VOID
-  )
-{
-  UINT32 CLIDR = ReadCLIDR ();
-
-  return (ARM_CACHE_ARCHITECTURE)CLIDR; // BugBug Fix Me
-}
-
-BOOLEAN
-EFIAPI
-ArmDataCachePresent (
-  VOID
-  )
-{
-  UINT32 CLIDR = ReadCLIDR ();
-
-  if ((CLIDR & 0x2) == 0x2) {
-    // Instruction cache exists
-    return TRUE;
-  }
-  if ((CLIDR & 0x7) == 0x4) {
-    // Unified cache
-    return TRUE;
-  }
-
-  return FALSE;
-}
-
-UINTN
-EFIAPI
-ArmDataCacheSize (
-  VOID
-  )
-{
-  UINT32 NumSets;
-  UINT32 Associativity;
-  UINT32 LineSize;
-  UINT32 CCSIDR = ReadCCSIDR (0);
-
-  LineSize      = (1 << ((CCSIDR & 0x7) + 2));
-  Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
-  NumSets       = ((CCSIDR >> 13) & 0x7fff) + 1;
-
-  // LineSize is in words (4 byte chunks)
-  return  NumSets * Associativity * LineSize * 4;
-}
-
-UINTN
-EFIAPI
-ArmDataCacheAssociativity (
-  VOID
-  )
-{
-  UINT32 CCSIDR = ReadCCSIDR (0);
-
-  return ((CCSIDR >> 3) & 0x3ff) + 1;
-}
-
-UINTN
-ArmDataCacheSets (
-  VOID
-  )
-{
-  UINT32 CCSIDR = ReadCCSIDR (0);
-
-  return ((CCSIDR >> 13) & 0x7fff) + 1;
-}
-
-UINTN
-EFIAPI
-ArmDataCacheLineLength (
-  VOID
-  )
-{
-  UINT32 CCSIDR = ReadCCSIDR (0) & 7;
-
-  // * 4 converts to bytes
-  return (1 << (CCSIDR + 2)) * 4;
-}
-
-BOOLEAN
-EFIAPI
-ArmInstructionCachePresent (
-  VOID
-  )
-{
-  UINT32 CLIDR = ReadCLIDR ();
-
-  if ((CLIDR & 1) == 1) {
-    // Instruction cache exists
-    return TRUE;
-  }
-  if ((CLIDR & 0x7) == 0x4) {
-    // Unified cache
-    return TRUE;
-  }
-
-  return FALSE;
-}
-
-UINTN
-EFIAPI
-ArmInstructionCacheSize (
-  VOID
-  )
-{
-  UINT32 NumSets;
-  UINT32 Associativity;
-  UINT32 LineSize;
-  UINT32 CCSIDR = ReadCCSIDR (1);
-
-  LineSize      = (1 << ((CCSIDR & 0x7) + 2));
-  Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
-  NumSets       = ((CCSIDR >> 13) & 0x7fff) + 1;
-
-  // LineSize is in words (4 byte chunks)
-  return  NumSets * Associativity * LineSize * 4;
-}
-
-UINTN
-EFIAPI
-ArmInstructionCacheAssociativity (
-  VOID
-  )
-{
-  UINT32 CCSIDR = ReadCCSIDR (1);
-
-  return ((CCSIDR >> 3) & 0x3ff) + 1;
-//  return 4;
-}
-
-UINTN
-EFIAPI
-ArmInstructionCacheSets (
-  VOID
-  )
-{
-  UINT32 CCSIDR = ReadCCSIDR (1);
-
-  return ((CCSIDR >> 13) & 0x7fff) + 1;
-}
-
-UINTN
-EFIAPI
-ArmInstructionCacheLineLength (
-  VOID
-  )
-{
-  UINT32 CCSIDR = ReadCCSIDR (1) & 7;
-
-  // * 4 converts to bytes
-  return (1 << (CCSIDR + 2)) * 4;
-
-//  return 64;
-}
-
-
-VOID
-ArmV7DataCacheOperation (
-  IN  ARM_V7_CACHE_OPERATION  DataCacheOperation
-  )
-{
-  UINTN     SavedInterruptState;
-
-  SavedInterruptState = ArmGetInterruptState ();
-  ArmDisableInterrupts ();
-
-  ArmV7AllDataCachesOperation (DataCacheOperation);
-
-  ArmDrainWriteBuffer ();
-
-  if (SavedInterruptState) {
-    ArmEnableInterrupts ();
-  }
-}
-
-
-VOID
-ArmV7PoUDataCacheOperation (
-  IN  ARM_V7_CACHE_OPERATION  DataCacheOperation
-  )
-{
-  UINTN     SavedInterruptState;
-
-  SavedInterruptState = ArmGetInterruptState ();
-  ArmDisableInterrupts ();
-
-  ArmV7PerformPoUDataCacheOperation (DataCacheOperation);
-
-  ArmDrainWriteBuffer ();
-
-  if (SavedInterruptState) {
-    ArmEnableInterrupts ();
-  }
-}
-
-VOID
-EFIAPI
-ArmInvalidateDataCache (
-  VOID
-  )
-{
-  ArmDrainWriteBuffer ();
-  ArmV7DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);
-}
-
-VOID
-EFIAPI
-ArmCleanInvalidateDataCache (
-  VOID
-  )
-{
-  ArmDrainWriteBuffer ();
-  ArmV7DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);
-}
-
-VOID
-EFIAPI
-ArmCleanDataCache (
-  VOID
-  )
-{
-  ArmDrainWriteBuffer ();
-  ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
-}
-
-VOID
-EFIAPI
-ArmCleanDataCacheToPoU (
-  VOID
-  )
-{
-  ArmDrainWriteBuffer ();
-  ArmV7PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);
-}
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.h b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.h
deleted file mode 100644
index 1398d75071..0000000000
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __ARM_V7_LIB_H__
-#define __ARM_V7_LIB_H__
-
-typedef VOID (*ARM_V7_CACHE_OPERATION)(UINT32);
-
-
-VOID
-ArmV7PerformPoUDataCacheOperation (
-  IN  ARM_V7_CACHE_OPERATION  DataCacheOperation
-  );
-
-VOID
-ArmV7AllDataCachesOperation (
-  IN  ARM_V7_CACHE_OPERATION  DataCacheOperation
-  );
-
-#endif // __ARM_V7_LIB_H__
-
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
deleted file mode 100644
index 01bdfb6996..0000000000
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
+++ /dev/null
@@ -1,50 +0,0 @@
-#/** @file
-#
-# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-# Copyright (c) 2011, ARM Limited. All rights reserved.
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution. The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = ArmV7Lib
-  FILE_GUID                      = 411cdfd8-f964-4b9d-a3e3-1719a9c15559
-  MODULE_TYPE                    = DXE_DRIVER
-  VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = ArmLib
-
-[Sources.common]
-  ArmLibSupportV7.S    | GCC
-  ArmLibSupportV7.asm  | RVCT
-
-  ../Common/Arm/ArmLibSupport.S    | GCC
-  ../Common/Arm/ArmLibSupport.asm  | RVCT
-  ../Common/ArmLib.c
-
-  ArmV7Support.S    | GCC
-  ArmV7Support.asm  | RVCT
-
-  ArmV7Lib.c
-  ArmV7Mmu.c
-
-  ArmV7ArchTimer.c
-  ArmV7ArchTimerSupport.S    | GCC
-  ArmV7ArchTimerSupport.asm    | RVCT
-
-[Packages]
-  ArmPkg/ArmPkg.dec
-  MdePkg/MdePkg.dec
-
-[LibraryClasses]
-  MemoryAllocationLib
-
-[Protocols]
-  gEfiCpuArchProtocolGuid
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf b/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
deleted file mode 100644
index ac081068db..0000000000
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
+++ /dev/null
@@ -1,50 +0,0 @@
-#/** @file
-# Semihosting  serail port lib
-#
-# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution. The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = ArmV7LibPrePi
-  FILE_GUID                      = A150FA0C-F4E8-4207-9BEB-CD6DFB430D73
-  MODULE_TYPE                    = BASE
-  VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = ArmLib
-
-[Sources.common]
-  ArmLibSupportV7.S    | GCC
-  ArmLibSupportV7.asm  | RVCT
-
-  ../Common/Arm/ArmLibSupport.S    | GCC
-  ../Common/Arm/ArmLibSupport.asm  | RVCT
-  ../Common/ArmLib.c
-
-  ArmV7Support.S    | GCC
-  ArmV7Support.asm  | RVCT
-
-  ArmV7Lib.c
-  ArmV7Mmu.c
-
-  ArmV7ArchTimer.c
-  ArmV7ArchTimerSupport.S    | GCC
-  ArmV7ArchTimerSupport.asm  | RVCT
-
-[Packages]
-  ArmPkg/ArmPkg.dec
-  MdePkg/MdePkg.dec
-
-[LibraryClasses]
-  PrePiLib
-
-[Protocols]
-  gEfiCpuArchProtocolGuid
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf b/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf
deleted file mode 100644
index 5ed325d4ad..0000000000
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf
+++ /dev/null
@@ -1,44 +0,0 @@
-#/* @file
-#  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#*/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = ArmV7LibSec
-  FILE_GUID                      = addd46ad-156a-4309-b134-46a1b14a61bf
-  MODULE_TYPE                    = BASE
-  VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = ArmLib
-
-[Sources.common]
-  ArmLibSupportV7.S    | GCC
-  ArmLibSupportV7.asm  | RVCT
-
-  ../Common/Arm/ArmLibSupport.S    | GCC
-  ../Common/Arm/ArmLibSupport.asm  | RVCT
-  ../Common/ArmLib.c
-
-  ArmV7Support.S    | GCC
-  ArmV7Support.asm  | RVCT
-
-  ArmV7Lib.c
-
-  ArmV7ArchTimer.c
-  ArmV7ArchTimerSupport.S    | GCC
-  ArmV7ArchTimerSupport.asm    | RVCT
-
-[Packages]
-  ArmPkg/ArmPkg.dec
-  MdePkg/MdePkg.dec
-
-[Protocols]
-  gEfiCpuArchProtocolGuid
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
deleted file mode 100644
index d035ff3caa..0000000000
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
+++ /dev/null
@@ -1,303 +0,0 @@
-/** @file
-*  File managing the MMU for ARMv7 architecture
-*
-*  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
-*
-*  This program and the accompanying materials
-*  are licensed and made available under the terms and conditions of the BSD License
-*  which accompanies this distribution.  The full text of the license may be found at
-*  http://opensource.org/licenses/bsd-license.php
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#include <Uefi.h>
-#include <Chipset/ArmV7.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/ArmLib.h>
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-#include "ArmV7Lib.h"
-#include "ArmLibPrivate.h"
-
-UINT32
-ConvertSectionAttributesToPageAttributes (
-  IN UINT32   SectionAttributes,
-  IN BOOLEAN  IsLargePage
-  )
-{
-  UINT32 PageAttributes;
-
-  PageAttributes = 0;
-  PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (SectionAttributes, IsLargePage);
-  PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (SectionAttributes);
-  PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_XN (SectionAttributes, IsLargePage);
-  PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_NG (SectionAttributes);
-  PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_S (SectionAttributes);
-
-  return PageAttributes;
-}
-
-STATIC
-VOID
-PopulateLevel2PageTable (
-  IN UINT32                         *SectionEntry,
-  IN UINT32                         PhysicalBase,
-  IN UINT32                         RemainLength,
-  IN ARM_MEMORY_REGION_ATTRIBUTES   Attributes
-  )
-{
-  UINT32* PageEntry;
-  UINT32  Pages;
-  UINT32  Index;
-  UINT32  PageAttributes;
-  UINT32  SectionDescriptor;
-  UINT32  TranslationTable;
-  UINT32  BaseSectionAddress;
-
-  switch (Attributes) {
-    case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
-    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
-      PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK;
-      break;
-    case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
-    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
-      PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_THROUGH;
-      break;
-    case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
-    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
-      PageAttributes = TT_DESCRIPTOR_PAGE_DEVICE;
-      break;
-    case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
-    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
-      PageAttributes = TT_DESCRIPTOR_PAGE_UNCACHED;
-      break;
-    default:
-      PageAttributes = TT_DESCRIPTOR_PAGE_UNCACHED;
-      break;
-  }
-
-  // Check if the Section Entry has already been populated. Otherwise attach a
-  // Level 2 Translation Table to it
-  if (*SectionEntry != 0) {
-    // The entry must be a page table. Otherwise it exists an overlapping in the memory map
-    if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(*SectionEntry)) {
-      TranslationTable = *SectionEntry & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK;
-    } else if ((*SectionEntry & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) {
-      // Case where a virtual memory map descriptor overlapped a section entry
-
-      // Allocate a Level2 Page Table for this Section
-      TranslationTable = (UINTN)AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_PAGE_SIZE + TRANSLATION_TABLE_PAGE_ALIGNMENT));
-      TranslationTable = ((UINTN)TranslationTable + TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK;
-
-      // Translate the Section Descriptor into Page Descriptor
-      SectionDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttributesToPageAttributes (*SectionEntry, FALSE);
-
-      BaseSectionAddress = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(*SectionEntry);
-
-      // Populate the new Level2 Page Table for the section
-      PageEntry = (UINT32*)TranslationTable;
-      for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {
-        PageEntry[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseSectionAddress + (Index << 12)) | SectionDescriptor;
-      }
-
-      // Overwrite the section entry to point to the new Level2 Translation Table
-      *SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) |
-          (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes) ? (1 << 3) : 0) |
-          TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
-    } else {
-      // We do not support the other section type (16MB Section)
-      ASSERT(0);
-      return;
-    }
-  } else {
-    TranslationTable = (UINTN)AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_PAGE_SIZE + TRANSLATION_TABLE_PAGE_ALIGNMENT));
-    TranslationTable = ((UINTN)TranslationTable + TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK;
-
-    ZeroMem ((VOID *)TranslationTable, TRANSLATION_TABLE_PAGE_SIZE);
-
-    *SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) |
-        (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes) ? (1 << 3) : 0) |
-        TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
-  }
-
-  PageEntry = ((UINT32 *)(TranslationTable) + ((PhysicalBase & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT));
-  Pages     = RemainLength / TT_DESCRIPTOR_PAGE_SIZE;
-
-  for (Index = 0; Index < Pages; Index++) {
-    *PageEntry++     =  TT_DESCRIPTOR_PAGE_BASE_ADDRESS(PhysicalBase) | PageAttributes;
-    PhysicalBase += TT_DESCRIPTOR_PAGE_SIZE;
-  }
-
-}
-
-STATIC
-VOID
-FillTranslationTable (
-  IN  UINT32                        *TranslationTable,
-  IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryRegion
-  )
-{
-  UINT32  *SectionEntry;
-  UINT32  Attributes;
-  UINT32  PhysicalBase = MemoryRegion->PhysicalBase;
-  UINT32  RemainLength = MemoryRegion->Length;
-
-  ASSERT(MemoryRegion->Length > 0);
-
-  switch (MemoryRegion->Attributes) {
-    case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
-      Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
-      break;
-    case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
-      Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);
-      break;
-    case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
-      Attributes = TT_DESCRIPTOR_SECTION_DEVICE(0);
-      break;
-    case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
-      Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
-      break;
-    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
-      Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);
-      break;
-    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
-      Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);
-      break;
-    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
-      Attributes = TT_DESCRIPTOR_SECTION_DEVICE(1);
-      break;
-    case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
-      Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);
-      break;
-    default:
-      Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
-      break;
-  }
-
-  // Get the first section entry for this mapping
-  SectionEntry    = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
-
-  while (RemainLength != 0) {
-    if (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE == 0) {
-      if (RemainLength >= TT_DESCRIPTOR_SECTION_SIZE) {
-        // Case: Physical address aligned on the Section Size (1MB) && the length is greater than the Section Size
-        *SectionEntry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
-        PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
-      } else {
-        // Case: Physical address aligned on the Section Size (1MB) && the length does not fill a section
-        PopulateLevel2PageTable (SectionEntry++, PhysicalBase, RemainLength, MemoryRegion->Attributes);
-
-        // It must be the last entry
-        break;
-      }
-    } else {
-      // Case: Physical address NOT aligned on the Section Size (1MB)
-      PopulateLevel2PageTable (SectionEntry++, PhysicalBase, RemainLength, MemoryRegion->Attributes);
-      // Aligned the address
-      PhysicalBase = (PhysicalBase + TT_DESCRIPTOR_SECTION_SIZE) & ~(TT_DESCRIPTOR_SECTION_SIZE-1);
-
-      // If it is the last entry
-      if (RemainLength < TT_DESCRIPTOR_SECTION_SIZE) {
-        break;
-      }
-    }
-    RemainLength -= TT_DESCRIPTOR_SECTION_SIZE;
-  }
-}
-
-RETURN_STATUS
-EFIAPI
-ArmConfigureMmu (
-  IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,
-  OUT VOID                         **TranslationTableBase OPTIONAL,
-  OUT UINTN                         *TranslationTableSize OPTIONAL
-  )
-{
-  VOID*                         TranslationTable;
-  ARM_MEMORY_REGION_ATTRIBUTES  TranslationTableAttribute;
-  UINT32                        TTBRAttributes;
-
-  // Allocate pages for translation table.
-  TranslationTable = AllocatePages (EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_SECTION_SIZE + TRANSLATION_TABLE_SECTION_ALIGNMENT));
-  if (TranslationTable == NULL) {
-    return RETURN_OUT_OF_RESOURCES;
-  }
-  TranslationTable = (VOID*)(((UINTN)TranslationTable + TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK);
-
-  if (TranslationTableBase != NULL) {
-    *TranslationTableBase = TranslationTable;
-  }
-
-  if (TranslationTableSize != NULL) {
-    *TranslationTableSize = TRANSLATION_TABLE_SECTION_SIZE;
-  }
-
-  ZeroMem (TranslationTable, TRANSLATION_TABLE_SECTION_SIZE);
-
-  // By default, mark the translation table as belonging to a uncached region
-  TranslationTableAttribute = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
-  while (MemoryTable->Length != 0) {
-    // Find the memory attribute for the Translation Table
-    if (((UINTN)TranslationTable >= MemoryTable->PhysicalBase) && ((UINTN)TranslationTable <= MemoryTable->PhysicalBase - 1 + MemoryTable->Length)) {
-      TranslationTableAttribute = MemoryTable->Attributes;
-    }
-
-    FillTranslationTable (TranslationTable, MemoryTable);
-    MemoryTable++;
-  }
-
-  // Translate the Memory Attributes into Translation Table Register Attributes
-  if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) ||
-      (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) {
-    TTBRAttributes = TTBR_NON_CACHEABLE;
-  } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||
-      (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {
-    TTBRAttributes = TTBR_WRITE_BACK_ALLOC;
-  } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) ||
-      (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) {
-    TTBRAttributes = TTBR_WRITE_THROUGH_NO_ALLOC;
-  } else {
-    ASSERT (0); // No support has been found for the attributes of the memory region that the translation table belongs to.
-    return RETURN_UNSUPPORTED;
-  }
-
-  ArmCleanInvalidateDataCache ();
-  ArmInvalidateInstructionCache ();
-
-  ArmDisableDataCache ();
-  ArmDisableInstructionCache();
-  // TLBs are also invalidated when calling ArmDisableMmu()
-  ArmDisableMmu ();
-
-  // Make sure nothing sneaked into the cache
-  ArmCleanInvalidateDataCache ();
-  ArmInvalidateInstructionCache ();
-
-  ArmSetTTBR0 ((VOID *)(UINTN)(((UINTN)TranslationTable & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) | (TTBRAttributes & 0x7F)));
-
-  ArmSetDomainAccessControl (DOMAIN_ACCESS_CONTROL_NONE(15) |
-                             DOMAIN_ACCESS_CONTROL_NONE(14) |
-                             DOMAIN_ACCESS_CONTROL_NONE(13) |
-                             DOMAIN_ACCESS_CONTROL_NONE(12) |
-                             DOMAIN_ACCESS_CONTROL_NONE(11) |
-                             DOMAIN_ACCESS_CONTROL_NONE(10) |
-                             DOMAIN_ACCESS_CONTROL_NONE( 9) |
-                             DOMAIN_ACCESS_CONTROL_NONE( 8) |
-                             DOMAIN_ACCESS_CONTROL_NONE( 7) |
-                             DOMAIN_ACCESS_CONTROL_NONE( 6) |
-                             DOMAIN_ACCESS_CONTROL_NONE( 5) |
-                             DOMAIN_ACCESS_CONTROL_NONE( 4) |
-                             DOMAIN_ACCESS_CONTROL_NONE( 3) |
-                             DOMAIN_ACCESS_CONTROL_NONE( 2) |
-                             DOMAIN_ACCESS_CONTROL_NONE( 1) |
-                             DOMAIN_ACCESS_CONTROL_MANAGER(0));
-
-  ArmEnableInstructionCache();
-  ArmEnableDataCache();
-  ArmEnableMmu();
-  return RETURN_SUCCESS;
-}
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
deleted file mode 100644
index af5ec23a1a..0000000000
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
+++ /dev/null
@@ -1,391 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution.  The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
-
-.text
-.align 2
-
-GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
-GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
-GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
-GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
-GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
-GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
-GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)
-GCC_ASM_EXPORT (ArmDrainWriteBuffer)
-GCC_ASM_EXPORT (ArmEnableMmu)
-GCC_ASM_EXPORT (ArmDisableMmu)
-GCC_ASM_EXPORT (ArmDisableCachesAndMmu)
-GCC_ASM_EXPORT (ArmMmuEnabled)
-GCC_ASM_EXPORT (ArmEnableDataCache)
-GCC_ASM_EXPORT (ArmDisableDataCache)
-GCC_ASM_EXPORT (ArmEnableInstructionCache)
-GCC_ASM_EXPORT (ArmDisableInstructionCache)
-GCC_ASM_EXPORT (ArmEnableSWPInstruction)
-GCC_ASM_EXPORT (ArmEnableBranchPrediction)
-GCC_ASM_EXPORT (ArmDisableBranchPrediction)
-GCC_ASM_EXPORT (ArmSetLowVectors)
-GCC_ASM_EXPORT (ArmSetHighVectors)
-GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)
-GCC_ASM_EXPORT (ArmV7PerformPoUDataCacheOperation)
-GCC_ASM_EXPORT (ArmDataMemoryBarrier)
-GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)
-GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
-GCC_ASM_EXPORT (ArmReadVBar)
-GCC_ASM_EXPORT (ArmWriteVBar)
-GCC_ASM_EXPORT (ArmEnableVFP)
-GCC_ASM_EXPORT (ArmCallWFI)
-GCC_ASM_EXPORT (ArmReadCbar)
-GCC_ASM_EXPORT (ArmReadMpidr)
-GCC_ASM_EXPORT (ArmReadTpidrurw)
-GCC_ASM_EXPORT (ArmWriteTpidrurw)
-GCC_ASM_EXPORT (ArmIsArchTimerImplemented)
-GCC_ASM_EXPORT (ArmReadIdPfr1)
-
-.set DC_ON, (0x1<<2)
-.set IC_ON, (0x1<<12)
-.set CTRL_M_BIT,  (1 << 0)
-.set CTRL_C_BIT,  (1 << 2)
-.set CTRL_B_BIT,  (1 << 7)
-.set CTRL_I_BIT,  (1 << 12)
-
-
-ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
-  mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line
-  dsb
-  isb
-  bx      lr
-
-ASM_PFX(ArmCleanDataCacheEntryByMVA):
-  mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line
-  dsb
-  isb
-  bx      lr
-
-
-ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
-  mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line
-  dsb
-  isb
-  bx      lr
-
-
-ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
-  mcr     p15, 0, r0, c7, c6, 2        @ Invalidate this line
-  dsb
-  isb
-  bx      lr
-
-
-ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
-  mcr     p15, 0, r0, c7, c14, 2       @ Clean and Invalidate this line
-  dsb
-  isb
-  bx      lr
-
-
-ASM_PFX(ArmCleanDataCacheEntryBySetWay):
-  mcr     p15, 0, r0, c7, c10, 2       @ Clean this line
-  dsb
-  isb
-  bx      lr
-
-ASM_PFX(ArmInvalidateInstructionCache):
-  mcr     p15,0,R0,c7,c5,0      @Invalidate entire instruction cache
-  dsb
-  isb
-  bx      LR
-
-ASM_PFX(ArmEnableMmu):
-  mrc     p15,0,R0,c1,c0,0
-  orr     R0,R0,#1
-  mcr     p15,0,R0,c1,c0,0
-  dsb
-  isb
-  bx      LR
-
-
-ASM_PFX(ArmDisableMmu):
-  mrc     p15,0,R0,c1,c0,0
-  bic     R0,R0,#1
-  mcr     p15,0,R0,c1,c0,0      @Disable MMU
-
-  mcr     p15,0,R0,c8,c7,0      @Invalidate TLB
-  mcr     p15,0,R0,c7,c5,6      @Invalidate Branch predictor array
-  dsb
-  isb
-  bx      LR
-
-ASM_PFX(ArmDisableCachesAndMmu):
-  mrc   p15, 0, r0, c1, c0, 0           @ Get control register
-  bic   r0, r0, #CTRL_M_BIT             @ Disable MMU
-  bic   r0, r0, #CTRL_C_BIT             @ Disable D Cache
-  bic   r0, r0, #CTRL_I_BIT             @ Disable I Cache
-  mcr   p15, 0, r0, c1, c0, 0           @ Write control register
-  dsb
-  isb
-  bx      LR
-
-ASM_PFX(ArmMmuEnabled):
-  mrc     p15,0,R0,c1,c0,0
-  and     R0,R0,#1
-  bx      LR
-
-ASM_PFX(ArmEnableDataCache):
-  ldr     R1,=DC_ON
-  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
-  orr     R0,R0,R1              @Set C bit
-  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
-  dsb
-  isb
-  bx      LR
-
-ASM_PFX(ArmDisableDataCache):
-  ldr     R1,=DC_ON
-  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
-  bic     R0,R0,R1              @Clear C bit
-  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
-  dsb
-  isb
-  bx      LR
-
-ASM_PFX(ArmEnableInstructionCache):
-  ldr     R1,=IC_ON
-  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
-  orr     R0,R0,R1              @Set I bit
-  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
-  dsb
-  isb
-  bx      LR
-
-ASM_PFX(ArmDisableInstructionCache):
-  ldr     R1,=IC_ON
-  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
-  bic     R0,R0,R1              @Clear I bit.
-  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
-  dsb
-  isb
-  bx      LR
-
-ASM_PFX(ArmEnableSWPInstruction):
-  mrc     p15, 0, r0, c1, c0, 0
-  orr     r0, r0, #0x00000400
-  mcr     p15, 0, r0, c1, c0, 0
-  isb
-  bx      LR
-
-ASM_PFX(ArmEnableBranchPrediction):
-  mrc     p15, 0, r0, c1, c0, 0
-  orr     r0, r0, #0x00000800
-  mcr     p15, 0, r0, c1, c0, 0
-  dsb
-  isb
-  bx      LR
-
-ASM_PFX(ArmDisableBranchPrediction):
-  mrc     p15, 0, r0, c1, c0, 0
-  bic     r0, r0, #0x00000800
-  mcr     p15, 0, r0, c1, c0, 0
-  dsb
-  isb
-  bx      LR
-
-ASM_PFX(ArmSetLowVectors):
-  mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
-  bic     r0, r0, #0x00002000   @ clear V bit
-  mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
-  isb
-  bx      LR
-
-ASM_PFX(ArmSetHighVectors):
-  mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
-  orr     r0, r0, #0x00002000   @ Set V bit
-  mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
-  isb
-  bx      LR
-
-ASM_PFX(ArmV7AllDataCachesOperation):
-  stmfd SP!,{r4-r12, LR}
-  mov   R1, R0                @ Save Function call in R1
-  mrc   p15, 1, R6, c0, c0, 1 @ Read CLIDR
-  ands  R3, R6, #0x7000000    @ Mask out all but Level of Coherency (LoC)
-  mov   R3, R3, LSR #23       @ Cache level value (naturally aligned)
-  beq   L_Finished
-  mov   R10, #0
-
-Loop1:
-  add   R2, R10, R10, LSR #1  @ Work out 3xcachelevel
-  mov   R12, R6, LSR R2       @ bottom 3 bits are the Cache type for this level
-  and   R12, R12, #7          @ get those 3 bits alone
-  cmp   R12, #2
-  blt   L_Skip                  @ no cache or only instruction cache at this level
-  mcr   p15, 2, R10, c0, c0, 0  @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
-  isb                           @ isb to sync the change to the CacheSizeID reg
-  mrc   p15, 1, R12, c0, c0, 0  @ reads current Cache Size ID register (CCSIDR)
-  and   R2, R12, #0x7           @ extract the line length field
-  add   R2, R2, #4              @ add 4 for the line length offset (log2 16 bytes)
-@  ldr   R4, =0x3FF
-  mov   R4, #0x400
-  sub   R4, R4, #1
-  ands  R4, R4, R12, LSR #3     @ R4 is the max number on the way size (right aligned)
-  clz   R5, R4                  @ R5 is the bit position of the way size increment
-@  ldr   R7, =0x00007FFF
-  mov   R7, #0x00008000
-  sub   R7, R7, #1
-  ands  R7, R7, R12, LSR #13    @ R7 is the max number of the index size (right aligned)
-
-Loop2:
-  mov   R9, R4                  @ R9 working copy of the max way size (right aligned)
-
-Loop3:
-  orr   R0, R10, R9, LSL R5     @ factor in the way number and cache number into R11
-  orr   R0, R0, R7, LSL R2      @ factor in the index number
-
-  blx   R1
-
-  subs  R9, R9, #1              @ decrement the way number
-  bge   Loop3
-  subs  R7, R7, #1              @ decrement the index
-  bge   Loop2
-L_Skip:
-  add   R10, R10, #2            @ increment the cache number
-  cmp   R3, R10
-  bgt   Loop1
-
-L_Finished:
-  dsb
-  ldmfd SP!, {r4-r12, lr}
-  bx    LR
-
-ASM_PFX(ArmV7PerformPoUDataCacheOperation):
-  stmfd SP!,{r4-r12, LR}
-  mov   R1, R0                @ Save Function call in R1
-  mrc   p15, 1, R6, c0, c0, 1 @ Read CLIDR
-  ands  R3, R6, #0x38000000    @ Mask out all but Level of Unification (LoU)
-  mov   R3, R3, LSR #26       @ Cache level value (naturally aligned)
-  beq   Finished2
-  mov   R10, #0
-
-Loop4:
-  add   R2, R10, R10, LSR #1    @ Work out 3xcachelevel
-  mov   R12, R6, LSR R2         @ bottom 3 bits are the Cache type for this level
-  and   R12, R12, #7            @ get those 3 bits alone
-  cmp   R12, #2
-  blt   Skip2                   @ no cache or only instruction cache at this level
-  mcr   p15, 2, R10, c0, c0, 0  @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
-  isb                           @ isb to sync the change to the CacheSizeID reg
-  mrc   p15, 1, R12, c0, c0, 0  @ reads current Cache Size ID register (CCSIDR)
-  and   R2, R12, #0x7            @ extract the line length field
-  add   R2, R2, #4              @ add 4 for the line length offset (log2 16 bytes)
-  ldr   R4, =0x3FF
-  ands  R4, R4, R12, LSR #3     @ R4 is the max number on the way size (right aligned)
-  clz   R5, R4                  @ R5 is the bit position of the way size increment
-  ldr   R7, =0x00007FFF
-  ands  R7, R7, R12, LSR #13    @ R7 is the max number of the index size (right aligned)
-
-Loop5:
-  mov   R9, R4                  @ R9 working copy of the max way size (right aligned)
-
-Loop6:
-  orr   R0, R10, R9, LSL R5     @ factor in the way number and cache number into R11
-  orr   R0, R0, R7, LSL R2      @ factor in the index number
-
-  blx   R1
-
-  subs  R9, R9, #1              @ decrement the way number
-  bge   Loop6
-  subs  R7, R7, #1              @ decrement the index
-  bge   Loop5
-Skip2:
-  add   R10, R10, #2            @ increment the cache number
-  cmp   R3, R10
-  bgt   Loop4
-
-Finished2:
-  dsb
-  ldmfd SP!, {r4-r12, lr}
-  bx    LR
-
-ASM_PFX(ArmDataMemoryBarrier):
-  dmb
-  bx      LR
-
-ASM_PFX(ArmDataSyncronizationBarrier):
-ASM_PFX(ArmDrainWriteBuffer):
-  dsb
-  bx      LR
-
-ASM_PFX(ArmInstructionSynchronizationBarrier):
-  isb
-  bx      LR
-
-ASM_PFX(ArmReadVBar):
-  # Set the Address of the Vector Table in the VBAR register
-  mrc     p15, 0, r0, c12, c0, 0
-  bx      lr
-
-ASM_PFX(ArmWriteVBar):
-  # Set the Address of the Vector Table in the VBAR register
-  mcr     p15, 0, r0, c12, c0, 0
-  # Ensure the SCTLR.V bit is clear
-  mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
-  bic     r0, r0, #0x00002000   @ clear V bit
-  mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
-  isb
-  bx      lr
-
-ASM_PFX(ArmEnableVFP):
-  # Read CPACR (Coprocessor Access Control Register)
-  mrc     p15, 0, r0, c1, c0, 2
-  # Enable VPF access (Full Access to CP10, CP11) (V* instructions)
-  orr     r0, r0, #0x00f00000
-  # Write back CPACR (Coprocessor Access Control Register)
-  mcr     p15, 0, r0, c1, c0, 2
-  isb
-  # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
-  mov     r0, #0x40000000
-  mcr     p10,#0x7,r0,c8,c0,#0
-  bx      lr
-
-ASM_PFX(ArmCallWFI):
-  wfi
-  bx      lr
-
-#Note: Return 0 in Uniprocessor implementation
-ASM_PFX(ArmReadCbar):
-  mrc     p15, 4, r0, c15, c0, 0  @ Read Configuration Base Address Register
-  bx      lr
-
-ASM_PFX(ArmReadMpidr):
-  mrc     p15, 0, r0, c0, c0, 5       @ read MPIDR
-  bx      lr
-
-ASM_PFX(ArmReadTpidrurw):
-  mrc     p15, 0, r0, c13, c0, 2    @ read TPIDRURW
-  bx      lr
-
-ASM_PFX(ArmWriteTpidrurw):
-  mcr     p15, 0, r0, c13, c0, 2    @ write TPIDRURW
-  bx      lr
-
-ASM_PFX(ArmIsArchTimerImplemented):
-  mrc    p15, 0, r0, c0, c1, 1     @ Read ID_PFR1
-  and    r0, r0, #0x000F0000
-  bx     lr
-
-ASM_PFX(ArmReadIdPfr1):
-  mrc    p15, 0, r0, c0, c1, 1     @ Read ID_PFR1 Register
-  bx     lr
-
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
deleted file mode 100644
index 2b13811dc6..0000000000
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
+++ /dev/null
@@ -1,385 +0,0 @@
-//------------------------------------------------------------------------------
-//
-// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
-//
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution.  The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//------------------------------------------------------------------------------
-
-    EXPORT  ArmInvalidateInstructionCache
-    EXPORT  ArmInvalidateDataCacheEntryByMVA
-    EXPORT  ArmCleanDataCacheEntryByMVA
-    EXPORT  ArmCleanInvalidateDataCacheEntryByMVA
-    EXPORT  ArmInvalidateDataCacheEntryBySetWay
-    EXPORT  ArmCleanDataCacheEntryBySetWay
-    EXPORT  ArmCleanInvalidateDataCacheEntryBySetWay
-    EXPORT  ArmDrainWriteBuffer
-    EXPORT  ArmEnableMmu
-    EXPORT  ArmDisableMmu
-    EXPORT  ArmDisableCachesAndMmu
-    EXPORT  ArmMmuEnabled
-    EXPORT  ArmEnableDataCache
-    EXPORT  ArmDisableDataCache
-    EXPORT  ArmEnableInstructionCache
-    EXPORT  ArmDisableInstructionCache
-    EXPORT  ArmEnableSWPInstruction
-    EXPORT  ArmEnableBranchPrediction
-    EXPORT  ArmDisableBranchPrediction
-    EXPORT  ArmSetLowVectors
-    EXPORT  ArmSetHighVectors
-    EXPORT  ArmV7AllDataCachesOperation
-    EXPORT  ArmV7PerformPoUDataCacheOperation
-    EXPORT  ArmDataMemoryBarrier
-    EXPORT  ArmDataSyncronizationBarrier
-    EXPORT  ArmInstructionSynchronizationBarrier
-    EXPORT  ArmReadVBar
-    EXPORT  ArmWriteVBar
-    EXPORT  ArmEnableVFP
-    EXPORT  ArmCallWFI
-    EXPORT  ArmReadCbar
-    EXPORT  ArmReadMpidr
-    EXPORT  ArmReadTpidrurw
-    EXPORT  ArmWriteTpidrurw
-    EXPORT  ArmIsArchTimerImplemented
-    EXPORT  ArmReadIdPfr1
-
-    AREA    ArmV7Support, CODE, READONLY
-    PRESERVE8
-
-DC_ON           EQU     ( 0x1:SHL:2 )
-IC_ON           EQU     ( 0x1:SHL:12 )
-CTRL_M_BIT      EQU     (1 << 0)
-CTRL_C_BIT      EQU     (1 << 2)
-CTRL_B_BIT      EQU     (1 << 7)
-CTRL_I_BIT      EQU     (1 << 12)
-
-
-ArmInvalidateDataCacheEntryByMVA
-  mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line
-  dsb
-  isb
-  bx      lr
-
-ArmCleanDataCacheEntryByMVA
-  mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line
-  dsb
-  isb
-  bx      lr
-
-
-ArmCleanInvalidateDataCacheEntryByMVA
-  mcr     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line
-  dsb
-  isb
-  bx      lr
-
-
-ArmInvalidateDataCacheEntryBySetWay
-  mcr     p15, 0, r0, c7, c6, 2        ; Invalidate this line
-  dsb
-  isb
-  bx      lr
-
-
-ArmCleanInvalidateDataCacheEntryBySetWay
-  mcr     p15, 0, r0, c7, c14, 2       ; Clean and Invalidate this line
-  dsb
-  isb
-  bx      lr
-
-
-ArmCleanDataCacheEntryBySetWay
-  mcr     p15, 0, r0, c7, c10, 2       ; Clean this line
-  dsb
-  isb
-  bx      lr
-
-
-ArmInvalidateInstructionCache
-  mcr     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache
-  isb
-  bx      LR
-
-ArmEnableMmu
-  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
-  orr     R0,R0,#1              ; Set SCTLR.M bit : Enable MMU
-  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
-  dsb
-  isb
-  bx      LR
-
-ArmDisableMmu
-  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
-  bic     R0,R0,#1              ; Clear SCTLR.M bit : Disable MMU
-  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
-
-  mcr     p15,0,R0,c8,c7,0      ; TLBIALL : Invalidate unified TLB
-  mcr     p15,0,R0,c7,c5,6      ; BPIALL  : Invalidate entire branch predictor array
-  dsb
-  isb
-  bx      LR
-
-ArmDisableCachesAndMmu
-  mrc   p15, 0, r0, c1, c0, 0           ; Get control register
-  bic   r0, r0, #CTRL_M_BIT             ; Disable MMU
-  bic   r0, r0, #CTRL_C_BIT             ; Disable D Cache
-  bic   r0, r0, #CTRL_I_BIT             ; Disable I Cache
-  mcr   p15, 0, r0, c1, c0, 0           ; Write control register
-  dsb
-  isb
-  bx      LR
-
-ArmMmuEnabled
-  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
-  and     R0,R0,#1
-  bx      LR
-
-ArmEnableDataCache
-  ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit
-  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
-  orr     R0,R0,R1              ; Set SCTLR.C bit : Data and unified caches enabled
-  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
-  dsb
-  isb
-  bx      LR
-
-ArmDisableDataCache
-  ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit
-  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
-  bic     R0,R0,R1              ; Clear SCTLR.C bit : Data and unified caches disabled
-  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
-  dsb
-  isb
-  bx      LR
-
-ArmEnableInstructionCache
-  ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit
-  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
-  orr     R0,R0,R1              ; Set SCTLR.I bit : Instruction caches enabled
-  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
-  dsb
-  isb
-  bx      LR
-
-ArmDisableInstructionCache
-  ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit
-  mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
-  BIC     R0,R0,R1              ; Clear SCTLR.I bit : Instruction caches disabled
-  mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
-  isb
-  bx      LR
-
-ArmEnableSWPInstruction
-  mrc     p15, 0, r0, c1, c0, 0
-  orr     r0, r0, #0x00000400
-  mcr     p15, 0, r0, c1, c0, 0
-  isb
-  bx      LR
-
-ArmEnableBranchPrediction
-  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
-  orr     r0, r0, #0x00000800   ;
-  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
-  dsb
-  isb
-  bx      LR
-
-ArmDisableBranchPrediction
-  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
-  bic     r0, r0, #0x00000800   ;
-  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
-  dsb
-  isb
-  bx      LR
-
-ArmSetLowVectors
-  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
-  bic     r0, r0, #0x00002000   ; clear V bit
-  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
-  isb
-  bx      LR
-
-ArmSetHighVectors
-  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
-  orr     r0, r0, #0x00002000   ; Set V bit
-  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
-  isb
-  bx      LR
-
-ArmV7AllDataCachesOperation
-  stmfd SP!,{r4-r12, LR}
-  mov   R1, R0                ; Save Function call in R1
-  mrc   p15, 1, R6, c0, c0, 1 ; Read CLIDR
-  ands  R3, R6, #&7000000     ; Mask out all but Level of Coherency (LoC)
-  mov   R3, R3, LSR #23       ; Cache level value (naturally aligned)
-  beq   Finished
-  mov   R10, #0
-
-Loop1
-  add   R2, R10, R10, LSR #1    ; Work out 3xcachelevel
-  mov   R12, R6, LSR R2         ; bottom 3 bits are the Cache type for this level
-  and   R12, R12, #7            ; get those 3 bits alone
-  cmp   R12, #2
-  blt   Skip                    ; no cache or only instruction cache at this level
-  mcr   p15, 2, R10, c0, c0, 0  ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
-  isb                           ; isb to sync the change to the CacheSizeID reg
-  mrc   p15, 1, R12, c0, c0, 0  ; reads current Cache Size ID register (CCSIDR)
-  and   R2, R12, #&7            ; extract the line length field
-  add   R2, R2, #4              ; add 4 for the line length offset (log2 16 bytes)
-  ldr   R4, =0x3FF
-  ands  R4, R4, R12, LSR #3     ; R4 is the max number on the way size (right aligned)
-  clz   R5, R4                  ; R5 is the bit position of the way size increment
-  ldr   R7, =0x00007FFF
-  ands  R7, R7, R12, LSR #13    ; R7 is the max number of the index size (right aligned)
-
-Loop2
-  mov   R9, R4                  ; R9 working copy of the max way size (right aligned)
-
-Loop3
-  orr   R0, R10, R9, LSL R5     ; factor in the way number and cache number into R11
-  orr   R0, R0, R7, LSL R2      ; factor in the index number
-
-  blx   R1
-
-  subs  R9, R9, #1              ; decrement the way number
-  bge   Loop3
-  subs  R7, R7, #1              ; decrement the index
-  bge   Loop2
-Skip
-  add   R10, R10, #2            ; increment the cache number
-  cmp   R3, R10
-  bgt   Loop1
-
-Finished
-  dsb
-  ldmfd SP!, {r4-r12, lr}
-  bx    LR
-
-ArmV7PerformPoUDataCacheOperation
-  stmfd SP!,{r4-r12, LR}
-  mov   R1, R0                ; Save Function call in R1
-  mrc   p15, 1, R6, c0, c0, 1 ; Read CLIDR
-  ands  R3, R6, #&38000000    ; Mask out all but Level of Unification (LoU)
-  mov   R3, R3, LSR #26       ; Cache level value (naturally aligned)
-  beq   Finished2
-  mov   R10, #0
-
-Loop4
-  add   R2, R10, R10, LSR #1    ; Work out 3xcachelevel
-  mov   R12, R6, LSR R2         ; bottom 3 bits are the Cache type for this level
-  and   R12, R12, #7            ; get those 3 bits alone
-  cmp   R12, #2
-  blt   Skip2                   ; no cache or only instruction cache at this level
-  mcr   p15, 2, R10, c0, c0, 0  ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
-  isb                           ; isb to sync the change to the CacheSizeID reg
-  mrc   p15, 1, R12, c0, c0, 0  ; reads current Cache Size ID register (CCSIDR)
-  and   R2, R12, #&7            ; extract the line length field
-  add   R2, R2, #4              ; add 4 for the line length offset (log2 16 bytes)
-  ldr   R4, =0x3FF
-  ands  R4, R4, R12, LSR #3     ; R4 is the max number on the way size (right aligned)
-  clz   R5, R4                  ; R5 is the bit position of the way size increment
-  ldr   R7, =0x00007FFF
-  ands  R7, R7, R12, LSR #13    ; R7 is the max number of the index size (right aligned)
-
-Loop5
-  mov   R9, R4                  ; R9 working copy of the max way size (right aligned)
-
-Loop6
-  orr   R0, R10, R9, LSL R5     ; factor in the way number and cache number into R11
-  orr   R0, R0, R7, LSL R2      ; factor in the index number
-
-  blx   R1
-
-  subs  R9, R9, #1              ; decrement the way number
-  bge   Loop6
-  subs  R7, R7, #1              ; decrement the index
-  bge   Loop5
-Skip2
-  add   R10, R10, #2            ; increment the cache number
-  cmp   R3, R10
-  bgt   Loop4
-
-Finished2
-  dsb
-  ldmfd SP!, {r4-r12, lr}
-  bx    LR
-
-ArmDataMemoryBarrier
-  dmb
-  bx      LR
-
-ArmDataSyncronizationBarrier
-ArmDrainWriteBuffer
-  dsb
-  bx      LR
-
-ArmInstructionSynchronizationBarrier
-  isb
-  bx      LR
-
-ArmReadVBar
-  // Set the Address of the Vector Table in the VBAR register
-  mrc     p15, 0, r0, c12, c0, 0
-  bx      lr
-
-ArmWriteVBar
-  // Set the Address of the Vector Table in the VBAR register
-  mcr     p15, 0, r0, c12, c0, 0
-  // Ensure the SCTLR.V bit is clear
-  mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
-  bic     r0, r0, #0x00002000   ; clear V bit
-  mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
-  isb
-  bx      lr
-
-ArmEnableVFP
-  // Read CPACR (Coprocessor Access Control Register)
-  mrc     p15, 0, r0, c1, c0, 2
-  // Enable VPF access (Full Access to CP10, CP11) (V* instructions)
-  orr     r0, r0, #0x00f00000
-  // Write back CPACR (Coprocessor Access Control Register)
-  mcr     p15, 0, r0, c1, c0, 2
-  isb
-  // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
-  mov     r0, #0x40000000
-  mcr     p10,#0x7,r0,c8,c0,#0
-  bx      lr
-
-ArmCallWFI
-  wfi
-  bx      lr
-
-//Note: Return 0 in Uniprocessor implementation
-ArmReadCbar
-  mrc     p15, 4, r0, c15, c0, 0  //Read Configuration Base Address Register
-  bx      lr
-
-ArmReadMpidr
-  mrc     p15, 0, r0, c0, c0, 5     ; read MPIDR
-  bx      lr
-
-ArmReadTpidrurw
-  mrc     p15, 0, r0, c13, c0, 2    ; read TPIDRURW
-  bx      lr
-
-ArmWriteTpidrurw
-  mcr     p15, 0, r0, c13, c0, 2   ; write TPIDRURW
-  bx      lr
-
-ArmIsArchTimerImplemented
-  mrc    p15, 0, r0, c0, c1, 1     ; Read ID_PFR1
-  and    r0, r0, #0x000F0000
-  bx     lr
-
-ArmReadIdPfr1
-  mrc    p15, 0, r0, c0, c1, 1     ; Read ID_PFR1 Register
-  bx     lr
-
- END
diff --git a/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S
deleted file mode 100644
index 28db98b417..0000000000
--- a/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S
+++ /dev/null
@@ -1,211 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution.  The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
-
-#include <AsmMacroIoLibV8.h>
-
-.text
-.align 3
-GCC_ASM_EXPORT (ArmReadMidr)
-GCC_ASM_EXPORT (ArmCacheInfo)
-GCC_ASM_EXPORT (ArmGetInterruptState)
-GCC_ASM_EXPORT (ArmGetFiqState)
-GCC_ASM_EXPORT (ArmGetTTBR0BaseAddress)
-GCC_ASM_EXPORT (ArmSetTTBR0)
-GCC_ASM_EXPORT (ArmGetTCR)
-GCC_ASM_EXPORT (ArmSetTCR)
-GCC_ASM_EXPORT (ArmGetMAIR)
-GCC_ASM_EXPORT (ArmSetMAIR)
-GCC_ASM_EXPORT (ArmWriteCpacr)
-GCC_ASM_EXPORT (ArmWriteAuxCr)
-GCC_ASM_EXPORT (ArmReadAuxCr)
-GCC_ASM_EXPORT (ArmInvalidateTlb)
-GCC_ASM_EXPORT (ArmUpdateTranslationTableEntry)
-GCC_ASM_EXPORT (ArmWriteCptr)
-GCC_ASM_EXPORT (ArmWriteScr)
-GCC_ASM_EXPORT (ArmWriteMVBar)
-GCC_ASM_EXPORT (ArmCallWFE)
-GCC_ASM_EXPORT (ArmCallSEV)
-GCC_ASM_EXPORT (ArmReadCpuActlr)
-GCC_ASM_EXPORT (ArmWriteCpuActlr)
-
-#------------------------------------------------------------------------------
-
-.set DAIF_FIQ_BIT,   (1 << 0)
-.set DAIF_IRQ_BIT,   (1 << 1)
-
-ASM_PFX(ArmReadMidr):
-  mrs     x0, midr_el1        // Read from Main ID Register (MIDR)
-  ret
-
-ASM_PFX(ArmCacheInfo):
-  mrs     x0, ctr_el0         // Read from Cache Type Regiter (CTR)
-  ret
-
-ASM_PFX(ArmGetInterruptState):
-  mrs     x0, daif
-  tst     w0, #DAIF_IRQ_BIT   // Check if IRQ is enabled. Enabled if 0.
-  mov     w0, #0
-  mov     w1, #1
-  csel    w0, w1, w0, ne
-  ret
-
-ASM_PFX(ArmGetFiqState):
-  mrs     x0, daif
-  tst     w0, #DAIF_FIQ_BIT   // Check if FIQ is enabled. Enabled if 0.
-  mov     w0, #0
-  mov     w1, #1
-  csel    w0, w1, w0, ne
-  ret
-
-ASM_PFX(ArmWriteCpacr):
-  msr     cpacr_el1, x0      // Coprocessor Access Control Reg (CPACR)
-  ret
-
-ASM_PFX(ArmWriteAuxCr):
-  EL1_OR_EL2(x1)
-1:msr     actlr_el1, x0      // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
-  ret
-2:msr     actlr_el2, x0      // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
-  ret
-
-ASM_PFX(ArmReadAuxCr):
-  EL1_OR_EL2(x1)
-1:mrs     x0, actlr_el1      // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
-  ret
-2:mrs     x0, actlr_el2      // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
-  ret
-
-ASM_PFX(ArmSetTTBR0):
-  EL1_OR_EL2_OR_EL3(x1)
-1:msr     ttbr0_el1, x0      // Translation Table Base Reg 0 (TTBR0)
-  b       4f
-2:msr     ttbr0_el2, x0      // Translation Table Base Reg 0 (TTBR0)
-  b       4f
-3:msr     ttbr0_el3, x0      // Translation Table Base Reg 0 (TTBR0)
-4:isb
-  ret
-
-ASM_PFX(ArmGetTTBR0BaseAddress):
-  EL1_OR_EL2(x1)
-1:mrs     x0, ttbr0_el1
-  b       3f
-2:mrs     x0, ttbr0_el2
-3:LoadConstantToReg(0xFFFFFFFFFFFF, x1) /* Look at bottom 48 bits */
-  and     x0, x0, x1
-  isb
-  ret
-
-ASM_PFX(ArmGetTCR):
-  EL1_OR_EL2_OR_EL3(x1)
-1:mrs     x0, tcr_el1
-  b       4f
-2:mrs     x0, tcr_el2
-  b       4f
-3:mrs     x0, tcr_el3
-4:isb
-  ret
-
-ASM_PFX(ArmSetTCR):
-  EL1_OR_EL2_OR_EL3(x1)
-1:msr     tcr_el1, x0
-  b       4f
-2:msr     tcr_el2, x0
-  b       4f
-3:msr     tcr_el3, x0
-4:isb
-  ret
-
-ASM_PFX(ArmGetMAIR):
-  EL1_OR_EL2_OR_EL3(x1)
-1:mrs     x0, mair_el1
-  b       4f
-2:mrs     x0, mair_el2
-  b       4f
-3:mrs     x0, mair_el3
-4:isb
-  ret
-
-ASM_PFX(ArmSetMAIR):
-  EL1_OR_EL2_OR_EL3(x1)
-1:msr     mair_el1, x0
-  b       4f
-2:msr     mair_el2, x0
-  b       4f
-3:msr     mair_el3, x0
-4:isb
-  ret
-
-
-//
-//VOID
-//ArmUpdateTranslationTableEntry (
-//  IN VOID  *TranslationTableEntry  // X0
-//  IN VOID  *MVA                    // X1
-//  );
-ASM_PFX(ArmUpdateTranslationTableEntry):
-   dc      civac, x0             // Clean and invalidate data line
-   dsb     sy
-   EL1_OR_EL2_OR_EL3(x0)
-1: tlbi    vaae1, x1             // TLB Invalidate VA , EL1
-   b       4f
-2: tlbi    vae2, x1              // TLB Invalidate VA , EL2
-   b       4f
-3: tlbi    vae3, x1              // TLB Invalidate VA , EL3
-4: dsb     sy
-   isb
-   ret
-
-ASM_PFX(ArmInvalidateTlb):
-   EL1_OR_EL2_OR_EL3(x0)
-1: tlbi  vmalle1
-   b     4f
-2: tlbi  alle2
-   b     4f
-3: tlbi  alle3
-4: dsb   sy
-   isb
-   ret
-
-ASM_PFX(ArmWriteCptr):
-  msr     cptr_el3, x0           // EL3 Coprocessor Trap Reg (CPTR)
-  ret
-
-ASM_PFX(ArmWriteScr):
-  msr     scr_el3, x0            // Secure configuration register EL3
-  ret
-
-ASM_PFX(ArmWriteMVBar):
-  msr    vbar_el3, x0            // Exception Vector Base address for Monitor on EL3
-  ret
-
-ASM_PFX(ArmCallWFE):
-  wfe
-  ret
-
-ASM_PFX(ArmCallSEV):
-  sev
-  ret
-
-ASM_PFX(ArmReadCpuActlr):
-  mrs   x0, S3_1_c15_c2_0
-  ret
-
-ASM_PFX(ArmWriteCpuActlr):
-  msr   S3_1_c15_c2_0, x0
-  dsb   sy
-  isb
-  ret
-
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
deleted file mode 100644
index 59f9918859..0000000000
--- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S
+++ /dev/null
@@ -1,190 +0,0 @@
-#------------------------------------------------------------------------------
-#
-# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution.  The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
-
-#include <AsmMacroIoLib.h>
-
-.text
-.align 2
-GCC_ASM_EXPORT(ArmReadMidr)
-GCC_ASM_EXPORT(ArmCacheInfo)
-GCC_ASM_EXPORT(ArmGetInterruptState)
-GCC_ASM_EXPORT(ArmGetFiqState)
-GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)
-GCC_ASM_EXPORT(ArmSetTTBR0)
-GCC_ASM_EXPORT(ArmSetDomainAccessControl)
-GCC_ASM_EXPORT(CPSRMaskInsert)
-GCC_ASM_EXPORT(CPSRRead)
-GCC_ASM_EXPORT(ArmReadCpacr)
-GCC_ASM_EXPORT(ArmWriteCpacr)
-GCC_ASM_EXPORT(ArmWriteAuxCr)
-GCC_ASM_EXPORT(ArmReadAuxCr)
-GCC_ASM_EXPORT(ArmInvalidateTlb)
-GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
-GCC_ASM_EXPORT(ArmReadScr)
-GCC_ASM_EXPORT(ArmWriteScr)
-GCC_ASM_EXPORT(ArmReadMVBar)
-GCC_ASM_EXPORT(ArmWriteMVBar)
-GCC_ASM_EXPORT(ArmReadHVBar)
-GCC_ASM_EXPORT(ArmWriteHVBar)
-GCC_ASM_EXPORT(ArmCallWFE)
-GCC_ASM_EXPORT(ArmCallSEV)
-GCC_ASM_EXPORT(ArmReadSctlr)
-GCC_ASM_EXPORT(ArmReadCpuActlr)
-GCC_ASM_EXPORT(ArmWriteCpuActlr)
-
-#------------------------------------------------------------------------------
-
-ASM_PFX(ArmReadMidr):
-  mrc     p15,0,R0,c0,c0,0
-  bx      LR
-
-ASM_PFX(ArmCacheInfo):
-  mrc     p15,0,R0,c0,c0,1
-  bx      LR
-
-ASM_PFX(ArmGetInterruptState):
-  mrs     R0,CPSR
-  tst     R0,#0x80      @Check if IRQ is enabled.
-  moveq   R0,#1
-  movne   R0,#0
-  bx      LR
-
-ASM_PFX(ArmGetFiqState):
-  mrs     R0,CPSR
-  tst     R0,#0x40      @Check if FIQ is enabled.
-  moveq   R0,#1
-  movne   R0,#0
-  bx      LR
-
-ASM_PFX(ArmSetDomainAccessControl):
-  mcr     p15,0,r0,c3,c0,0
-  bx      lr
-
-ASM_PFX(CPSRMaskInsert):    @ on entry, r0 is the mask and r1 is the field to insert
-  stmfd   sp!, {r4-r12, lr} @ save all the banked registers
-  mov     r3, sp            @ copy the stack pointer into a non-banked register
-  mrs     r2, cpsr          @ read the cpsr
-  bic     r2, r2, r0        @ clear mask in the cpsr
-  and     r1, r1, r0        @ clear bits outside the mask in the input
-  orr     r2, r2, r1        @ set field
-  msr     cpsr_cxsf, r2     @ write back cpsr (may have caused a mode switch)
-  isb
-  mov     sp, r3            @ restore stack pointer
-  ldmfd   sp!, {r4-r12, lr} @ restore registers
-  bx      lr                @ return (hopefully thumb-safe!)
-
-ASM_PFX(CPSRRead):
-  mrs     r0, cpsr
-  bx      lr
-
-ASM_PFX(ArmReadCpacr):
-  mrc     p15, 0, r0, c1, c0, 2
-  bx      lr
-
-ASM_PFX(ArmWriteCpacr):
-  mcr     p15, 0, r0, c1, c0, 2
-  isb
-  bx      lr
-
-ASM_PFX(ArmWriteAuxCr):
-  mcr     p15, 0, r0, c1, c0, 1
-  bx      lr
-
-ASM_PFX(ArmReadAuxCr):
-  mrc     p15, 0, r0, c1, c0, 1
-  bx      lr
-
-ASM_PFX(ArmSetTTBR0):
-  mcr     p15,0,r0,c2,c0,0
-  isb
-  bx      lr
-
-ASM_PFX(ArmGetTTBR0BaseAddress):
-  mrc     p15,0,r0,c2,c0,0
-  LoadConstantToReg(0xFFFFC000, r1)
-  and     r0, r0, r1
-  isb
-  bx      lr
-
-//
-//VOID
-//ArmUpdateTranslationTableEntry (
-//  IN VOID  *TranslationTableEntry  // R0
-//  IN VOID  *MVA                    // R1
-//  );
-ASM_PFX(ArmUpdateTranslationTableEntry):
-  mcr     p15,0,R0,c7,c14,1     @ DCCIMVAC Clean data cache by MVA
-  dsb
-  mcr     p15,0,R1,c8,c7,1      @ TLBIMVA TLB Invalidate MVA
-  mcr     p15,0,R9,c7,c5,6      @ BPIALL Invalidate Branch predictor array. R9 == NoOp
-  dsb
-  isb
-  bx      lr
-
-ASM_PFX(ArmInvalidateTlb):
-  mov     r0,#0
-  mcr     p15,0,r0,c8,c7,0
-  mcr     p15,0,R9,c7,c5,6      @ BPIALL Invalidate Branch predictor array. R9 == NoOp
-  dsb
-  isb
-  bx      lr
-
-ASM_PFX(ArmReadScr):
-  mrc     p15, 0, r0, c1, c1, 0
-  bx      lr
-
-ASM_PFX(ArmWriteScr):
-  mcr     p15, 0, r0, c1, c1, 0
-  bx      lr
-
-ASM_PFX(ArmReadHVBar):
-  mrc     p15, 4, r0, c12, c0, 0
-  bx      lr
-
-ASM_PFX(ArmWriteHVBar):
-  mcr     p15, 4, r0, c12, c0, 0
-  bx      lr
-
-ASM_PFX(ArmReadMVBar):
-  mrc     p15, 0, r0, c12, c0, 1
-  bx      lr
-
-ASM_PFX(ArmWriteMVBar):
-  mcr     p15, 0, r0, c12, c0, 1
-  bx      lr
-
-ASM_PFX(ArmCallWFE):
-  wfe
-  bx      lr
-
-ASM_PFX(ArmCallSEV):
-  sev
-  bx      lr
-
-ASM_PFX(ArmReadSctlr):
-  mrc     p15, 0, r0, c1, c0, 0      @ Read SCTLR into R0 (Read control register configuration data)
-  bx      lr
-
-ASM_PFX(ArmReadCpuActlr):
-  mrc     p15, 0, r0, c1, c0, 1
-  bx      lr
-
-ASM_PFX(ArmWriteCpuActlr):
-  mcr     p15, 0, r0, c1, c0, 1
-  dsb
-  isb
-  bx      lr
-
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
deleted file mode 100644
index 0974d4608f..0000000000
--- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm
+++ /dev/null
@@ -1,191 +0,0 @@
-//------------------------------------------------------------------------------
-//
-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
-//
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution.  The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//------------------------------------------------------------------------------
-
-#include <AsmMacroIoLib.h>
-
-    INCLUDE AsmMacroIoLib.inc
-
-    EXPORT ArmReadMidr
-    EXPORT ArmCacheInfo
-    EXPORT ArmGetInterruptState
-    EXPORT ArmGetFiqState
-    EXPORT ArmGetTTBR0BaseAddress
-    EXPORT ArmSetTTBR0
-    EXPORT ArmSetDomainAccessControl
-    EXPORT CPSRMaskInsert
-    EXPORT CPSRRead
-    EXPORT ArmReadCpacr
-    EXPORT ArmWriteCpacr
-    EXPORT ArmWriteAuxCr
-    EXPORT ArmReadAuxCr
-    EXPORT ArmInvalidateTlb
-    EXPORT ArmUpdateTranslationTableEntry
-    EXPORT ArmReadScr
-    EXPORT ArmWriteScr
-    EXPORT ArmReadMVBar
-    EXPORT ArmWriteMVBar
-    EXPORT ArmReadHVBar
-    EXPORT ArmWriteHVBar
-    EXPORT ArmCallWFE
-    EXPORT ArmCallSEV
-    EXPORT ArmReadSctlr
-    EXPORT ArmReadCpuActlr
-    EXPORT ArmWriteCpuActlr
-
-    AREA ArmLibSupport, CODE, READONLY
-
-ArmReadMidr
-  mrc     p15,0,R0,c0,c0,0
-  bx      LR
-
-ArmCacheInfo
-  mrc     p15,0,R0,c0,c0,1
-  bx      LR
-
-ArmGetInterruptState
-  mrs     R0,CPSR
-  tst     R0,#0x80      // Check if IRQ is enabled.
-  moveq   R0,#1
-  movne   R0,#0
-  bx      LR
-
-ArmGetFiqState
-  mrs     R0,CPSR
-  tst     R0,#0x40      // Check if FIQ is enabled.
-  moveq   R0,#1
-  movne   R0,#0
-  bx      LR
-
-ArmSetDomainAccessControl
-  mcr     p15,0,r0,c3,c0,0
-  bx      lr
-
-CPSRMaskInsert    // on entry, r0 is the mask and r1 is the field to insert
-  stmfd   sp!, {r4-r12, lr} // save all the banked registers
-  mov     r3, sp            // copy the stack pointer into a non-banked register
-  mrs     r2, cpsr          // read the cpsr
-  bic     r2, r2, r0        // clear mask in the cpsr
-  and     r1, r1, r0        // clear bits outside the mask in the input
-  orr     r2, r2, r1        // set field
-  msr     cpsr_cxsf, r2     // write back cpsr (may have caused a mode switch)
-  isb
-  mov     sp, r3            // restore stack pointer
-  ldmfd   sp!, {r4-r12, lr} // restore registers
-  bx      lr                // return (hopefully thumb-safe!)             // return (hopefully thumb-safe!)
-
-CPSRRead
-  mrs     r0, cpsr
-  bx      lr
-
-ArmReadCpacr
-  mrc     p15, 0, r0, c1, c0, 2
-  bx      lr
-
-ArmWriteCpacr
-  mcr     p15, 0, r0, c1, c0, 2
-  isb
-  bx      lr
-
-ArmWriteAuxCr
-  mcr     p15, 0, r0, c1, c0, 1
-  bx      lr
-
-ArmReadAuxCr
-  mrc     p15, 0, r0, c1, c0, 1
-  bx      lr
-
-ArmSetTTBR0
-  mcr     p15,0,r0,c2,c0,0
-  isb
-  bx      lr
-
-ArmGetTTBR0BaseAddress
-  mrc     p15,0,r0,c2,c0,0
-  LoadConstantToReg(0xFFFFC000, r1)
-  and     r0, r0, r1
-  isb
-  bx      lr
-
-//
-//VOID
-//ArmUpdateTranslationTableEntry (
-//  IN VOID  *TranslationTableEntry  // R0
-//  IN VOID  *MVA                    // R1
-//  );
-ArmUpdateTranslationTableEntry
-  mcr     p15,0,R0,c7,c14,1     // DCCIMVAC Clean data cache by MVA
-  dsb
-  mcr     p15,0,R1,c8,c7,1      // TLBIMVA TLB Invalidate MVA
-  mcr     p15,0,R9,c7,c5,6      // BPIALL Invalidate Branch predictor array. R9 == NoOp
-  dsb
-  isb
-  bx      lr
-
-ArmInvalidateTlb
-  mov     r0,#0
-  mcr     p15,0,r0,c8,c7,0
-  mcr     p15,0,R9,c7,c5,6      // BPIALL Invalidate Branch predictor array. R9 == NoOp
-  dsb
-  isb
-  bx      lr
-
-ArmReadScr
-  mrc     p15, 0, r0, c1, c1, 0
-  bx      lr
-
-ArmWriteScr
-  mcr     p15, 0, r0, c1, c1, 0
-  bx      lr
-
-ArmReadHVBar
-  mrc     p15, 4, r0, c12, c0, 0
-  bx      lr
-
-ArmWriteHVBar
-  mcr     p15, 4, r0, c12, c0, 0
-  bx      lr
-
-ArmReadMVBar
-  mrc     p15, 0, r0, c12, c0, 1
-  bx      lr
-
-ArmWriteMVBar
-  mcr     p15, 0, r0, c12, c0, 1
-  bx      lr
-
-ArmCallWFE
-  wfe
-  bx      lr
-
-ArmCallSEV
-  sev
-  bx      lr
-
-ArmReadSctlr
-  mrc     p15, 0, r0, c1, c0, 0      // Read SCTLR into R0 (Read control register configuration data)
-  bx      lr
-
-
-ArmReadCpuActlr
-  mrc     p15, 0, r0, c1, c0, 1
-  bx      lr
-
-ArmWriteCpuActlr
-  mcr     p15, 0, r0, c1, c0, 1
-  dsb
-  isb
-  bx      lr
-
-  END
diff --git a/ArmPkg/Library/ArmLib/Common/ArmLib.c b/ArmPkg/Library/ArmLib/Common/ArmLib.c
deleted file mode 100644
index d7316972b7..0000000000
--- a/ArmPkg/Library/ArmLib/Common/ArmLib.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-  Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Base.h>
-
-#include <Library/ArmLib.h>
-#include <Library/DebugLib.h>
-#include <Library/PcdLib.h>
-
-#include "ArmLibPrivate.h"
-
-VOID
-EFIAPI
-ArmCacheInformation (
-  OUT ARM_CACHE_INFO  *CacheInfo
-  )
-{
-  if (CacheInfo != NULL) {
-    CacheInfo->Type                           = ArmCacheType();
-    CacheInfo->Architecture                   = ArmCacheArchitecture();
-    CacheInfo->DataCachePresent               = ArmDataCachePresent();
-    CacheInfo->DataCacheSize                  = ArmDataCacheSize();
-    CacheInfo->DataCacheAssociativity         = ArmDataCacheAssociativity();
-    CacheInfo->DataCacheLineLength            = ArmDataCacheLineLength();
-    CacheInfo->InstructionCachePresent        = ArmInstructionCachePresent();
-    CacheInfo->InstructionCacheSize           = ArmInstructionCacheSize();
-    CacheInfo->InstructionCacheAssociativity  = ArmInstructionCacheAssociativity();
-    CacheInfo->InstructionCacheLineLength     = ArmInstructionCacheLineLength();
-  }
-}
-
-VOID
-EFIAPI
-ArmSetAuxCrBit (
-  IN  UINT32    Bits
-  )
-{
-  UINT32 val = ArmReadAuxCr();
-  val |= Bits;
-  ArmWriteAuxCr(val);
-}
-
-VOID
-EFIAPI
-ArmUnsetAuxCrBit (
-  IN  UINT32    Bits
-  )
-{
-  UINT32 val = ArmReadAuxCr();
-  val &= ~Bits;
-  ArmWriteAuxCr(val);
-}
-
-//
-// Helper functions for accessing CPUACTLR
-//
-
-VOID
-EFIAPI
-ArmSetCpuActlrBit (
-  IN  UINTN    Bits
-  )
-{
-  UINTN Value;
-  Value =  ArmReadCpuActlr ();
-  Value |= Bits;
-  ArmWriteCpuActlr (Value);
-}
-
-VOID
-EFIAPI
-ArmUnsetCpuActlrBit (
-  IN  UINTN    Bits
-  )
-{
-  UINTN Value;
-  Value = ArmReadCpuActlr ();
-  Value &= ~Bits;
-  ArmWriteCpuActlr (Value);
-}
diff --git a/ArmPkg/Library/ArmLib/Common/ArmLibPrivate.h b/ArmPkg/Library/ArmLib/Common/ArmLibPrivate.h
deleted file mode 100644
index fdd5a26ba0..0000000000
--- a/ArmPkg/Library/ArmLib/Common/ArmLibPrivate.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __ARM_LIB_PRIVATE_H__
-#define __ARM_LIB_PRIVATE_H__
-
-#define CACHE_SIZE_4_KB             (3UL)
-#define CACHE_SIZE_8_KB             (4UL)
-#define CACHE_SIZE_16_KB            (5UL)
-#define CACHE_SIZE_32_KB            (6UL)
-#define CACHE_SIZE_64_KB            (7UL)
-#define CACHE_SIZE_128_KB           (8UL)
-
-#define CACHE_ASSOCIATIVITY_DIRECT  (0UL)
-#define CACHE_ASSOCIATIVITY_4_WAY   (2UL)
-#define CACHE_ASSOCIATIVITY_8_WAY   (3UL)
-
-#define CACHE_PRESENT               (0UL)
-#define CACHE_NOT_PRESENT           (1UL)
-
-#define CACHE_LINE_LENGTH_32_BYTES  (2UL)
-
-#define SIZE_FIELD_TO_CACHE_SIZE(x)           (((x) >> 6) & 0x0F)
-#define SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(x)  (((x) >> 3) & 0x07)
-#define SIZE_FIELD_TO_CACHE_PRESENCE(x)       (((x) >> 2) & 0x01)
-#define SIZE_FIELD_TO_CACHE_LINE_LENGTH(x)    (((x) >> 0) & 0x03)
-
-#define DATA_CACHE_SIZE_FIELD(x)              (((x) >> 12) & 0x0FFF)
-#define INSTRUCTION_CACHE_SIZE_FIELD(x)       (((x) >>  0) & 0x0FFF)
-
-#define DATA_CACHE_SIZE(x)                    (SIZE_FIELD_TO_CACHE_SIZE(DATA_CACHE_SIZE_FIELD(x)))
-#define DATA_CACHE_ASSOCIATIVITY(x)           (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(DATA_CACHE_SIZE_FIELD(x)))
-#define DATA_CACHE_PRESENT(x)                 (SIZE_FIELD_TO_CACHE_PRESENCE(DATA_CACHE_SIZE_FIELD(x)))
-#define DATA_CACHE_LINE_LENGTH(x)             (SIZE_FIELD_TO_CACHE_LINE_LENGTH(DATA_CACHE_SIZE_FIELD(x)))
-
-#define INSTRUCTION_CACHE_SIZE(x)             (SIZE_FIELD_TO_CACHE_SIZE(INSTRUCTION_CACHE_SIZE_FIELD(x)))
-#define INSTRUCTION_CACHE_ASSOCIATIVITY(x)    (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(INSTRUCTION_CACHE_SIZE_FIELD(x)))
-#define INSTRUCTION_CACHE_PRESENT(x)          (SIZE_FIELD_TO_CACHE_PRESENCE(INSTRUCTION_CACHE_SIZE_FIELD(x)))
-#define INSTRUCTION_CACHE_LINE_LENGTH(x)      (SIZE_FIELD_TO_CACHE_LINE_LENGTH(INSTRUCTION_CACHE_SIZE_FIELD(x)))
-
-#define CACHE_TYPE(x)                         (((x) >> 25) & 0x0F)
-#define CACHE_TYPE_WRITE_BACK                 (0x0EUL)
-
-#define CACHE_ARCHITECTURE(x)                 (((x) >> 24) & 0x01)
-#define CACHE_ARCHITECTURE_UNIFIED            (0UL)
-#define CACHE_ARCHITECTURE_SEPARATE           (1UL)
-
-VOID
-CPSRMaskInsert (
-  IN  UINT32  Mask,
-  IN  UINT32  Value
-  );
-
-UINT32
-CPSRRead (
-  VOID
-  );
-
-UINT32
-ReadCCSIDR (
-  IN UINT32 CSSELR
-  );
-
-UINT32
-ReadCLIDR (
-  VOID
-  );
-
-#endif // __ARM_LIB_PRIVATE_H__
diff --git a/ArmPkg/Library/ArmLib/Null/NullArmCacheInformation.c b/ArmPkg/Library/ArmLib/Null/NullArmCacheInformation.c
deleted file mode 100644
index 2eeb42e1b7..0000000000
--- a/ArmPkg/Library/ArmLib/Null/NullArmCacheInformation.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Library/ArmLib.h>
-#include "ArmLibPrivate.h"
-
-ARM_CACHE_TYPE
-EFIAPI
-ArmCacheType (
-  VOID
-  )
-{
-  return ARM_CACHE_TYPE_UNKNOWN;
-}
-
-ARM_CACHE_ARCHITECTURE
-EFIAPI
-ArmCacheArchitecture (
-  VOID
-  )
-{
-  return ARM_CACHE_ARCHITECTURE_UNKNOWN;
-}
-
-BOOLEAN
-EFIAPI
-ArmDataCachePresent (
-  VOID
-  )
-{
-  return FALSE;
-}
-
-UINTN
-EFIAPI
-ArmDataCacheSize (
-  VOID
-  )
-{
-  return 0;
-}
-
-UINTN
-EFIAPI
-ArmDataCacheAssociativity (
-  VOID
-  )
-{
-  return 0;
-}
-
-UINTN
-EFIAPI
-ArmDataCacheLineLength (
-  VOID
-  )
-{
-  return 0;
-}
-
-BOOLEAN
-EFIAPI
-ArmInstructionCachePresent (
-  VOID
-  )
-{
-  return FALSE;
-}
-
-UINTN
-EFIAPI
-ArmInstructionCacheSize (
-  VOID
-  )
-{
-  return 0;
-}
-
-UINTN
-EFIAPI
-ArmInstructionCacheAssociativity (
-  VOID
-  )
-{
-  return 0;
-}
-
-UINTN
-EFIAPI
-ArmInstructionCacheLineLength (
-  VOID
-  )
-{
-  return 0;
-}
diff --git a/ArmPkg/Library/ArmLib/Null/NullArmLib.c b/ArmPkg/Library/ArmLib/Null/NullArmLib.c
deleted file mode 100644
index e7e9c52547..0000000000
--- a/ArmPkg/Library/ArmLib/Null/NullArmLib.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Uefi.h>
-#include <Library/ArmLib.h>
-#include <Library/DebugLib.h>
-
-VOID
-EFIAPI
-ArmCleanInvalidateDataCache (
-  VOID
-  )
-{
-  // Do not run code using the Null cache library.
-  ASSERT(FALSE);
-}
-
-VOID
-EFIAPI
-ArmCleanDataCache (
-  VOID
-  )
-{
-  // Do not run code using the Null cache library.
-  ASSERT(FALSE);
-}
-
-VOID
-EFIAPI
-ArmInvalidateInstructionCache (
-  VOID
-  )
-{
-  // Do not run code using the Null cache library.
-  ASSERT(FALSE);
-}
-
-VOID
-EFIAPI
-ArmInvalidateDataCacheEntryByMVA (
-  IN  UINTN Address
-  )
-{
-  // Do not run code using the Null cache library.
-  ASSERT(FALSE);
-}
-
-VOID
-EFIAPI
-ArmCleanDataCacheEntryByMVA (
-  IN  UINTN Address
-  )
-{
-  // Do not run code using the Null cache library.
-  ASSERT(FALSE);
-}
-
-VOID
-EFIAPI
-ArmCleanInvalidateDataCacheEntryByMVA (
-  IN  UINTN Address
-  )
-{
-  // Do not run code using the Null cache library.
-  ASSERT(FALSE);
-}
-
-VOID
-EFIAPI
-ArmEnableDataCache (
-  VOID
-  )
-{
-  // Do not run code using the Null cache library.
-  ASSERT(FALSE);
-}
-
-VOID
-EFIAPI
-ArmDisableDataCache (
-  VOID
-  )
-{
-  // Do not run code using the Null cache library.
-  ASSERT(FALSE);
-}
-
-VOID
-EFIAPI
-ArmEnableInstructionCache (
-  VOID
-  )
-{
-  // Do not run code using the Null cache library.
-  ASSERT(FALSE);
-}
-
-VOID
-EFIAPI
-ArmDisableInstructionCache (
-  VOID
-  )
-{
-  // Do not run code using the Null cache library.
-  ASSERT(FALSE);
-}
diff --git a/ArmPkg/Library/ArmLib/Null/NullArmLib.inf b/ArmPkg/Library/ArmLib/Null/NullArmLib.inf
deleted file mode 100644
index 36860a7bf9..0000000000
--- a/ArmPkg/Library/ArmLib/Null/NullArmLib.inf
+++ /dev/null
@@ -1,42 +0,0 @@
-#/** @file
-# Semihosting  serail port lib
-#
-# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution. The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#
-#**/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = NullArmLib
-  FILE_GUID                      = 00586300-0E06-4790-AC44-86C56ACBB942
-  MODULE_TYPE                    = DXE_DRIVER
-  VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = ArmLib
-
-[Sources.common]
-  ../Common/ArmLib.c
-
-  NullArmLib.c
-  NullArmCacheInformation.c
-
-[Sources.ARM]
-  ../Common/Arm/ArmLibSupport.S    | GCC
-  ../Common/Arm/ArmLibSupport.asm  | RVCT
-
-[Sources.AARCH64]
-  ../Common/AArch64/ArmLibSupport.S
-
-[Packages]
-  ArmPkg/ArmPkg.dec
-  MdePkg/MdePkg.dec
-
-[Protocols]
-  gEfiCpuArchProtocolGuid