1 files changed, 5 insertions, 5 deletions
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/InitializeFpu.s b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/InitializeFpu.s
index 782eb00bb6..924815114c 100644
--- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/InitializeFpu.s
+++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/InitializeFpu.s
@@ -12,7 +12,7 @@
 ##
 
 #
-# Float control word initial value:
+# Float control word initial value: 
 # all exceptions masked, double-precision, round-to-nearest
 #
 ASM_PFX(mFpuControlWord): .word     0x027F
@@ -40,7 +40,7 @@ ASM_PFX(InitializeFloatingPointUnits):
     #
     finit
     fldcw   ASM_PFX(mFpuControlWord)
-
+    
     #
     # Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
     # whether the processor supports SSE instruction.
@@ -49,14 +49,14 @@ ASM_PFX(InitializeFloatingPointUnits):
     cpuid
     btl     $25, %edx
     jnc     Done
-
+    
     #
     # Set OSFXSR bit 9 in CR4
     #
-    movl    %cr4, %eax
+    movl    %cr4, %eax 
     or      $0x200, %eax
     movl    %eax, %cr4
-
+    
     #
     # The processor should support SSE instruction and we can use
     # ldmxcsr instruction