diff options
Diffstat (limited to 'BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit')
38 files changed, 347 insertions, 324 deletions
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Cpu.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Cpu.c index e8ef367545..71d138f7b2 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Cpu.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Cpu.c @@ -232,7 +232,7 @@ DisableInterrupt ( @param[out] State Pointer to the CPU's current interrupt state
@retval EFI_SUCCESS If interrupts were disabled in the CPU.
- @retval EFI_INVALID_PARAMETER State is NULL.
+ @retval EFI_INVALID_PARAMETER State is NULL.
**/
EFI_STATUS
@@ -629,7 +629,7 @@ Done: }
/**
- @todo Add structure description
+ @todo Add structure description
**/
typedef struct {
@@ -839,7 +839,7 @@ InitializeCpu ( /**
Determine the processor core frequency
- @retval Processor core frequency multiplied by 3
+ @retval Processor core frequency multiplied by 3
**/
UINT16
@@ -997,3 +997,4 @@ ApCpuInitBeforeBoot ( )
{
}
+
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/CpuDataStruct.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/CpuDataStruct.h index 5d61762969..4ad78dd033 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/CpuDataStruct.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/CpuDataStruct.h @@ -119,3 +119,4 @@ typedef struct { } EFI_CPU_VERSION;
#endif
+
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/CpuDxe.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/CpuDxe.h index 9ead237ffe..f3a67032f5 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/CpuDxe.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/CpuDxe.h @@ -49,7 +49,7 @@ #include "CpuDataStruct.h"
#define BSEL_CR_OVERCLOCK_CONTROL 0xCD
-#define FUSE_BSEL_MASK 0x07
+#define FUSE_BSEL_MASK 0x07
#define INTERRUPT_VECTOR_NUMBER 256
#define INTERRUPT_GATE_ATTRIBUTE 0x8e00
@@ -238,3 +238,4 @@ PCIConfigWA ( )
#endif
+
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/CpuRegs.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/CpuRegs.h index 5dd1d959e0..e2d2abf4df 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/CpuRegs.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/CpuRegs.h @@ -408,3 +408,4 @@ typedef enum { #pragma pack()
#endif
+
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Exception.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Exception.h index 695670458a..29c04a31bd 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Exception.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Exception.h @@ -69,3 +69,4 @@ InitializeException ( IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol
);
#endif
+
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/CpuAsm.asm b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/CpuAsm.asm index dfc81eeed8..c47d0042f2 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/CpuAsm.asm +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/CpuAsm.asm @@ -14,7 +14,7 @@ page ,132
title CPU ARCHITECTURAL DXE PROTOCOL ASSEMBLY HOOKS
.686p
-.model flat
+.model flat
.data
ExternalVectorTablePtr DD ? ; Table of call backs
@@ -40,47 +40,47 @@ UINTN TYPEDEF UINT32 ;---------------------------------------;
; _InitializeIdt ;
;----------------------------------------------------------------------------;
-;
+;
; Protocol prototype
; InitializeIdt (
; IN EFI_CPU_INTERRUPT_HANDLER TableStart,
; IN UINTN *IdtTablePtr,
; IN UINT16 IdtLimit
; )
-;
+;
; Routine Description:
-;
+;
; Creates an IDT table starting at IdtTablPtr. It has IdtLimit/8 entries.
; Table is initialized to intxx where xx is from 00 to number of entries or
; 100h, whichever is smaller. After table has been initialized the LIDT
; instruction is invoked.
-;
-; TableStart is the pointer to the callback table and is not used by
+;
+; TableStart is the pointer to the callback table and is not used by
; InitializedIdt but by commonEntry. CommonEntry handles all interrupts,
; does the context save and calls the callback entry, if non-NULL.
; It is the responsibility of the callback routine to do hardware EOIs.
-;
+;
; Arguments:
-;
+;
; TableStart - Pointer to interrupt callback table
;
; IdtTablePtr - Pointer to IDT table
;
; IdtLimit - IDT Table limit = number of interrupt entries * 8
-;
-; Returns:
-;
+;
+; Returns:
+;
; Nothing
;
-;
+;
; Input: [ebp][0] = Original ebp
; [ebp][4] = Return address
; [ebp][8] = TableStart
; [ebp][0c] = *IdtTablePtr
; [ebp][10] = IdtLimit
-;
+;
; Output: Nothing
-;
+;
; Destroys: Nothing
;-----------------------------------------------------------------------------;
@@ -98,7 +98,7 @@ _InitializeIdt proc near public mov eax, [ebp+0ch] ; Get Start of IDT
mov Idtr1, eax
-
+
mov edi, OFFSET Idtr ; Load IDT register
lidt FWORD PTR es:[edi]
@@ -108,45 +108,45 @@ _InitializeIdt proc near public _InitializeIdt endp
;----------------------------------------------------------------------------;
-;
+;
; Protocol prototype
; None
-;
+;
; Routine Description:
-;
+;
; These routines handle the individual interrupts. These routines always
; gain control on any interrupt or exception. They save EAX and place
-; the interrupt number in EAX. CommonEntry is then jumped to.
+; the interrupt number in EAX. CommonEntry is then jumped to.
; instruction is invoked.
-;
-; CommonEntry handles all interrupts,does the context save and calls the
-; callback entry, if non-NULL. It is the responsibility of the callback
+;
+; CommonEntry handles all interrupts,does the context save and calls the
+; callback entry, if non-NULL. It is the responsibility of the callback
; routine to do hardware EOIs. Callbacks are entered into the table
; located at TableStart. Entries are modified by the InstallInterruptHandler
; and UninstallInterruptHandler protocols.
-;
+;
; Arguments to CommonEntry:
-;
+;
; EAX - Interrupt or exception number
;
; TableStart - Pointer to interrupt callback table
-;
-; Returns:
-;
+;
+; Returns:
+;
; Nothing
;
-;
+;
; Output: Nothing
-;
+;
; Destroys: Nothing
;-----------------------------------------------------------------------------;
TemplateStart:
push eax
-
- ;mov eax, 0nnh (nn stands for vector number, which will be fixed at runtime
+
+ ;mov eax, 0nnh (nn stands for vector number, which will be fixed at runtime
DB 0b8h
-VectorNumber:
+VectorNumber:
DD 00h
jmp dword ptr [CommonInterruptEntry];
@@ -193,7 +193,7 @@ NoErrorCode: ;
push [esp]
mov dword ptr [esp + 4], 0
-@@:
+@@:
push ebp
mov ebp, esp
@@ -385,30 +385,30 @@ nonNullValue: ;---------------------------------------;
; _GetTemplateAddressMap ;
;----------------------------------------------------------------------------;
-;
+;
; Protocol prototype
; GetTemplateAddressMap (
; INTERRUPT_HANDLER_TEMPLATE_MAP *AddressMap
; );
-;
+;
; Routine Description:
-;
+;
; Return address map of interrupt handler template so that C code can generate
; interrupt handlers, and dynamically do address fix.
-;
+;
; Arguments:
-;
-;
-; Returns:
-;
+;
+;
+; Returns:
+;
; Nothing
;
-;
+;
; Input: [ebp][0] = Original ebp
; [ebp][4] = Return address
-;
+;
; Output: Nothing
-;
+;
; Destroys: Nothing
;-----------------------------------------------------------------------------;
_GetTemplateAddressMap proc near public
@@ -419,8 +419,8 @@ _GetTemplateAddressMap proc near public mov ebx, dword ptr [ebp+08h]
mov dword ptr [ebx], TemplateStart
mov dword ptr [ebx+4h], TemplateEnd - TemplateStart
-
- ; if code in Template is updated, the value fills into the 3rd parameter
+
+ ; if code in Template is updated, the value fills into the 3rd parameter
; also needs update
mov dword ptr [ebx+8h], VectorNumber - TemplateStart
@@ -434,31 +434,31 @@ _GetTemplateAddressMap endp ;---------------------------------------;
; _InitializeSelectors ;
;----------------------------------------------------------------------------;
-;
+;
; Protocol prototype
; InitializeSelectors (
; )
-;
+;
; Routine Description:
-;
+;
; Creates an new GDT in RAM. The problem is that our former selectors
-; were ROM based and the EFI OS Loader does not manipulate the machine state
+; were ROM based and the EFI OS Loader does not manipulate the machine state
; to change them (as it would for a 16-bit PC/AT startup code that had to
; go from Real Mode to flat mode).
-;
+;
; Arguments:
-;
-;
-; Returns:
-;
+;
+;
+; Returns:
+;
; Nothing
;
-;
+;
; Input: [ebp][0] = Original ebp
; [ebp][4] = Return address
-;
+;
; Output: Nothing
-;
+;
; Destroys: Nothing
;-----------------------------------------------------------------------------;
@@ -471,7 +471,7 @@ _InitializeSelectors proc near public pushad
mov edi, OFFSET Gdtr ; Load GDT register
- mov ax,cs ; Get the selector data from our code image
+ mov ax,cs ; Get the selector data from our code image
mov es,ax
lgdt FWORD PTR es:[edi] ; and update the GDTR
@@ -485,13 +485,13 @@ SelectorRld:: mov es, ax
mov fs, ax
mov gs, ax
- mov ss, ax
+ mov ss, ax
popad
pop ebp
ret
_InitializeSelectors endp
-
+
;------------------------------------------------------------------------------
; VOID
; CpuEnableInterrupt (
@@ -513,7 +513,7 @@ CpuEnableInterrupt ENDP CpuDisableInterrupt PROC C PUBLIC
cli
ret
-CpuDisableInterrupt ENDP
+CpuDisableInterrupt ENDP
;------------------------------------------------------------------------------
; VOID
@@ -535,7 +535,7 @@ CpuInitFloatPointUnit ENDP GetCodeSegment PROC C PUBLIC
mov ax,cs
ret
-GetCodeSegment ENDP
+GetCodeSegment ENDP
;------------------------------------------------------------------------------
@@ -569,7 +569,7 @@ EfiInvd ENDP ;------------------------------------------------------------------------------
_GetIdt proc near public
push ebp ; C prolog
-
+
mov ebp, esp
mov eax, [ebp+8]
sidt FWORD PTR [eax]
@@ -581,19 +581,19 @@ _GetIdt ENDP GetCoreNumber PROC C PUBLIC
push ebx
-
+
mov eax, 4
mov ecx, 0
cpuid
-
+
shr eax, 26
and eax, 3fh
inc al
-
+
pop ebx
-
+
ret
-
+
GetCoreNumber ENDP
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/CpuAsm.s b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/CpuAsm.s index 9b62ca1688..bac06d08f8 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/CpuAsm.s +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/CpuAsm.s @@ -39,7 +39,7 @@ Idtr1: .space 4 .equ IdtrProfile , LockLocation + 0x16
.equ BufferStart , LockLocation + 0x1C
.equ Cr3Location , LockLocation + 0x20
-.equ InitFlag , LockLocation + 0x24
+.equ InitFlag , LockLocation + 0x24
.equ WakeUpApManner , LockLocation + 0x28
.equ BistBuffer , LockLocation + 0x2C
@@ -53,47 +53,47 @@ Idtr1: .space 4 #---------------------------------------#
# _InitializeIdt #
#----------------------------------------------------------------------------#
-#
+#
# Protocol prototype
# InitializeIdt (
# IN EFI_CPU_INTERRUPT_HANDLER TableStart,
# IN UINTN *IdtTablePtr,
# IN UINT16 IdtLimit
# )
-#
+#
# Routine Description:
-#
+#
# Creates an IDT table starting at IdtTablPtr. It has IdtLimit/8 entries.
# Table is initialized to intxx where xx is from 00 to number of entries or
# 100h, whichever is smaller. After table has been initialized the LIDT
# instruction is invoked.
-#
-# TableStart is the pointer to the callback table and is not used by
+#
+# TableStart is the pointer to the callback table and is not used by
# InitializedIdt but by commonEntry. CommonEntry handles all interrupts,
# does the context save and calls the callback entry, if non-NULL.
# It is the responsibility of the callback routine to do hardware EOIs.
-#
+#
# Arguments:
-#
+#
# TableStart - Pointer to interrupt callback table
#
# IdtTablePtr - Pointer to IDT table
#
# IdtLimit - IDT Table limit = number of interrupt entries * 8
-#
-# Returns:
-#
+#
+# Returns:
+#
# Nothing
#
-#
+#
# Input: [ebp][0] = Original ebp
# [ebp][4] = Return address
# [ebp][8] = TableStart
# [ebp][0c] = *IdtTablePtr
# [ebp][10] = IdtLimit
-#
+#
# Output: Nothing
-#
+#
# Destroys: Nothing
#-----------------------------------------------------------------------------#
@@ -121,51 +121,51 @@ ASM_PFX(InitializeIdt): ret
#----------------------------------------------------------------------------#
-#
+#
# Protocol prototype
# None
-#
+#
# Routine Description:
-#
+#
# These routines handle the individual interrupts. These routines always
# gain control on any interrupt or exception. They save EAX and place
-# the interrupt number in EAX. CommonEntry is then jumped to.
+# the interrupt number in EAX. CommonEntry is then jumped to.
# instruction is invoked.
-#
-# CommonEntry handles all interrupts,does the context save and calls the
-# callback entry, if non-NULL. It is the responsibility of the callback
+#
+# CommonEntry handles all interrupts,does the context save and calls the
+# callback entry, if non-NULL. It is the responsibility of the callback
# routine to do hardware EOIs. Callbacks are entered into the table
# located at TableStart. Entries are modified by the InstallInterruptHandler
# and UninstallInterruptHandler protocols.
-#
+#
# Arguments to CommonEntry:
-#
+#
# EAX - Interrupt or exception number
#
# TableStart - Pointer to interrupt callback table
-#
-# Returns:
-#
+#
+# Returns:
+#
# Nothing
#
-#
+#
# Output: Nothing
-#
+#
# Destroys: Nothing
#-----------------------------------------------------------------------------#
-TemplateStart:
+TemplateStart:
pushl %eax
- #mov eax, 0nnh (nn stands for vector number, which will be fixed at runtime
+ #mov eax, 0nnh (nn stands for vector number, which will be fixed at runtime
.byte 0xb8
-VectorNumber:
+VectorNumber:
.long 0x0
jmp *CommonInterruptEntry
-TemplateEnd:
+TemplateEnd:
-CommonEntry:
+CommonEntry:
#---------------------------------------#
# _CommonEntry #
@@ -199,7 +199,7 @@ CommonEntry: btl %eax, %cs:ASM_PFX(mErrorCodeFlag)
jc L1
-NoErrorCode:
+NoErrorCode:
#
# Push a dummy error code on the stack
# to maintain coherent stack map
@@ -324,7 +324,7 @@ L1: call *%eax
addl $8, %esp
-nonNullValue:
+nonNullValue:
cli
## UINT32 ExceptionData#
@@ -402,30 +402,30 @@ nonNullValue: #---------------------------------------#
# _GetTemplateAddressMap #
#----------------------------------------------------------------------------#
-#
+#
# Protocol prototype
# GetTemplateAddressMap (
# INTERRUPT_HANDLER_TEMPLATE_MAP *AddressMap
# )#
-#
+#
# Routine Description:
-#
+#
# Return address map of interrupt handler template so that C code can generate
# interrupt handlers, and dynamically do address fix.
-#
+#
# Arguments:
-#
-#
-# Returns:
-#
+#
+#
+# Returns:
+#
# Nothing
#
-#
+#
# Input: [ebp][0] = Original ebp
# [ebp][4] = Return address
-#
+#
# Output: Nothing
-#
+#
# Destroys: Nothing
#-----------------------------------------------------------------------------#
ASM_GLOBAL ASM_PFX(GetTemplateAddressMap)
@@ -438,7 +438,7 @@ ASM_PFX(GetTemplateAddressMap): movl $TemplateStart, (%ebx)
movl $(TemplateEnd - TemplateStart), 4(%ebx)
- # Note: if code in Template is updated, the value fills into the 3rd parameter
+ # Note: if code in Template is updated, the value fills into the 3rd parameter
# also needs update
movl $(VectorNumber - TemplateStart), 8(%ebx)
@@ -451,31 +451,31 @@ ASM_PFX(GetTemplateAddressMap): #---------------------------------------#
# _InitializeSelectors #
#----------------------------------------------------------------------------#
-#
+#
# Protocol prototype
# InitializeSelectors (
# )
-#
+#
# Routine Description:
-#
+#
# Creates an new GDT in RAM. The problem is that our former selectors
-# were ROM based and the EFI OS Loader does not manipulate the machine state
+# were ROM based and the EFI OS Loader does not manipulate the machine state
# to change them (as it would for a 16-bit PC/AT startup code that had to
# go from Real Mode to flat mode).
-#
+#
# Arguments:
-#
-#
-# Returns:
-#
+#
+#
+# Returns:
+#
# Nothing
#
-#
+#
# Input: [ebp][0] = Original ebp
# [ebp][4] = Return address
-#
+#
# Output: Nothing
-#
+#
# Destroys: Nothing
#-----------------------------------------------------------------------------#
@@ -489,7 +489,7 @@ ASM_PFX(InitializeSelectors): pushal
movl $Gdtr, %edi
- movw %cs,%ax # Get the selector data from our code image
+ movw %cs,%ax # Get the selector data from our code image
.byte 0x66
movw %ax,%es
lgdt %es:(%edi)
@@ -538,7 +538,7 @@ ASM_GLOBAL ASM_PFX(CpuDisableInterrupt) ASM_PFX(CpuDisableInterrupt):
cli
ret
-#CpuDisableInterrupt ENDP
+#CpuDisableInterrupt ENDP
#------------------------------------------------------------------------------
# VOID
@@ -562,7 +562,7 @@ ASM_GLOBAL ASM_PFX(GetCodeSegment) ASM_PFX(GetCodeSegment):
movw %cs, %ax
ret
-#GetCodeSegment ENDP
+#GetCodeSegment ENDP
#------------------------------------------------------------------------------
@@ -598,7 +598,7 @@ ASM_PFX(EfiInvd): ASM_GLOBAL ASM_PFX(GetIdt)
ASM_PFX(GetIdt):
push %ebp # C prolog
-
+
movl %esp, %ebp
movl 8(%ebp), %eax
sidt (%eax)
@@ -621,7 +621,7 @@ ASM_PFX(C1eExceptionHandler): cli
pushal
- # Verify if GPE was caused by C1e write.
+ # Verify if GPE was caused by C1e write.
# If not, pass control to real exception handler.
cmp $0, ASM_PFX(mWroteMsr)
je notourexception
@@ -654,19 +654,19 @@ ASM_GLOBAL ASM_PFX(GetCoreNumber) ASM_PFX(GetCoreNumber):
pushl %ebx
-
+
movl $4, %eax
movl $0, %ecx
cpuid
-
+
shrl $26, %eax
andl $0x3f, %eax
incb %al
-
+
popl %ebx
-
+
ret
-
+
#GetCoreNumber ENDP
#-----------------------------------------------------------------------------#
@@ -684,7 +684,7 @@ Gdtr: .word GDT_END - GDT_BASE - 1 .p2align 4
-GDT_BASE:
+GDT_BASE:
# null descriptor
# .equ NULL_SEL, $-GDT_BASE # Selector [0]
.word 0 # limit 15:0
@@ -757,5 +757,5 @@ GDT_BASE: .byte 0 # page-granular, 32-bit
.byte 0
-GDT_END:
+GDT_END:
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/Exception.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/Exception.c index 89734ddfe2..cfad3e6044 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/Exception.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/Exception.c @@ -24,7 +24,7 @@ VOID IN VOID *SystemContext
);
/**
- @todo No description
+ @todo No description
**/
typedef struct {
@@ -335,3 +335,4 @@ InitializeException ( return Status;
}
+
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/Htequ.inc b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/Htequ.inc index 5554cefd42..95f00adaa8 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/Htequ.inc +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/Htequ.inc @@ -29,7 +29,7 @@ GdtrProfile equ LockLocation + 10h IdtrProfile equ LockLocation + 16h
BufferStart equ LockLocation + 1Ch
Cr3Location equ LockLocation + 20h
-InitFlag equ LockLocation + 24h
+InitFlag equ LockLocation + 24h
WakeUpApManner equ LockLocation + 28h
BistBuffer equ LockLocation + 2Ch
PAUSE32 MACRO
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/InitializeFpu.s b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/InitializeFpu.s index 782eb00bb6..924815114c 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/InitializeFpu.s +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/InitializeFpu.s @@ -12,7 +12,7 @@ ##
#
-# Float control word initial value:
+# Float control word initial value:
# all exceptions masked, double-precision, round-to-nearest
#
ASM_PFX(mFpuControlWord): .word 0x027F
@@ -40,7 +40,7 @@ ASM_PFX(InitializeFloatingPointUnits): #
finit
fldcw ASM_PFX(mFpuControlWord)
-
+
#
# Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
# whether the processor supports SSE instruction.
@@ -49,14 +49,14 @@ ASM_PFX(InitializeFloatingPointUnits): cpuid
btl $25, %edx
jnc Done
-
+
#
# Set OSFXSR bit 9 in CR4
#
- movl %cr4, %eax
+ movl %cr4, %eax
or $0x200, %eax
movl %eax, %cr4
-
+
#
# The processor should support SSE instruction and we can use
# ldmxcsr instruction
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MPFuncs32.asm b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MPFuncs32.asm index 1350addb7d..3f15ff3749 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MPFuncs32.asm +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MPFuncs32.asm @@ -14,8 +14,8 @@ ;;
.686p
-.model flat
-.code
+.model flat
+.code
include Htequ.inc
;-------------------------------------------------------------------------------------
@@ -51,7 +51,7 @@ RendezvousFunnelProcStart:: db 8ch, 0c8h ; mov ax, cs
db 8eh, 0d8h ; mov ds, ax
db 8eh, 0c0h ; mov es, ax
- db 8eh, 0d0h ; mov ss, ax
+ db 8eh, 0d0h ; mov ss, ax
db 33h, 0c0h ; xor ax, ax
db 8eh, 0e0h ; mov fs, ax
db 8eh, 0e8h ; mov gs, ax
@@ -76,18 +76,18 @@ RendezvousFunnelProcStart:: ;
db 0B0h, 08h ; mov al, 8
db 0F6h, 0E3h ; mul bl
-
+
db 0BEh, 2Ch, 0Ch ; mov si, BistBuffer
db 03h, 0F0h ; add si, ax
-
+
db 66h, 0C7h, 04h
dd 00000001h ; mov dword ptr [si], 1 ; Set Valid Flag
- db 66h, 89h, 6Ch, 04h ; mov dword ptr [si + 4], ebp ; Store BIST value
-
+ db 66h, 89h, 6Ch, 04h ; mov dword ptr [si + 4], ebp ; Store BIST value
+
cli
hlt
jmp $-2
-
+
; Switch to flat mode.
flat32Start::
@@ -99,12 +99,12 @@ flat32Start:: db 0BEh, 10h, 0Ch ; mov si, GdtrProfile
db 66h ; db 66h
db 2Eh,0Fh, 01h, 14h ; lgdt fword ptr cs:[si]
-
+
db 0BEh, 16h, 0Ch ; mov si, IdtrProfile
db 66h ; db 66h
db 2Eh,0Fh, 01h, 1Ch ; lidt fword ptr cs:[si]
-
-
+
+
db 33h, 0C0h ; xor ax, ax
db 8Eh, 0D8h ; mov ds, ax
db 0Fh, 20h, 0C0h ; mov eax, cr0 ; Get control register 0
@@ -139,23 +139,23 @@ ProgramStaticStack:: mov edi, esi
add edi, BistBuffer
mov ecx, dword ptr [edi + 8 * ebx] ; EBX = CpuNumber
-
+
mov edi, esi
add edi, StackSize
mov eax, dword ptr [edi]
- inc ecx
+ inc ecx
mul ecx ; EAX = StackSize * (CpuNumber + 1)
-
+
mov edi, esi
add edi, StackStart
mov edx, dword ptr [edi]
add eax, edx ; EAX = StackStart + StackSize * (CpuNumber + 1)
-
+
mov esp, eax
sub esp, MonitorFilterSize ; Reserved Monitor data space
or ebx, StartupApSignal ; ebx = #Cpu run signature
jmp ProgramLocalApic
-
+
ProgramDynamicStack::
mov edi, esi
@@ -215,7 +215,7 @@ EnableXmm:: mov eax, cr4
or eax, 600h
mov cr4, eax
-
+
@@:
;
; Call C Function
@@ -290,7 +290,7 @@ HltApLoop:: cli
hlt
jmp HltApLoop
-
+
RendezvousFunnelProc ENDP
RendezvousFunnelProcEnd::
;-------------------------------------------------------------------------------------
@@ -300,19 +300,19 @@ AsmGetAddressMap PROC near C PUBLIC pushad
mov ebp,esp
-
+
mov ebx, dword ptr [ebp+24h]
mov dword ptr [ebx], RendezvousFunnelProcStart
mov dword ptr [ebx+4h], PMODE_ENTRY - RendezvousFunnelProcStart
mov dword ptr [ebx+8h], FLAT32_JUMP - RendezvousFunnelProcStart
mov dword ptr [ebx+0ch], RendezvousFunnelProcEnd - RendezvousFunnelProcStart
-
+
popad
ret
AsmGetAddressMap ENDP
;-------------------------------------------------------------------------------------
-;AsmExchangeRole procedure follows. This procedure executed by current BSP, that is
+;AsmExchangeRole procedure follows. This procedure executed by current BSP, that is
;about to become an AP. It switches it'stack with the current AP.
;AsmExchangeRole (IN CPU_EXCHANGE_INFO *MyInfo, IN CPU_EXCHANGE_INFO *OthersInfo);
;-------------------------------------------------------------------------------------
@@ -336,7 +336,7 @@ AsmExchangeRole PROC near C PUBLIC pushfd
sgdt fword ptr [esi+8]
sidt fword ptr [esi+14]
-
+
; Store the its StackPointer
mov dword ptr [esi+4],esp
@@ -349,13 +349,13 @@ TryLock1: jz LockObtained1
PAUSE32
jmp TryLock1
-
+
LockObtained1:
mov byte ptr [esi+1], CPU_SWITCH_STATE_STORED
db 0f0h ; opcode for lock instruction
xchg al, byte ptr [esi]
-WaitForOtherStored::
+WaitForOtherStored::
; wait until the other CPU finish storing its state
mov al, NotVacantFlag
TryLock2:
@@ -365,24 +365,24 @@ TryLock2: jz LockObtained2
PAUSE32
jmp TryLock2
-
+
LockObtained2:
mov bl, byte ptr [edi+1]
db 0f0h ; opcode for lock instruction
xchg al, byte ptr [edi]
cmp bl, CPU_SWITCH_STATE_STORED
jb WaitForOtherStored
-
+
; Since another CPU already stored its state, load them
; load GDTR value
lgdt fword ptr [edi+8]
-
+
; load IDTR value
lidt fword ptr [edi+14]
; load its future StackPointer
mov esp, dword ptr [edi+4]
-
+
; update its switch state to LOADED
mov al, NotVacantFlag
TryLock3:
@@ -392,7 +392,7 @@ TryLock3: jz LockObtained3
PAUSE32
jmp TryLock3
-
+
LockObtained3:
mov byte ptr [esi+1], CPU_SWITCH_STATE_LOADED
db 0f0h ; opcode for lock instruction
@@ -409,7 +409,7 @@ TryLock4: jz LockObtained4
PAUSE32
jmp TryLock4
-
+
LockObtained4:
mov bl, byte ptr [edi+1]
db 0f0h ; opcode for lock instruction
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MPFuncs32.s b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MPFuncs32.s index fd44beae0b..01c5e22164 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MPFuncs32.s +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MPFuncs32.s @@ -32,7 +32,7 @@ .equ IdtrProfile , LockLocation + 0x16
.equ BufferStart , LockLocation + 0x1C
.equ Cr3Location , LockLocation + 0x20
-.equ InitFlag , LockLocation + 0x24
+.equ InitFlag , LockLocation + 0x24
.equ WakeUpApManner , LockLocation + 0x28
.equ BistBuffer , LockLocation + 0x2C
@@ -50,7 +50,7 @@ .long \Offset # 32-bit offset
.word \Selector # 16-bit selector
.endm
-
+
.macro FCALL32 Selector, Offset
.byte 0x09A
.long \Offset # 32-bit offset
@@ -102,18 +102,18 @@ RendezvousFunnelProcStart: #
.byte 0xB0, 0x08 # mov al, 8
.byte 0xF6, 0xE3 # mul bl
-
+
.byte 0xBE, 0x2C, 0x0C # mov si, BistBuffer
.byte 0x03, 0xF0 # add si, ax
.byte 0x66, 0xC7, 0x04
.byte 0x00000001 # mov dword ptr [si], 1 # Set Valid Flag
- .byte 0x66, 0x89, 0x6C, 0x04 # mov dword ptr [si + 4], ebp # Store BIST value
-
+ .byte 0x66, 0x89, 0x6C, 0x04 # mov dword ptr [si + 4], ebp # Store BIST value
+
cli
hlt
jmp .-2
-
+
# Switch to flat mode.
flat32Start:
@@ -125,12 +125,12 @@ flat32Start: .byte 0xBE, 0x10, 0x0C # mov si, GdtrProfile
.byte 0x66 # db 66h
.byte 0x2E, 0x0F, 0x01, 0x14 # lgdt fword ptr cs:[si]
-
+
.byte 0xBE, 0x16, 0x0C # mov si, IdtrProfile
.byte 0x66 # db 66h
.byte 0x2E, 0x0F, 0x01, 0x1C # lidt fword ptr cs:[si]
-
-
+
+
.byte 0x33, 0xC0 # xor ax, ax
.byte 0x8E, 0xD8 # mov ds, ax
.byte 0x0F, 0x20, 0xC0 # mov eax, cr0 # Get control register 0
@@ -156,7 +156,7 @@ PMODE_ENTRY: # protected mode entry point movl %esi,%edi
addl $InitFlag, %edi
- cmpl $2, (%edi) # Check whether in S3 boot path
+ cmpl $2, (%edi) # Check whether in S3 boot path
jz ProgramDynamicStack
ProgramStaticStack:
@@ -165,23 +165,23 @@ ProgramStaticStack: movl %esi, %edi
addl $BistBuffer, %edi
movl (%edi, %ebx, 8), %ecx # EBX = CpuNumber
-
+
movl %esi, %edi
addl $StackSize, %edi
movl (%edi), %eax
- incl %ecx
+ incl %ecx
mull %ecx # EAX = StackSize * (CpuNumber + 1)
-
+
movl %esi, %edi
addl $StackStart, %edi
movl (%edi), %edx
addl %edx, %eax # EAX = StackStart + StackSize * (CpuNumber + 1)
-
+
movl %eax, %esp
subl $MonitorFilterSize, %esp # Reserved Monitor data space
orl $StartupApSignal, %ebx # EBX = #Cpu run signature
jmp ProgramLocalApic
-
+
ProgramDynamicStack:
movl %esi, %edi
@@ -219,7 +219,7 @@ ProgramLocalApic: movl (%edi), %eax
andl $0x0FFFE00FF, %eax
orl $0x700, %eax
- movl %eax, (%edi)
+ movl %eax, (%edi)
movl $0x0FEE00360, %edi
movl (%edi), %eax
@@ -236,17 +236,17 @@ EnableXmm: #
movl %cr0, %eax
orl $2, %eax
- movl %eax, %cr0
+ movl %eax, %cr0
movl %cr4, %eax
orl $0x600, %eax
movl %eax, %cr4
-
+
L1:
#
# Call C Function
#
movl %esi, %edi
- addl $RendezvousProc, %edi
+ addl $RendezvousProc, %edi
addl $WakeUpApManner, %esi # esi = WakeUpApManner Address Location
WakeUpThisAp:
@@ -315,7 +315,7 @@ HltApLoop: cli
hlt
jmp HltApLoop
-
+
#RendezvousFunnelProc ENDP
RendezvousFunnelProcEnd:
@@ -326,19 +326,19 @@ ASM_GLOBAL ASM_PFX(AsmGetAddressMap) ASM_PFX(AsmGetAddressMap):
pushal
movl %esp, %ebp
-
+
movl 0x24(%ebp), %ebx
movl $RendezvousFunnelProcStart, (%ebx)
- movl $(PMODE_ENTRY - RendezvousFunnelProcStart), 0x4(%ebx)
+ movl $(PMODE_ENTRY - RendezvousFunnelProcStart), 0x4(%ebx)
movl $(FLAT32_JUMP - RendezvousFunnelProcStart), 0x8(%ebx)
movl $(RendezvousFunnelProcEnd - RendezvousFunnelProcStart), 0xc(%ebx)
-
+
popal
ret
#AsmGetAddressMap ENDP
#-------------------------------------------------------------------------------------
-#AsmExchangeRole procedure follows. This procedure executed by current BSP, that is
+#AsmExchangeRole procedure follows. This procedure executed by current BSP, that is
#about to become an AP. It switches it'stack with the current AP.
#AsmExchangeRole (IN CPU_EXCHANGE_INFO *MyInfo, IN CPU_EXCHANGE_INFO *OthersInfo)#
#-------------------------------------------------------------------------------------
@@ -363,7 +363,7 @@ ASM_PFX(AsmExchangeRole): pushfl
sgdt 8(%esi)
sidt 14(%esi)
-
+
# Store the its StackPointer
movl %esp, 4(%esi)
@@ -375,11 +375,11 @@ TryLock1: jz LockObtained1
PAUSE32
jmp TryLock1
-
+
LockObtained1:
movb $CPU_SWITCH_STATE_STORED, 1(%esi)
lock xchgb (%esi), %al
-WaitForOtherStored:
+WaitForOtherStored:
# wait until the other CPU finish storing its state
movb $NotVacantFlag, %al
TryLock2:
@@ -388,23 +388,23 @@ TryLock2: jz LockObtained2
PAUSE32
jmp TryLock2
-
+
LockObtained2:
movb 1(%edi), %bl
lock xchgb (%edi), %al
cmpb $CPU_SWITCH_STATE_STORED, %bl
jb WaitForOtherStored
-
+
# Since another CPU already stored its state, load them
# load GDTR value
lgdt 8(%edi)
-
+
# load IDTR value
lidt 14(%edi)
# load its future StackPointer
movl 4(%edi), %esp
-
+
# update its switch state to LOADED
movb $NotVacantFlag, %al
TryLock3:
@@ -413,7 +413,7 @@ TryLock3: jz LockObtained3
PAUSE32
jmp TryLock3
-
+
LockObtained3:
movb $CPU_SWITCH_STATE_LOADED, 1(%esi)
lock xchgb (%esi), %al
@@ -428,7 +428,7 @@ TryLock4: jz LockObtained4
PAUSE32
jmp TryLock4
-
+
LockObtained4:
movb 1(%edi), %bl
lock xchgb (%edi), %al
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpCommon32.asm b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpCommon32.asm index 25434ad41f..1e422f34d0 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpCommon32.asm +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpCommon32.asm @@ -14,14 +14,14 @@ ;;
.686p
-.model flat
+.model flat
.data
.stack
.code
.MMX
.XMM
- include Htequ.inc
+ include Htequ.inc
PAUSE32 MACRO
DB 0F3h
DB 090h
@@ -44,7 +44,7 @@ TryGetLock: jz LockObtained
PAUSE32
- jmp TryGetLock
+ jmp TryGetLock
LockObtained:
popad
@@ -52,7 +52,7 @@ LockObtained: AsmAcquireMPLock ENDP
;-------------------------------------------------------------------------------
-; AsmReleaseMPLock (&Lock);
+; AsmReleaseMPLock (&Lock);
;-------------------------------------------------------------------------------------
AsmReleaseMPLock PROC near C PUBLIC
@@ -63,13 +63,13 @@ AsmReleaseMPLock PROC near C PUBLIC mov ebx, dword ptr [ebp+24h]
db 0f0h ; opcode for lock instruction
xchg al, byte ptr [ebx]
-
+
popad
ret
AsmReleaseMPLock ENDP
;-------------------------------------------------------------------------------
-; AsmGetGdtrIdtr (&Gdt, &Idt);
+; AsmGetGdtrIdtr (&Gdt, &Idt);
;-------------------------------------------------------------------------------------
AsmGetGdtrIdtr PROC near C PUBLIC
@@ -85,7 +85,7 @@ AsmGetGdtrIdtr PROC near C PUBLIC lea esi, IdtDesc
mov edi, dword ptr [ebp+28h]
mov dword ptr [edi], esi
-
+
popad
ret
AsmGetGdtrIdtr ENDP
@@ -100,4 +100,4 @@ IdtDesc:: ; IDT descriptor DW 0h ; IDT base and limit will be
DW 0h ; filled using sidt
-END
+END
\ No newline at end of file diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpCommon32.s b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpCommon32.s index dc110da96a..49877954d3 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpCommon32.s +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpCommon32.s @@ -32,7 +32,7 @@ .equ IdtrProfile , LockLocation + 0x16
.equ BufferStart , LockLocation + 0x1C
.equ Cr3Location , LockLocation + 0x20
-.equ InitFlag , LockLocation + 0x24
+.equ InitFlag , LockLocation + 0x24
.equ WakeUpApManner , LockLocation + 0x28
.equ BistBuffer , LockLocation + 0x2C
@@ -59,7 +59,7 @@ TryGetLock: PAUSE32
- jmp TryGetLock
+ jmp TryGetLock
LockObtained:
popal
@@ -83,7 +83,7 @@ ASM_PFX(AsmReleaseMPLock): #AsmReleaseMPLock ENDP
#-------------------------------------------------------------------------------
-# AsmGetGdtrIdtr (&Gdt, &Idt)#
+# AsmGetGdtrIdtr (&Gdt, &Idt)#
#-------------------------------------------------------------------------------------
ASM_GLOBAL ASM_PFX(AsmGetGdtrIdtr)
ASM_PFX(AsmGetGdtrIdtr):
@@ -98,7 +98,7 @@ ASM_PFX(AsmGetGdtrIdtr): leal IdtDesc, %esi
movl 0x28(%ebp), %edi
movl %esi, (%edi)
-
+
popal
ret
#AsmGetGdtrIdtr ENDP
@@ -109,6 +109,6 @@ GdtDesc: # GDT descriptor .word 0x0 # filled using sgdt
IdtDesc: # IDT descriptor
- .word 0x0 # IDT limit
+ .word 0x0 # IDT limit
.word 0x0 # IDT base and limit will be
.word 0x0 # filled using sidt
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpCpu.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpCpu.c index 133e10c57b..b6e3ed8f8e 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpCpu.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpCpu.c @@ -88,3 +88,4 @@ InitializeMpSupport ( return EFI_SUCCESS;
}
+
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpProc.asm b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpProc.asm index e07056d304..e9d6128461 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpProc.asm +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpProc.asm @@ -15,7 +15,7 @@ page ,132
title MP ASSEMBLY HOOKS
.686p
-.model flat
+.model flat
.data
.stack
.code
@@ -45,13 +45,13 @@ _MpMtrrSynchUpEntry PROC NEAR PUBLIC ;
mov eax, cr3
mov cr3, eax
-
+
mov eax, edx
ret
-
+
_MpMtrrSynchUpEntry ENDP
-
+
_MpMtrrSynchUpExit PROC NEAR PUBLIC
push ebp ; C prolog
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpProc.s b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpProc.s index 73ebd1cf2e..797ea9be6d 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpProc.s +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/MpProc.s @@ -38,7 +38,7 @@ ASM_PFX(MpMtrrSynchUpEntry): #
movl %cr3, %eax
movl %eax, %cr3
-
+
movl %edx, %eax
ret
#MpMtrrSynchUpEntry ENDP
@@ -63,7 +63,7 @@ ASM_PFX(MpMtrrSynchUpExit): #
movl 8(%ebp), %eax
movl %eax, %cr4
-
+
pop %ebp
ret
#MpMtrrSynchUpExit ENDP
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/ProcessorDef.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/ProcessorDef.h index c150ba60b7..174f9e2312 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/ProcessorDef.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Ia32/ProcessorDef.h @@ -19,7 +19,7 @@ #pragma pack(1)
/**
- @todo No structure description
+ @todo No structure description
**/
typedef struct {
@@ -32,7 +32,7 @@ typedef struct { #pragma pack()
/**
- @todo No structure description
+ @todo No structure description
**/
@@ -54,3 +54,4 @@ AsmGetAddressMap ( );
#endif
+
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MemoryAttribute.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MemoryAttribute.c index ddf4f56536..2dd763c065 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MemoryAttribute.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MemoryAttribute.c @@ -39,7 +39,7 @@ extern UINT64 mValidMtrrBitsMask; /**
@todo Add function description
- @retval @todo add return values
+ @retval @todo add return values
**/
VOID
@@ -61,7 +61,7 @@ PreMtrrChange ( /**
@todo Add function description
- @retval @todo add return values
+ @retval @todo add return values
**/
VOID
@@ -973,3 +973,4 @@ SetGcdMemorySpaceAttributes ( return EFI_SUCCESS;
}
+
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MemoryAttribute.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MemoryAttribute.h index eb70d66252..b20546b890 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MemoryAttribute.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MemoryAttribute.h @@ -18,7 +18,7 @@ extern UINT32 mUsedMtrr;
/**
- @todo add description
+ @todo add description
**/
typedef struct {
@@ -27,7 +27,7 @@ typedef struct { UINT32 Length;
} EFI_FIXED_MTRR;
/**
- @todo add description
+ @todo add description
**/
typedef struct {
@@ -134,3 +134,4 @@ SetGcdMemorySpaceAttributes ( IN UINT64 Attributes
);
#endif
+
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Microcode.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Microcode.c index 61b7227a4e..1e09c6eee1 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Microcode.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/Microcode.c @@ -23,7 +23,7 @@ EFI_CPU_MICROCODE_HEADER **mMicrocodePointerBuffer; BOOLEAN mVerifyMicrocodeChecksum = TRUE;
//
-// Function declaration
+// Function declaration
//
EFI_STATUS
FindLoadMicrocode (
@@ -481,3 +481,4 @@ CheckMicrocodeUpdate ( DataSize
);
}
+
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MiscFuncs.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MiscFuncs.c index 975907fa39..5490f55454 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MiscFuncs.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MiscFuncs.c @@ -20,7 +20,7 @@ extern MP_SYSTEM_DATA *mMPSystemData;
/**
- @todo add description
+ @todo add description
**/
VOID
@@ -50,7 +50,7 @@ EfiWriteToScript ( }
/**
- @todo add description
+ @todo add description
**/
VOID
@@ -87,7 +87,7 @@ CpuMiscEnable ( }
/**
- @todo add description
+ @todo add description
**/
VOID
@@ -101,3 +101,4 @@ ProgramProcessorFuncs ( CpuMiscEnable (MPSystemData->MonitorMwaitEnable, B_EFI_MSR_IA32_MISC_ENABLE_MONITOR);
}
+
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MiscFuncs.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MiscFuncs.h index c64c2d1dcc..c2ab1b5e96 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MiscFuncs.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MiscFuncs.h @@ -43,3 +43,4 @@ CpuMiscEnable ( );
#endif
+
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpCommon.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpCommon.c index ad98d91a56..7a9c12f631 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpCommon.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpCommon.c @@ -30,7 +30,7 @@ EFI_GUID mSmramCpuNvsHeaderGuid = EFI_SMRAM_CPU_NVS_HEADER_GUID; CHAR16 EfiPlatformCpuInfoVariable[] = L"PlatformCpuInfo";
/**
- @todo add description
+ @todo add description
**/
BOOLEAN
@@ -454,7 +454,7 @@ int _outp( #endif
/**
- @todo add description
+ @todo add description
**/
VOID
@@ -877,3 +877,4 @@ ResetAPs ( )
{
}
+
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpCommon.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpCommon.h index 33840aa76e..7327a3653d 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpCommon.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpCommon.h @@ -53,7 +53,7 @@ #define SIZE_OF_MCE_HANDLER 16
/**
- @todo add description
+ @todo add description
**/
typedef struct {
@@ -67,7 +67,7 @@ typedef struct { #pragma pack()
/**
- @todo add description
+ @todo add description
**/
typedef struct {
@@ -83,7 +83,7 @@ typedef enum { } WAKEUP_AP_MANNER;
/**
- @todo add description
+ @todo add description
**/
typedef struct {
@@ -423,3 +423,4 @@ LegacyRegionAPCount ( );
#endif
+
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpCpu.inf b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpCpu.inf index dfade3f5c5..3025a459af 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpCpu.inf +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpCpu.inf @@ -96,7 +96,7 @@ [Packages]
MdePkg/MdePkg.dec
IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
- BraswellPlatformPkg/BraswellPlatformPkg.dec
+ BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/IntelSiliconBasic.dec
[LibraryClasses]
BaseMemoryLib
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpService.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpService.c index 5157e766ae..6d12d8ea65 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpService.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MpService.c @@ -975,11 +975,11 @@ PollForInitialization ( }
/**
- @todo Add function description
+ @todo Add function description
- @param[in] Location @todo Add argument description
+ @param[in] Location @todo Add argument description
- @retval EFI_SUCCESS @todo Add argument description
+ @retval EFI_SUCCESS @todo Add argument description
**/
EFI_STATUS
@@ -1779,3 +1779,4 @@ LegacyRegionAPCount ( AsmReleaseMPLock (&mMPSystemData->APSerializeLock);
}
+
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MtrrSync.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MtrrSync.c index daf3f5dc60..7c0a357d72 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MtrrSync.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/MtrrSync.c @@ -184,7 +184,7 @@ MpMtrrSynchUp ( }
/**
- @todo add description
+ @todo add description
**/
VOID
@@ -231,3 +231,4 @@ SaveBspMtrrForS3 ( ASSERT (TableIndex < MAX_CPU_S3_MTRR_ENTRY);
}
+
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/PlatformMpService.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/PlatformMpService.h index aaac6ceb8a..29ba5686dc 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/PlatformMpService.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/PlatformMpService.h @@ -20,7 +20,7 @@ #include "MpCommon.h"
/**
- @todo add description
+ @todo add description
**/
typedef struct {
@@ -54,7 +54,7 @@ typedef struct { #define MSR_L3_CACHE_DISABLE 0x40
/**
- @todo add description
+ @todo add description
**/
typedef struct {
@@ -88,7 +88,7 @@ typedef enum { #define MAX_FEATURE_NUM 6
/**
- @todo add description
+ @todo add description
**/
typedef struct {
@@ -127,7 +127,7 @@ typedef struct { } CPU_DATA_BLOCK;
/**
- @todo add description
+ @todo add description
**/
typedef struct {
@@ -137,7 +137,7 @@ typedef struct { } MP_CPU_S3_SCRIPT_DATA;
/**
- @todo add description
+ @todo add description
**/
typedef struct {
@@ -147,7 +147,7 @@ typedef struct { } MP_CPU_S3_DATA_POINTER;
/**
- @todo add description
+ @todo add description
**/
#pragma pack (1)
@@ -238,7 +238,7 @@ typedef struct { #pragma pack (1)
/**
- @todo add description
+ @todo add description
**/
typedef struct {
@@ -252,7 +252,7 @@ typedef struct { #define CPU_MP_SERVICE_PRIVATE_SIGNATURE EFI_SIGNATURE_32 ('m', 'p', '3', '2')
/**
- @todo add description
+ @todo add description
**/
typedef struct {
@@ -634,3 +634,4 @@ GetCoreNumber ( );
#endif
+
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/Cpu.asm b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/Cpu.asm index c621e28bfb..b19f5f7f0f 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/Cpu.asm +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/Cpu.asm @@ -114,7 +114,7 @@ CpuSwitchStacks PROC PUBLIC call rcx ; rcx = EntryPoint
;
; no ret as we have a new stack and we jumped to the new location
- ;
+ ;
CpuSwitchStacks ENDP
;------------------------------------------------------------------------------
@@ -122,7 +122,7 @@ CpuSwitchStacks ENDP ; CpuSwitchStacks2Args (
; IN UINTN EntryPoint, // rcx
; IN UINTN Parameter1, // rdx
-; IN UINTN Parameter2, // r8
+; IN UINTN Parameter2, // r8
; IN UINTN NewStack, // r9
; IN UINTN Bsp // Only used on IPF
; );
@@ -130,14 +130,14 @@ CpuSwitchStacks ENDP ; BSP not used on IA-32
;
;------------------------------------------------------------------------------
-CpuSwitchStacks2Args PROC PUBLIC
+CpuSwitchStacks2Args PROC PUBLIC
mov rsp, r8 ; rsp = NewStack
push r8 ; Parameter2
push rdx ; Parameter1
call rcx ; rcx = EntryPoint
;
; no ret as we have a new stack and we jumped to the new location
- ;
+ ;
CpuSwitchStacks2Args ENDP
@@ -147,7 +147,7 @@ CpuSwitchStacks2Args PROC PUBLIC ; VOID
; );
;------------------------------------------------------------------------------
-CpuCodeSegment PROC PUBLIC
+CpuCodeSegment PROC PUBLIC
xor eax, eax
mov eax, cs
ret
@@ -178,9 +178,9 @@ CpuLoadGlobalDescriptorTable PROC PUBLIC CpuLoadGlobalDescriptorTable ENDP
CpuInitSelectors PROC PUBLIC
- int 68h
- ret
-CpuInitSelectors ENDP
+ int 68h
+ ret
+CpuInitSelectors ENDP
;------------------------------------------------------------------------------
; VOID
; CpuLoadInterruptDescriptorTable (
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/CpuAsm.asm b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/CpuAsm.asm index 1082001fc4..7318565e5e 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/CpuAsm.asm +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/CpuAsm.asm @@ -1,4 +1,4 @@ -;; @file
+;; @file
; Assembly code of the implementation of X64 CPU architectural protocol
;
; Copyright (c) 2005 - 2015, Intel Corporation. All rights reserved.<BR>
@@ -74,7 +74,7 @@ ENDM ; +---------------------+ <-- RBP, 16-byte aligned
;
-CommonInterruptEntry PROC PUBLIC
+CommonInterruptEntry PROC PUBLIC
cli
;
; All interrupt handlers are invoked through interrupt gates, so
@@ -97,7 +97,7 @@ NoErrorCode: ;
push [rsp]
mov qword ptr [rsp + 8], 0
-@@:
+@@:
push rbp
mov rbp, rsp
@@ -337,18 +337,18 @@ in_long_mode:: mov rsp, rbx ; On a new stack now
mov rcx, [rbp+10h] ; Pass Hob Start in RCX
- mov rax, [rbp+20h] ; Get the function pointer for
+ mov rax, [rbp+20h] ; Get the function pointer for
; PpisNeededByDxeIplEntryPoint into EAX
call fword ptr [rax] ; Make the call into PpisNeededByDxeIplEntryPoint
mov ecx, [rbp+10h] ; Pass Hob Start in RCX
- mov eax, [rbp+28h] ; Get the function pointer for
+ mov eax, [rbp+28h] ; Get the function pointer for
; DxeCoreEntryPoint into EAX
call fword ptr [rax] ; Make the call into Dxe Core
call CommonInterruptEntry
- mov rdi, CommonInterruptEntry
+ mov rdi, CommonInterruptEntry
lgdt fword ptr [rdi]
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/Exception.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/Exception.c index 4e4d4ed1c0..6f1b3bcf08 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/Exception.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/Exception.c @@ -24,7 +24,7 @@ VOID IN VOID *SystemContext
);
/**
- @todo No structure description
+ @todo No structure description
**/
typedef struct {
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/MemoryOperation.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/MemoryOperation.c index 83bfa8bf05..8dc8f6f061 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/MemoryOperation.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/MemoryOperation.c @@ -49,7 +49,7 @@ UINT64 mValidMtrrBitsMask; #pragma pack (1)
/**
- @todo add description
+ @todo add description
**/
typedef struct {
@@ -62,7 +62,7 @@ typedef struct { } SEGMENT_DESCRIPTOR_x64;
/**
- @todo Add description
+ @todo Add description
**/
@@ -161,7 +161,7 @@ ALINE_16BYTE_BOUNDRY PSEUDO_DESCRIPTOR_x64 gLidtPseudoDescriptor = { };
/**
- @todo add function description
+ @todo add function description
**/
VOID
@@ -210,7 +210,7 @@ InitializeInterruptTables ( }
/**
- @todo add function description
+ @todo add function description
**/
VOID
@@ -288,7 +288,7 @@ InitailizeMemoryAttributes ( }
/**
- @todo add function description
+ @todo add function description
**/
VOID *
@@ -312,7 +312,7 @@ AllocateZeroedPage ( @param[in] PageAddress
@param[in] **PageDirectoryToConvert
- @todo review parameters and description
+ @todo review parameters and description
**/
VOID
@@ -367,13 +367,13 @@ Convert2MBPageTo4KPages ( }
/**
- @todo Add description to function
+ @todo Add description to function
- @param[in] BaseAddress @todo Add parameter description
- @param[out] PageTable @todo Add parameter description
- @param[out] Page2MBytes @todo Add parameter description
+ @param[in] BaseAddress @todo Add parameter description
+ @param[out] PageTable @todo Add parameter description
+ @param[out] Page2MBytes @todo Add parameter description
- @retval @todo Add return value description
+ @retval @todo Add return value description
**/
EFI_STATUS
@@ -525,7 +525,7 @@ PrepareMemoryForAPs ( @param[in] ApFunction Address of function assigned to AP.
@param[in] WakeUpBuffer Pointer to the address of wakeup buffer.
- @retval EFI_SUCCESS Exchange Info successfully prepared for APs.
+ @retval EFI_SUCCESS Exchange Info successfully prepared for APs.
**/
EFI_STATUS
@@ -716,3 +716,4 @@ PrepareGdtIdtForAP ( return EFI_SUCCESS;
}
+
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/MpCpu.c b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/MpCpu.c index 7ef2f43ba1..d2eb96df49 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/MpCpu.c +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/MpCpu.c @@ -74,3 +74,4 @@ InitializeMpSupport ( return EFI_SUCCESS;
}
+
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/MpFuncs.asm b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/MpFuncs.asm index 9970dfba48..6a843e2a4e 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/MpFuncs.asm +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/MpFuncs.asm @@ -13,7 +13,7 @@ ;
;;
-include Htequ.inc
+include Htequ.inc
;-------------------------------------------------------------------------------------
;-------------------------------------------------------------------------------------
@@ -36,7 +36,7 @@ RendezvousFunnelProcStart:: db 8ch, 0c8h ; mov ax, cs
db 8eh, 0d8h ; mov ds, ax
db 8eh, 0c0h ; mov es, ax
- db 8eh, 0d0h ; mov ss, ax
+ db 8eh, 0d0h ; mov ss, ax
db 33h, 0c0h ; xor ax, ax
db 8eh, 0e0h ; mov fs, ax
db 8eh, 0e8h ; mov gs, ax
@@ -60,7 +60,7 @@ RendezvousFunnelProcStart:: db flat32Start - ($ + 1) ; jz flat32Start
; Record BIST information
-;
+;
db 0B0h, 08h ; mov al, 8
db 0F6h, 0E3h ; mul bl
@@ -70,7 +70,7 @@ RendezvousFunnelProcStart:: db 66h, 0C7h, 04h
dd 00000001h ; mov dword ptr [si], 1 ; Set Valid Flag
- db 66h, 89h, 6Ch, 04h ; mov dword ptr [si + 4], ebp ; Store BIST value
+ db 66h, 89h, 6Ch, 04h ; mov dword ptr [si + 4], ebp ; Store BIST value
cli
hlt
@@ -101,7 +101,7 @@ flat32Start:: db 0BFh ; opcode of mov di, imm16
dw LongModeStartJump - RendezvousFunnelProcStart ; Get offset of LongModeStartJump
- db 66h, 8Bh, 3Dh ; mov edi,dword ptr [di] ; EDI is keeping the LongModeStart Jump Address
+ db 66h, 8Bh, 3Dh ; mov edi,dword ptr [di] ; EDI is keeping the LongModeStart Jump Address
db 31h, 0C0h ; xor ax, ax
db 8Eh, 0D8h ; mov ds, ax
@@ -179,7 +179,7 @@ LongModeStart:: add edx, RunLoopAndMwaitLoop64Jump - LongModeStart
mov dword ptr [rdx], eax
-;
+;
; ProgramStack
;
xor rcx, rcx
@@ -306,7 +306,7 @@ RunLoopAndMwaitLoop32:: db 66h, 0B8h, 18h, 00h ; mov ax, 18h
db 66h, 8Eh, 0D8h ; mov ds, ax
- db 8eh, 0d0h ; mov ss, ax
+ db 8eh, 0d0h ; mov ss, ax
db 0Fh, 20h, 0C0h ; mov eax, cr0 ; Read CR0.
db 0Fh, 0BAh, 0F0h, 1Fh ; btr eax, 31 ; Reset PG=0.
@@ -387,9 +387,9 @@ AsmGetAddressMap PROC PUBLIC mov qword ptr [rcx+18h], LongModeStart - RendezvousFunnelProcStart
mov qword ptr [rcx+20h], LONG_JUMP - RendezvousFunnelProcStart
mov qword ptr [rcx+28h], RendezvousFunnelProcEnd - RendezvousFunnelProcStart
-
+
ret
-
+
AsmGetAddressMap ENDP
AsmGetGdtrIdtr PROC PUBLIC
@@ -401,16 +401,16 @@ AsmGetGdtrIdtr PROC PUBLIC sidt IdtDesc
lea rax, IdtDesc
mov [rdx], rax
-
+
ret
-
+
AsmGetGdtrIdtr ENDP
AsmGetCr3 PROC PUBLIC
-
+
mov rax, cr3
ret
-
+
AsmGetCr3 ENDP
@@ -423,24 +423,24 @@ TryGetLock: jz LockObtained
pause
- jmp TryGetLock
+ jmp TryGetLock
LockObtained:
ret
-
+
AsmAcquireMPLock ENDP
AsmReleaseMPLock PROC PUBLIC
mov al, VacantFlag
xchg al, byte ptr [rcx]
-
+
ret
-
+
AsmReleaseMPLock ENDP
;-------------------------------------------------------------------------------------
-;AsmExchangeRole procedure follows. This procedure executed by current BSP, that is
+;AsmExchangeRole procedure follows. This procedure executed by current BSP, that is
;about to become an AP. It switches it'stack with the current AP.
;AsmExchangeRole (IN CPU_EXCHANGE_INFO *MyInfo, IN CPU_EXCHANGE_INFO *OthersInfo);
;-------------------------------------------------------------------------------------
@@ -470,10 +470,10 @@ AsmExchangeRole PROC PUBLIC mov rax, cr0
push rax
-
+
mov rax, cr4
push rax
-
+
; rsi contains MyInfo pointer
mov rsi, rcx
@@ -484,7 +484,7 @@ AsmExchangeRole PROC PUBLIC pushfq
sgdt fword ptr [rsi + 16]
sidt fword ptr [rsi + 26]
-
+
; Store the its StackPointer
mov qword ptr [rsi + 8], rsp
@@ -497,13 +497,13 @@ TryLock1: jz LockObtained1
pause
jmp TryLock1
-
+
LockObtained1:
mov byte ptr [rsi + 1], CPU_SWITCH_STATE_STORED
db 0f0h ; opcode for lock instruction
xchg al, byte ptr [rsi]
-WaitForOtherStored::
+WaitForOtherStored::
; wait until the other CPU finish storing its state
mov al, NotVacantFlag
TryLock2:
@@ -513,24 +513,24 @@ TryLock2: jz LockObtained2
PAUSE32
jmp TryLock2
-
+
LockObtained2:
mov bl, byte ptr [rdi + 1]
db 0f0h ; opcode for lock instruction
xchg al, byte ptr [rdi]
cmp bl, CPU_SWITCH_STATE_STORED
jb WaitForOtherStored
-
+
; Since another CPU already stored its state, load them
; load GDTR value
lgdt fword ptr [rdi + 16]
-
+
; load IDTR value
lidt fword ptr [rdi + 26]
; load its future StackPointer
mov rsp, qword ptr [rdi + 8]
-
+
; update its switch state to LOADED
mov al, NotVacantFlag
TryLock3:
@@ -540,7 +540,7 @@ TryLock3: jz LockObtained3
PAUSE32
jmp TryLock3
-
+
LockObtained3:
mov byte ptr [rsi+1], CPU_SWITCH_STATE_LOADED
db 0f0h ; opcode for lock instruction
@@ -557,7 +557,7 @@ TryLock4: jz LockObtained4
PAUSE32
jmp TryLock4
-
+
LockObtained4:
mov bl, byte ptr [rdi+1]
db 0f0h ; opcode for lock instruction
@@ -570,10 +570,10 @@ LockObtained4: pop rax
mov cr4, rax
-
+
pop rax
mov cr0, rax
-
+
pop r15
pop r14
pop r13
@@ -595,7 +595,7 @@ AsmExchangeRole ENDP GdtDesc QWORD 0
WORD 0
-
+
IdtDesc QWORD 0
WORD 0
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/PlatformCpuLib.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/PlatformCpuLib.h index 33fc064199..1c9e17ffab 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/PlatformCpuLib.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/PlatformCpuLib.h @@ -133,3 +133,4 @@ CpuLoadInterruptDescriptorTable ( );
#endif
+
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/ProcessorDef.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/ProcessorDef.h index 328a12fdd0..d6612296c3 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/ProcessorDef.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/ProcessorDef.h @@ -18,7 +18,7 @@ #pragma pack(1)
/**
- @todo @todo add structure description
+ @todo @todo add structure description
**/
typedef struct {
@@ -32,7 +32,7 @@ typedef struct { #pragma pack()
/**
- @todo @todo add structure description
+ @todo @todo add structure description
**/
typedef struct {
@@ -55,3 +55,4 @@ AsmGetAddressMap ( );
#endif
+
diff --git a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/VirtualMemory.h b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/VirtualMemory.h index e8ef0afc82..1ff5861300 100644 --- a/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/VirtualMemory.h +++ b/BraswellPlatformPkg/Common/Silicon/IntelSiliconBasic/CpuInit/x64/VirtualMemory.h @@ -118,7 +118,7 @@ typedef union { UINT64 Uint64;
} x64_PAGE_TABLE_ENTRY_2M;
/**
- @todo Add union description
+ @todo Add union description
**/
typedef union {
@@ -132,7 +132,7 @@ typedef union { UINT64 Reserved:57;
} x64_PAGE_TABLE_ENTRY_COMMON;
/**
- @todo Add union description
+ @todo Add union description
**/
typedef union {
@@ -145,3 +145,4 @@ typedef union { #pragma pack()
#endif
+
|