1 files changed, 192 insertions, 0 deletions
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/IncludePrivate/Library/CpuCommonLib.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/IncludePrivate/Library/CpuCommonLib.h
new file mode 100644
index 0000000000..8099236d88
--- /dev/null
+++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/IncludePrivate/Library/CpuCommonLib.h
@@ -0,0 +1,192 @@
+/** @file
+  Header file for Cpu Common Lib implementation.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CPU_COMMON_LIB_H_
+#define _CPU_COMMON_LIB_H_
+
+typedef UINT32 CPU_RESET_TYPE;
+
+#define NO_RESET                              0
+#define WARM_RESET                            BIT0
+#define COLD_RESET                            (BIT0 | BIT1)
+
+
+/**
+  Set up flags in CR4 for XMM instruction enabling
+**/
+VOID
+EFIAPI
+XmmInit (
+  VOID
+  );
+
+/**
+  Enable "Machine Check Enable"
+**/
+VOID
+EFIAPI
+EnableMce (
+  VOID
+  );
+
+/**
+  Mtrr Synch Up Entry
+**/
+UINTN
+EFIAPI
+MpMtrrSynchUpEntry (
+  VOID
+  );
+
+/**
+  Mtrr Synch Up Exit
+**/
+VOID
+EFIAPI
+MpMtrrSynchUpExit (
+  UINTN Cr4
+  );
+
+/**
+  This procedure sends an IPI to the designated processor in
+  the requested delivery mode with the requested vector.
+
+  @param[in] ApicID          - APIC ID of processor.
+  @param[in] VectorNumber    - Vector number.
+  @param[in] DeliveryMode    - I/O APIC Interrupt Deliver Modes
+
+  @retval EFI_INVALID_PARAMETER - Input paramters were not correct.
+  @retval EFI_NOT_READY         - There was a pending interrupt
+  @retval EFI_SUCCESS           - Interrupt sent successfully
+**/
+EFI_STATUS
+EFIAPI
+CpuSendIpi (
+  IN UINT32            ApicID,
+  IN UINTN             VectorNumber,
+  IN UINTN             DeliveryMode
+  );
+
+
+/**
+  Get APIC ID of processor
+
+  @retval APIC ID of processor
+**/
+UINT32
+GetCpuApicId (
+  VOID
+  );
+
+/**
+  Programs XAPIC registers.
+
+  @param[in] Bsp             - Is this BSP?
+**/
+VOID
+ProgramXApic (
+  BOOLEAN Bsp
+  );
+
+/**
+  This function is to disable BIOS Write Protect in SMM phase.
+**/
+VOID
+EFIAPI
+CpuSmmDisableBiosWriteProtect (
+  VOID
+  );
+
+/**
+  This function is to enable BIOS Write Protect in SMM phase.
+**/
+VOID
+EFIAPI
+CpuSmmEnableBiosWriteProtect (
+  VOID
+  );
+
+/**
+  This function returns the maximum number of cores supported in this physical processor package.
+
+  @retval Maximum number of supported cores in the package.
+**/
+UINT8
+GetMaxSupportedCoreCount (
+  VOID
+  );
+
+/**
+  This function returns the actual factory-configured number of threads per core,
+  and actual factory-configured number of cores in this physical processor package.
+
+  @param[out] *ThreadsPerCore    - variable that will store Maximum enabled threads per core
+  @param[out] *NumberOfCores     - variable that will store Maximum enabled cores per die
+**/
+VOID
+GetSupportedCount (
+  OUT UINT16 *ThreadsPerCore,  OPTIONAL
+  OUT UINT16 *NumberOfCores    OPTIONAL
+  );
+
+
+/**
+  Check to see if the executing thread is BSP
+
+  @retval TRUE   Executing thread is BSP
+  @retval FALSE  Executing thread is AP
+**/
+BOOLEAN
+IsBsp (
+  VOID
+  );
+
+
+/**
+  Return TRUE if PRMRR base was already set on this core and was
+  locked
+
+  @retval TRUE  PRMRR base was already set
+  @retval FALSE PRMRR base wasn't set
+**/
+BOOLEAN
+IsPrmrrAlreadySet (
+  VOID
+  );
+
+/**
+  Check if this is non-core processor - HT AP thread
+
+  @retval TRUE if this is HT AP thread
+  @retval FALSE if this is core thread
+**/
+BOOLEAN
+IsSecondaryThread (
+  VOID
+  );
+
+
+/**
+  Based on ResetType, perform warm or cold reset using PCH reset PPI.
+
+  @param[in] ResetType    - CPU_RESET_TYPE to indicate which reset should be performed.
+
+  @retval EFI_SUCCESS     - Function successful (system should already reset).
+  @retval EFI_UNSUPPORTED - Reset type unsupported.
+**/
+EFI_STATUS
+PerformWarmOrColdReset (
+  IN CPU_RESET_TYPE ResetType
+  );
+#endif