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| author | Jose Marinho <jose.marinho@arm.com> | 2017-07-28 15:28:02 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-08-30 16:26:19 +0000 |
| commit | b277ad3bdb25e2fe7d53d470a57bf48edb6299df (patch) | |
| tree | 0f21f0f8e0c15f3d788c5c046aa772afa2e91312 | |
| parent | 653d2ee29a09be2f9cb3b8145ca1aecb363fbd8e (diff) | |
| download | gem5-b277ad3bdb25e2fe7d53d470a57bf48edb6299df.tar.xz | |
arch-arm: Only increment SW PMU counters on writes to PMSWINC
When writing a bitmask of counters to PMSWINC, the PMU currently
increments the corresponding counters regardless of what they are
configured to count. According to the ARM ARM (D5.10.4), counters
should only be updated if they have been configured to count
software events (event type 0).
Change-Id: I5b2bc1fae55faa342b863721c9838342442831a9
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4285
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
| -rw-r--r-- | src/arch/arm/pmu.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/arch/arm/pmu.cc b/src/arch/arm/pmu.cc index 14b1b50a0..f1ff6cbbc 100644 --- a/src/arch/arm/pmu.cc +++ b/src/arch/arm/pmu.cc @@ -147,8 +147,10 @@ PMU::setMiscReg(int misc_reg, MiscReg val) case MISCREG_PMSWINC: for (int i = 0; i < counters.size(); ++i) { CounterState &ctr(getCounter(i)); - if (ctr.enabled && (val & (1 << i))) + if (ctr.enabled && (val & (1 << i)) + && ctr.eventId == ARCH_EVENT_SW_INCR ) { ++ctr.value; + } } break; |