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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:06 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:06 -0500 |
| commit | 0aff168f1a3852150dc9520c294a60e8e5f917b9 (patch) | |
| tree | f6271277dcbbde5f45267c26e9593b9aa2b37c37 | |
| parent | 8ba812f1fbcf44b21fa7967380bfae0499dbfd35 (diff) | |
| download | gem5-0aff168f1a3852150dc9520c294a60e8e5f917b9.tar.xz | |
ARM: Decode the signed add/subtract and subtract/add instructions.
| -rw-r--r-- | src/arch/arm/isa/formats/data.isa | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa index 05d89abf5..cd902242e 100644 --- a/src/arch/arm/isa/formats/data.isa +++ b/src/arch/arm/isa/formats/data.isa @@ -236,9 +236,9 @@ def format ArmParallelAddSubtract() {{ case 0x0: return new Sadd16RegCc(machInst, rd, rn, rm, 0, LSL); case 0x1: - return new WarnUnimplemented("sasx", machInst); + return new SasxRegCc(machInst, rd, rn, rm, 0, LSL); case 0x2: - return new WarnUnimplemented("ssax", machInst); + return new SsaxRegCc(machInst, rd, rn, rm, 0, LSL); case 0x3: return new Ssub16RegCc(machInst, rd, rn, rm, 0, LSL); case 0x4: @@ -553,9 +553,11 @@ def format Thumb32DataProcReg() {{ return new Sadd16RegCc(machInst, rd, rn, rm, 0, LSL); case 0x2: - return new WarnUnimplemented("sasx", machInst); + return new SasxRegCc(machInst, rd, + rn, rm, 0, LSL); case 0x6: - return new WarnUnimplemented("ssax", machInst); + return new SsaxRegCc(machInst, rd, + rn, rm, 0, LSL); case 0x5: return new Ssub16RegCc(machInst, rd, rn, rm, 0, LSL); |