summaryrefslogtreecommitdiff
AgeCommit message (Expand)Author
2019-03-06remove static branch predictorinvisispec-1.0Iru Cai
2019-03-04remove unused src/mem/ruby/structures/SBE*Iru Cai
2019-02-28attack code and exp scriptIru Cai
2019-02-28invisispec-1.0 configsIru Cai
2019-02-28invisispec-1.0 sourceIru Cai
2018-02-20arch-arm: Make hlt64 a mem barrier with semihostingGiacomo Travaglini
2018-02-20arch-arm: Add AArch32 HLT Semihosting interfaceGiacomo Travaglini
2018-02-20arch-arm: Add AArch32 SVC Semihosting interfaceGiacomo Travaglini
2018-02-20arch-arm: Adding isa templates for semihosting opsGiacomo Travaglini
2018-02-20arch-arm: HLT using immediate when checking for semihostingGiacomo Travaglini
2018-02-20arch-arm: Fix Hlt64,Svc64,Hvc64,Smc64,Brk64 disassemblyGiacomo Travaglini
2018-02-20cpu-o3: Don't add non-speculative mem barriers to the IQ twiceAndreas Sandberg
2018-02-19mem: fix page_table bug for .fast buildBrandon Potter
2018-02-19arch-riscv: Fix compressed branch op offsetAlec Roelke
2018-02-19arch-arm: Semihosting not available in syscall emulationGiacomo Travaglini
2018-02-19arch-arm: Add support for secure state in semihostingAndreas Sandberg
2018-02-19mem: Refactor port proxies to support secure accessesAndreas Sandberg
2018-02-19arch-arm: Add aarch64 semihosting supportAndreas Sandberg
2018-02-16arch-arm: IMPLEMENTATION DEFINED registerGiacomo Travaglini
2018-02-16arch-arm: Arch regs and pseudo regs distinctionGiacomo Travaglini
2018-02-16arch-arm: Fix syntax error in TLB::getResultTeChuan Zhu
2018-02-16arch-arm: Fix big endian support in {Load,Store}Double64Chuan Zhu
2018-02-16arch-arm: Fix big endian support in do{Long,L1,L2}DescriptorChuan Zhu
2018-02-16arch-arm: Add support for automatic reset addr selectionAndreas Sandberg
2018-02-16arch-arm: Change ArmFault cast from reinterpret to staticGiacomo Travaglini
2018-02-16arch-arm: Decode Brk64 instructionsAndreas Sandberg
2018-02-16mem: Add PortProxy read/write helper with explicit endiannessAndreas Sandberg
2018-02-16sim: Add gtoh/htog helpers that take an explicit endiannessChuan Zhu
2018-02-16arch-arm: Fix Secure state check in checkFPAdvSIMDTrap64Chuan Zhu
2018-02-14mem, sim-se: Fixed seg-fault in EmulationPageTable::remapRico Amslinger
2018-02-13dev: Remove unused interrupt controller in TerminalAndreas Sandberg
2018-02-13sim: Make Stats truly non-copy-constructibleRekai Gonzalez-Alberquilla
2018-02-09Fix DDR4_2400_8x8 DRAMCTRL configurationWendy Elsasser
2018-02-09sim: Remove _numContexts member in System classGiacomo Travaglini
2018-02-09dev: Fix i8042 device errorsJason Lowe-Power
2018-02-08mem-cache: Make cache warmup percentage a parameter.Daniel R. Carvalho
2018-02-08arch-arm: Correct SecureMonitorTrap vals for aarch32Giacomo Travaglini
2018-02-08arch-arm: Fixed error in choosing vector offsetChuan Zhu
2018-02-08arch-arm: Don't change PSTATE in Illegal Exception returnGiacomo Travaglini
2018-02-08arch-arm: Handle route to EL2 in Supervisor TrapChuan Zhu
2018-02-07arch-arm: Change the type of fault for dc ivac instructionsNikos Nikoleris
2018-02-07arch-arm: Unify permission checks for dc * instructionsNikos Nikoleris
2018-02-07arch-arm: Check cache maintenance insts for permission faultsNikos Nikoleris
2018-02-07arch-arm: Turn dc ivac to dc civac when some conditions are metNikos Nikoleris
2018-02-07arch-arm: Fix printing of the data cache maintenance instructionsNikos Nikoleris
2018-02-07arch-arm: Fix cache line size for cache maintenace instNikos Nikoleris
2018-02-07arch-arm: Fault when dc ivac is executed from EL0Nikos Nikoleris
2018-02-07mem-cache: Only pendingModified MSHRs can satisfy CMO snoopsNikos Nikoleris
2018-02-07mem-cache: Cleaned blocks should be marked as not writableNikos Nikoleris
2018-02-07arch-arm: Change function name for banked miscregsGiacomo Travaglini
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-03 18:00:17 +0000