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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:01 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:01 -0500 |
| commit | 386424ccb59ffdabcb4ce9d363903741e329ebcb (patch) | |
| tree | 20986eb78a6e315ce48d10dfc4fd488756d92aa2 | |
| parent | 292b8a3c9169fcf587dd81fb8072e7d451e16afe (diff) | |
| download | gem5-386424ccb59ffdabcb4ce9d363903741e329ebcb.tar.xz | |
ARM: Implement the 32 bit thumb load word instructions.
| -rw-r--r-- | src/arch/arm/isa/thumbdecode.isa | 48 |
1 files changed, 42 insertions, 6 deletions
diff --git a/src/arch/arm/isa/thumbdecode.isa b/src/arch/arm/isa/thumbdecode.isa index 3d8e56a48..9bf596b88 100644 --- a/src/arch/arm/isa/thumbdecode.isa +++ b/src/arch/arm/isa/thumbdecode.isa @@ -396,17 +396,53 @@ 0x1: WarnUnimpl::Load_halfword_memory_hints(); 0x2: decode HTOPCODE_8 { 0x0: decode HTRN { - 0xf: WarnUnimpl::ldr(); // literal A8-122 + 0xf: ArmLoadMemory::ldr1( + {{ Rd.uw = Mem.uw }}, + {{ EA = roundUp(PC, 4) + + (UP ? IMMED_11_0 : -IMMED_11_0); }}); default: decode HTOPCODE_7 { 0x0: decode LTOPCODE_11_8 { 0x0: decode LTOPCODE_7_6 { - 0x0: WarnUnimpl::ldr(); // register A8-122 + 0x0: ArmLoadMemory::ldr2( + {{ Rd = Mem; }}, + {{ EA = Rn + + (Rm << + bits(machInst, 5, 4)); }} + ); } - 0x9, 0xb, 0xc, 0xd, 0xf: - WarnUnimpl::ldr(); // immediate thumb A8-118 - 0xe: WarnUnimpl::ldrt(); // A8-176 + 0x9: ArmLoadMemory::ldr3( + {{ Rd = Mem; + Rn = Rn - IMMED_11_0; }}, + {{ EA = Rn; }} + ); + 0xb: ArmLoadMemory::ldr4( + {{ Rd = Mem; + Rn = Rn + IMMED_11_0; }}, + {{ EA = Rn; }} + ); + 0xc: ArmLoadMemory::ldr5( + {{ Rd = Mem; }}, + {{ EA = Rn - IMMED_11_0; }} + ); + 0xd: ArmLoadMemory::ldr6( + {{ Rd = Mem; + Rn = Rn - IMMED_11_0; }}, + {{ EA = Rn - IMMED_11_0; }} + ); + 0xf: ArmLoadMemory::ldr7( + {{ Rd = Mem; + Rn = Rn + IMMED_11_0; }}, + {{ EA = Rn + IMMED_11_0; }} + ); + 0xe: ArmLoadMemory::ldrt( + {{ Rd = Mem; }}, + {{ EA = Rn + IMMED_11_0; }} + ); // This should force user level access } - 0x1: WarnUnimpl::ldr(); // immediate thumb A8-118 + 0x1: ArmLoadMemory::ldr8( + {{ Rd = Mem; }}, + {{ EA = Rn + IMMED_11_0; }} + ); } } } |