Minor code cleanup of BaseDynInst.

src/cpu/base_dyn_inst.cc:
src/cpu/base_dyn_inst.hh:
    Minor code cleanup by putting several bools into a bitset instead.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rob_impl.hh:
    Changed around some things in BaseDynInst.

--HG--
extra : convert_revision : 1db363d69a863cc8744cc9f9ec542ade8472eb42

10 files changed, 102 insertions, 159 deletions

diff --git a/src/cpu/base_dyn_inst.cc b/src/cpu/base_dyn_inst.cc
index e3829297d..4bcd59848 100644
--- a/src/cpu/base_dyn_inst.cc
+++ b/src/cpu/base_dyn_inst.cc
@@ -99,39 +99,18 @@ BaseDynInst<Impl>::initVars()
     memData = NULL;
     effAddr = 0;
     physEffAddr = 0;
-    storeSize = 0;
 
     readyRegs = 0;
 
     instResult.integer = 0;
 
-    // May want to turn this into a bit vector or something.
-    completed = false;
-    resultReady = false;
-    canIssue = false;
-    issued = false;
-    executed = false;
-    canCommit = false;
-    committed = false;
-    squashed = false;
-    squashedInIQ = false;
-    squashedInLSQ = false;
-    squashedInROB = false;
+    status.reset();
+
     eaCalcDone = false;
     memOpDone = false;
+
     lqIdx = -1;
     sqIdx = -1;
-    reachedCommit = false;
-
-    blockingInst = false;
-    recoverInst = false;
-
-    iqEntry = false;
-    robEntry = false;
-
-    serializeBefore = false;
-    serializeAfter = false;
-    serializeHandled = false;
 
     // Eventually make this a parameter.
     threadNumber = 0;
@@ -294,7 +273,7 @@ void
 BaseDynInst<Impl>::markSrcRegReady()
 {
     if (++readyRegs == numSrcRegs()) {
-        canIssue = true;
+        status.set(CanIssue);
     }
 }
 
@@ -302,13 +281,9 @@ template <class Impl>
 void
 BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
 {
-    ++readyRegs;
-
     _readySrcRegIdx[src_idx] = true;
 
-    if (readyRegs == numSrcRegs()) {
-        canIssue = true;
-    }
+    markSrcRegReady();
 }
 
 template <class Impl>
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index fc9bf8b94..f188e661c 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -31,6 +31,7 @@
 #ifndef __CPU_BASE_DYN_INST_HH__
 #define __CPU_BASE_DYN_INST_HH__
 
+#include <bitset>
 #include <list>
 #include <string>
 
@@ -126,56 +127,34 @@ class BaseDynInst : public FastAlloc, public RefCounted
     /** The sequence number of the instruction. */
     InstSeqNum seqNum;
 
-    /** Is the instruction in the IQ */
-    bool iqEntry;
-
-    /** Is the instruction in the ROB */
-    bool robEntry;
-
-    /** Is the instruction in the LSQ */
-    bool lsqEntry;
-
-    /** Is the instruction completed. */
-    bool completed;
-
-    /** Is the instruction's result ready. */
-    bool resultReady;
-
-    /** Can this instruction issue. */
-    bool canIssue;
-
-    /** Has this instruction issued. */
-    bool issued;
-
-    /** Has this instruction executed (or made it through execute) yet. */
-    bool executed;
-
-    /** Can this instruction commit. */
-    bool canCommit;
-
-    /** Is this instruction committed. */
-    bool committed;
-
-    /** Is this instruction squashed. */
-    bool squashed;
-
-    /** Is this instruction squashed in the instruction queue. */
-    bool squashedInIQ;
-
-    /** Is this instruction squashed in the instruction queue. */
-    bool squashedInLSQ;
-
-    /** Is this instruction squashed in the instruction queue. */
-    bool squashedInROB;
-
-    /** Is this a recover instruction. */
-    bool recoverInst;
-
-    /** Is this a thread blocking instruction. */
-    bool blockingInst;	/* this inst has called thread_block() */
+    enum Status {
+        IqEntry,                 /// Instruction is in the IQ
+        RobEntry,                /// Instruction is in the ROB
+        LsqEntry,                /// Instruction is in the LSQ
+        Completed,               /// Instruction has completed
+        ResultReady,             /// Instruction has its result
+        CanIssue,                /// Instruction can issue and execute
+        Issued,                  /// Instruction has issued
+        Executed,                /// Instruction has executed
+        CanCommit,               /// Instruction can commit
+        AtCommit,                /// Instruction has reached commit
+        Committed,               /// Instruction has committed
+        Squashed,                /// Instruction is squashed
+        SquashedInIQ,            /// Instruction is squashed in the IQ
+        SquashedInLSQ,           /// Instruction is squashed in the LSQ
+        SquashedInROB,           /// Instruction is squashed in the ROB
+        RecoverInst,             /// Is a recover instruction
+        BlockingInst,            /// Is a blocking instruction
+        ThreadsyncWait,          /// Is a thread synchronization instruction
+        SerializeBefore,         /// Needs to serialize on
+                                 /// instructions ahead of it
+        SerializeAfter,          /// Needs to serialize instructions behind it
+        SerializeHandled,        /// Serialization has been handled
+        NumStatus
+    };
 
-    /** Is this a thread syncrhonization instruction. */
-    bool threadsyncWait;
+    /** The status of this BaseDynInst.  Several bits can be set. */
+    std::bitset<NumStatus> status;
 
     /** The thread this instruction is from. */
     short threadNumber;
@@ -216,12 +195,6 @@ class BaseDynInst : public FastAlloc, public RefCounted
     /** The memory request flags (from translation). */
     unsigned memReqFlags;
 
-    /** The size of the data to be stored. */
-    int storeSize;
-
-    /** The data to be stored. */
-    IntReg storeData;
-
     union Result {
         uint64_t integer;
         float fp;
@@ -338,9 +311,9 @@ class BaseDynInst : public FastAlloc, public RefCounted
     bool isThreadSync()   const { return staticInst->isThreadSync(); }
     bool isSerializing()  const { return staticInst->isSerializing(); }
     bool isSerializeBefore() const
-    { return staticInst->isSerializeBefore() || serializeBefore; }
+    { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
     bool isSerializeAfter() const
-    { return staticInst->isSerializeAfter() || serializeAfter; }
+    { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
     bool isMemBarrier()   const { return staticInst->isMemBarrier(); }
     bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
     bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
@@ -349,41 +322,32 @@ class BaseDynInst : public FastAlloc, public RefCounted
     bool isUnverifiable() const { return staticInst->isUnverifiable(); }
 
     /** Temporarily sets this instruction as a serialize before instruction. */
-    void setSerializeBefore() { serializeBefore = true; }
+    void setSerializeBefore() { status.set(SerializeBefore); }
 
     /** Clears the serializeBefore part of this instruction. */
-    void clearSerializeBefore() { serializeBefore = false; }
+    void clearSerializeBefore() { status.reset(SerializeBefore); }
 
     /** Checks if this serializeBefore is only temporarily set. */
-    bool isTempSerializeBefore() { return serializeBefore; }
-
-    /** Tracks if instruction has been externally set as serializeBefore. */
-    bool serializeBefore;
+    bool isTempSerializeBefore() { return status[SerializeBefore]; }
 
     /** Temporarily sets this instruction as a serialize after instruction. */
-    void setSerializeAfter() { serializeAfter = true; }
+    void setSerializeAfter() { status.set(SerializeAfter); }
 
     /** Clears the serializeAfter part of this instruction.*/
-    void clearSerializeAfter() { serializeAfter = false; }
+    void clearSerializeAfter() { status.reset(SerializeAfter); }
 
     /** Checks if this serializeAfter is only temporarily set. */
-    bool isTempSerializeAfter() { return serializeAfter; }
+    bool isTempSerializeAfter() { return status[SerializeAfter]; }
 
-    /** Tracks if instruction has been externally set as serializeAfter. */
-    bool serializeAfter;
+    /** Sets the serialization part of this instruction as handled. */
+    void setSerializeHandled() { status.set(SerializeHandled); }
 
     /** Checks if the serialization part of this instruction has been
      *  handled.  This does not apply to the temporary serializing
      *  state; it only applies to this instruction's own permanent
      *  serializing state.
      */
-    bool isSerializeHandled() { return serializeHandled; }
-
-    /** Sets the serialization part of this instruction as handled. */
-    void setSerializeHandled() { serializeHandled = true; }
-
-    /** Whether or not the serialization of this instruction has been handled. */
-    bool serializeHandled;
+    bool isSerializeHandled() { return status[SerializeHandled]; }
 
     /** Returns the opclass of this instruction. */
     OpClass opClass() const { return staticInst->opClass(); }
@@ -465,106 +429,112 @@ class BaseDynInst : public FastAlloc, public RefCounted
     }
 
     /** Sets this instruction as completed. */
-    void setCompleted() { completed = true; }
+    void setCompleted() { status.set(Completed); }
 
     /** Returns whether or not this instruction is completed. */
-    bool isCompleted() const { return completed; }
+    bool isCompleted() const { return status[Completed]; }
 
-    void setResultReady() { resultReady = true; }
+    /** Marks the result as ready. */
+    void setResultReady() { status.set(ResultReady); }
 
-    bool isResultReady() const { return resultReady; }
+    /** Returns whether or not the result is ready. */
+    bool isResultReady() const { return status[ResultReady]; }
 
     /** Sets this instruction as ready to issue. */
-    void setCanIssue() { canIssue = true; }
+    void setCanIssue() { status.set(CanIssue); }
 
     /** Returns whether or not this instruction is ready to issue. */
-    bool readyToIssue() const { return canIssue; }
+    bool readyToIssue() const { return status[CanIssue]; }
 
     /** Sets this instruction as issued from the IQ. */
-    void setIssued() { issued = true; }
+    void setIssued() { status.set(Issued); }
 
     /** Returns whether or not this instruction has issued. */
-    bool isIssued() const { return issued; }
+    bool isIssued() const { return status[Issued]; }
 
     /** Sets this instruction as executed. */
-    void setExecuted() { executed = true; }
+    void setExecuted() { status.set(Executed); }
 
     /** Returns whether or not this instruction has executed. */
-    bool isExecuted() const { return executed; }
+    bool isExecuted() const { return status[Executed]; }
 
     /** Sets this instruction as ready to commit. */
-    void setCanCommit() { canCommit = true; }
+    void setCanCommit() { status.set(CanCommit); }
 
     /** Clears this instruction as being ready to commit. */
-    void clearCanCommit() { canCommit = false; }
+    void clearCanCommit() { status.reset(CanCommit); }
 
     /** Returns whether or not this instruction is ready to commit. */
-    bool readyToCommit() const { return canCommit; }
+    bool readyToCommit() const { return status[CanCommit]; }
+
+    void setAtCommit() { status.set(AtCommit); }
+
+    bool isAtCommit() { return status[AtCommit]; }
 
     /** Sets this instruction as committed. */
-    void setCommitted() { committed = true; }
+    void setCommitted() { status.set(Committed); }
 
     /** Returns whether or not this instruction is committed. */
-    bool isCommitted() const { return committed; }
+    bool isCommitted() const { return status[Committed]; }
 
     /** Sets this instruction as squashed. */
-    void setSquashed() { squashed = true; }
+    void setSquashed() { status.set(Squashed); }
 
     /** Returns whether or not this instruction is squashed. */
-    bool isSquashed() const { return squashed; }
+    bool isSquashed() const { return status[Squashed]; }
 
     //Instruction Queue Entry
     //-----------------------
     /** Sets this instruction as a entry the IQ. */
-    void setInIQ() { iqEntry = true; }
+    void setInIQ() { status.set(IqEntry); }
 
     /** Sets this instruction as a entry the IQ. */
-    void removeInIQ() { iqEntry = false; }
+    void clearInIQ() { status.reset(IqEntry); }
+
+    /** Returns whether or not this instruction has issued. */
+    bool isInIQ() const { return status[IqEntry]; }
 
     /** Sets this instruction as squashed in the IQ. */
-    void setSquashedInIQ() { squashedInIQ = true; squashed = true;}
+    void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
 
     /** Returns whether or not this instruction is squashed in the IQ. */
-    bool isSquashedInIQ() const { return squashedInIQ; }
-
-    /** Returns whether or not this instruction has issued. */
-    bool isInIQ() const { return iqEntry; }
+    bool isSquashedInIQ() const { return status[SquashedInIQ]; }
 
 
     //Load / Store Queue Functions
     //-----------------------
     /** Sets this instruction as a entry the LSQ. */
-    void setInLSQ() { lsqEntry = true; }
+    void setInLSQ() { status.set(LsqEntry); }
 
     /** Sets this instruction as a entry the LSQ. */
-    void removeInLSQ() { lsqEntry = false; }
+    void removeInLSQ() { status.reset(LsqEntry); }
+
+    /** Returns whether or not this instruction is in the LSQ. */
+    bool isInLSQ() const { return status[LsqEntry]; }
 
     /** Sets this instruction as squashed in the LSQ. */
-    void setSquashedInLSQ() { squashedInLSQ = true;}
+    void setSquashedInLSQ() { status.set(SquashedInLSQ);}
 
     /** Returns whether or not this instruction is squashed in the LSQ. */
-    bool isSquashedInLSQ() const { return squashedInLSQ; }
-
-    /** Returns whether or not this instruction is in the LSQ. */
-    bool isInLSQ() const { return lsqEntry; }
+    bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
 
 
     //Reorder Buffer Functions
     //-----------------------
     /** Sets this instruction as a entry the ROB. */
-    void setInROB() { robEntry = true; }
+    void setInROB() { status.set(RobEntry); }
 
     /** Sets this instruction as a entry the ROB. */
-    void removeInROB() { robEntry = false; }
+    void clearInROB() { status.reset(RobEntry); }
+
+    /** Returns whether or not this instruction is in the ROB. */
+    bool isInROB() const { return status[RobEntry]; }
 
     /** Sets this instruction as squashed in the ROB. */
-    void setSquashedInROB() { squashedInROB = true; }
+    void setSquashedInROB() { status.set(SquashedInROB); }
 
     /** Returns whether or not this instruction is squashed in the ROB. */
-    bool isSquashedInROB() const { return squashedInROB; }
-
-    /** Returns whether or not this instruction is in the ROB. */
-    bool isInROB() const { return robEntry; }
+    bool isSquashedInROB() const { return status[SquashedInROB]; }
 
     /** Read the PC of this instruction. */
     const Addr readPC() const { return PC; }
@@ -581,10 +551,10 @@ class BaseDynInst : public FastAlloc, public RefCounted
     /** Sets the thread id. */
     void setTid(unsigned tid) { threadNumber = tid; }
 
+    /** Sets the pointer to the thread state. */
     void setThreadState(ImplState *state) { thread = state; }
 
-    /** Returns the thread context.
-     */
+    /** Returns the thread context. */
     ThreadContext *tcBase() { return thread->getTC(); }
 
   private:
@@ -621,8 +591,6 @@ class BaseDynInst : public FastAlloc, public RefCounted
     /** Store queue index. */
     int16_t sqIdx;
 
-    bool reachedCommit;
-
     /** Iterator pointing to this BaseDynInst in the list of all insts. */
     ListIt instListIt;
 
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 021d3ef90..b0c8bee77 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -907,7 +907,7 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
         // and committed this instruction.
         thread[tid]->funcExeInst--;
 
-        head_inst->reachedCommit = true;
+        head_inst->setAtCommit();
 
         if (head_inst->isNonSpeculative() ||
             head_inst->isStoreConditional() ||
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index 0748ddb3b..48f6ee612 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -296,7 +296,7 @@ DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid)
     for (int i=0; i<fromFetch->size; i++) {
         if (fromFetch->insts[i]->threadNumber == tid &&
             fromFetch->insts[i]->seqNum > inst->seqNum) {
-            fromFetch->insts[i]->squashed = true;
+            fromFetch->insts[i]->setSquashed();
         }
     }
 
@@ -345,7 +345,7 @@ DefaultDecode<Impl>::squash(unsigned tid)
 
     for (int i=0; i<fromFetch->size; i++) {
         if (fromFetch->insts[i]->threadNumber == tid) {
-            fromFetch->insts[i]->squashed = true;
+            fromFetch->insts[i]->setSquashed();
             squash_count++;
         }
     }
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index b02ee8555..6c207d94a 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -579,7 +579,7 @@ DefaultIEW<Impl>::validInstsFromRename()
     unsigned inst_count = 0;
 
     for (int i=0; i<fromRename->size; i++) {
-        if (!fromRename->insts[i]->squashed)
+        if (!fromRename->insts[i]->isSquashed())
             inst_count++;
     }
 
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 66d4a54c6..1ef1b2cff 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -776,7 +776,7 @@ InstructionQueue<Impl>::scheduleReadyInsts()
                 // complete.
                 ++freeEntries;
                 count[tid]--;
-                issuing_inst->removeInIQ();
+                issuing_inst->clearInIQ();
             } else {
                 memDepUnit[tid].issue(issuing_inst);
             }
@@ -1082,7 +1082,7 @@ InstructionQueue<Impl>::doSquash(unsigned tid)
             // inst will flow through the rest of the pipeline.
             squashed_inst->setIssued();
             squashed_inst->setCanCommit();
-            squashed_inst->removeInIQ();
+            squashed_inst->clearInIQ();
 
             //Update Thread IQ Count
             count[squashed_inst->threadNumber]--;
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 3de581519..2d700ddf1 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -527,7 +527,7 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
     // at the head of the LSQ and are ready to commit (at the head of the ROB
     // too).
     if (req->getFlags() & UNCACHEABLE &&
-        (load_idx != loadHead || !load_inst->reachedCommit)) {
+        (load_idx != loadHead || !load_inst->isAtCommit())) {
         iewStage->rescheduleMemInst(load_inst);
         ++lsqRescheduledLoads;
         return TheISA::genMachineCheckFault();
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index a5c1eb12a..b48d7fb74 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -710,7 +710,7 @@ LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
         }
 
         // Clear the smart pointer to make sure it is decremented.
-        loadQueue[load_idx]->squashed = true;
+        loadQueue[load_idx]->setSquashed();
         loadQueue[load_idx] = NULL;
         --loads;
 
@@ -754,7 +754,7 @@ LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
         }
 
         // Clear the smart pointer to make sure it is decremented.
-        storeQueue[store_idx].inst->squashed = true;
+        storeQueue[store_idx].inst->setSquashed();
         storeQueue[store_idx].inst = NULL;
         storeQueue[store_idx].canWB = 0;
 
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index f9e2a03ee..307022cb8 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -341,7 +341,7 @@ DefaultRename<Impl>::squash(unsigned tid)
 
     for (int i=0; i<fromDecode->size; i++) {
         if (fromDecode->insts[i]->threadNumber == tid) {
-            fromDecode->insts[i]->squashed = true;
+            fromDecode->insts[i]->setSquashed();
             wroteToTimeBuffer = true;
             squashCount++;
         }
@@ -1022,7 +1022,7 @@ DefaultRename<Impl>::validInsts()
     unsigned inst_count = 0;
 
     for (int i=0; i<fromDecode->size; i++) {
-        if (!fromDecode->insts[i]->squashed)
+        if (!fromDecode->insts[i]->isSquashed())
             inst_count++;
     }
 
diff --git a/src/cpu/o3/rob_impl.hh b/src/cpu/o3/rob_impl.hh
index 97694e371..5a941834b 100644
--- a/src/cpu/o3/rob_impl.hh
+++ b/src/cpu/o3/rob_impl.hh
@@ -276,7 +276,7 @@ ROB<Impl>::retireHead(unsigned tid)
     --numInstsInROB;
     --threadEntries[tid];
 
-    head_inst->removeInROB();
+    head_inst->clearInROB();
     head_inst->setCommitted();
 
     instList[tid].erase(head_it);