arch-arm: Change function name for banked miscregs

This commit changes the function's name used for retrieving the index of a
security banked register given the flatten index. This will avoid confusion
with flattenRegId, which has a different purpose.

Change-Id: I470ffb55916cb7fc9f78e071a7f2e609c1829f1a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7982
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

7 files changed, 31 insertions, 31 deletions

diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc
index f7a9745ad..aace1de2b 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -880,7 +880,7 @@ ArmStaticInst::checkSETENDEnabled(ThreadContext *tc, CPSR cpsr) const
 
         // Get the index of the banked version of SCTLR:
         // SCTLR_s or SCTLR_ns.
-        auto banked_sctlr = flattenMiscRegNsBanked(
+        auto banked_sctlr = snsBankedIndex(
             MISCREG_SCTLR, tc, !inSecureState(tc));
 
         // SCTLR.SED bit is enabling/disabling the ue of SETEND instruction.
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 23962b02d..8745e86bc 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -872,7 +872,7 @@ let {{
     exec_output += PredOpExecute.subst(mcr14Iop)
 
     mrc15code = '''
-    int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase());
+    int preFlatOp1 = snsBankedIndex(op1, xc->tcBase());
     MiscRegIndex miscReg = (MiscRegIndex)
                            xc->tcBase()->flattenRegId(RegId(MiscRegClass,
                                                       preFlatOp1)).index();
@@ -904,7 +904,7 @@ let {{
 
 
     mcr15code = '''
-    int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
+    int preFlatDest = snsBankedIndex(dest, xc->tcBase());
     MiscRegIndex miscReg = (MiscRegIndex)
                        xc->tcBase()->flattenRegId(RegId(MiscRegClass,
                                                   preFlatDest)).index();
@@ -937,7 +937,7 @@ let {{
 
 
     mrrc15code = '''
-    int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase());
+    int preFlatOp1 = snsBankedIndex(op1, xc->tcBase());
     MiscRegIndex miscReg = (MiscRegIndex)
                            xc->tcBase()->flattenRegId(RegId(MiscRegClass,
                                                       preFlatOp1)).index();
@@ -968,7 +968,7 @@ let {{
 
 
     mcrr15code = '''
-    int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
+    int preFlatDest = snsBankedIndex(dest, xc->tcBase());
     MiscRegIndex miscReg = (MiscRegIndex)
                            xc->tcBase()->flattenRegId(RegId(MiscRegClass,
                                                       preFlatDest)).index();
@@ -1045,7 +1045,7 @@ let {{
     exec_output += PredOpExecute.subst(clrexIop)
 
     McrDcCheckCode = '''
-        int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
+        int preFlatDest = snsBankedIndex(dest, xc->tcBase());
         MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
             RegId(MiscRegClass, preFlatDest)).index();
         bool hypTrap  = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index babf0accf..3daba5739 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -102,11 +102,11 @@ let {{
         xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(32))
     '''
     cntrlNsBankedWrite = '''
-        xc->setMiscReg(flattenMiscRegNsBanked(dest, xc->tcBase()), %(final_val)s)
+        xc->setMiscReg(snsBankedIndex(dest, xc->tcBase()), %(final_val)s)
     '''
 
     cntrlNsBankedRead = '''
-        xc->readMiscReg(flattenMiscRegNsBanked(op1, xc->tcBase()))
+        xc->readMiscReg(snsBankedIndex(op1, xc->tcBase()))
     '''
 
     #PCState operands need to have a sorting index (the number at the end)
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 445ba18cf..a9031fe0e 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -815,14 +815,14 @@ canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
 }
 
 int
-flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc)
+snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
 {
     SCR scr = tc->readMiscReg(MISCREG_SCR);
-    return flattenMiscRegNsBanked(reg, tc, scr.ns);
+    return snsBankedIndex(reg, tc, scr.ns);
 }
 
 int
-flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc, bool ns)
+snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
 {
     int reg_as_int = static_cast<int>(reg);
     if (miscRegInfo[reg][MISCREG_BANKED]) {
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 779ead7f4..8cfa01345 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -1891,14 +1891,14 @@ namespace ArmISA
     // Uses just the scr.ns bit to pre flatten the misc regs. This is useful
     // for MCR/MRC instructions
     int
-    flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc);
+    snsBankedIndex(MiscRegIndex reg, ThreadContext *tc);
 
     // Flattens a misc reg index using the specified security state. This is
     // used for opperations (eg address translations) where the security
     // state of the register access may differ from the current state of the
     // processor
     int
-    flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc, bool ns);
+    snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns);
 
     // Takes a misc reg index and returns the root reg if its one of a set of
     // banked registers
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 88f6eae42..428556b1a 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -281,9 +281,9 @@ TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint16_t _asid,
         }
         currState->hcr = currState->tc->readMiscReg(MISCREG_HCR_EL2);
     } else {
-        currState->sctlr = currState->tc->readMiscReg(flattenMiscRegNsBanked(
+        currState->sctlr = currState->tc->readMiscReg(snsBankedIndex(
             MISCREG_SCTLR, currState->tc, !currState->isSecure));
-        currState->ttbcr = currState->tc->readMiscReg(flattenMiscRegNsBanked(
+        currState->ttbcr = currState->tc->readMiscReg(snsBankedIndex(
             MISCREG_TTBCR, currState->tc, !currState->isSecure));
         currState->htcr  = currState->tc->readMiscReg(MISCREG_HTCR);
         currState->hcr   = currState->tc->readMiscReg(MISCREG_HCR);
@@ -484,7 +484,7 @@ TableWalker::processWalk()
                     ArmFault::TranslationLL + L1, isStage2,
                     ArmFault::VmsaTran);
         }
-        ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked(
+        ttbr = currState->tc->readMiscReg(snsBankedIndex(
             MISCREG_TTBR0, currState->tc, !currState->isSecure));
     } else {
         DPRINTF(TLB, " - Selecting TTBR1\n");
@@ -503,7 +503,7 @@ TableWalker::processWalk()
                     ArmFault::TranslationLL + L1, isStage2,
                     ArmFault::VmsaTran);
         }
-        ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked(
+        ttbr = currState->tc->readMiscReg(snsBankedIndex(
             MISCREG_TTBR1, currState->tc, !currState->isSecure));
         currState->ttbcr.n = 0;
     }
@@ -616,7 +616,7 @@ TableWalker::processWalkLPAE()
                         isStage2,
                         ArmFault::LpaeTran);
             }
-            ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked(
+            ttbr = currState->tc->readMiscReg(snsBankedIndex(
                 MISCREG_TTBR0, currState->tc, !currState->isSecure));
             tsz = currState->ttbcr.t0sz;
             if (ttbr0_max < (1ULL << 30))  // Upper limit < 1 GB
@@ -640,7 +640,7 @@ TableWalker::processWalkLPAE()
                         isStage2,
                         ArmFault::LpaeTran);
             }
-            ttbr = currState->tc->readMiscReg(flattenMiscRegNsBanked(
+            ttbr = currState->tc->readMiscReg(snsBankedIndex(
                 MISCREG_TTBR1, currState->tc, !currState->isSecure));
             tsz = currState->ttbcr.t1sz;
             if (ttbr1_min >= (1ULL << 31) + (1ULL << 30))  // Lower limit >= 3 GB
@@ -1064,9 +1064,9 @@ TableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
         }
     } else {
         assert(tc);
-        PRRR prrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_PRRR,
+        PRRR prrr = tc->readMiscReg(snsBankedIndex(MISCREG_PRRR,
                                     currState->tc, !currState->isSecure));
-        NMRR nmrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_NMRR,
+        NMRR nmrr = tc->readMiscReg(snsBankedIndex(MISCREG_NMRR,
                                     currState->tc, !currState->isSecure));
         DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr);
         uint8_t curr_tr = 0, curr_ir = 0, curr_or = 0;
@@ -1228,8 +1228,8 @@ TableWalker::memAttrsLPAE(ThreadContext *tc, TlbEntry &te,
         // LPAE always uses remapping of memory attributes, irrespective of the
         // value of SCTLR.TRE
         MiscRegIndex reg = attrIndx & 0x4 ? MISCREG_MAIR1 : MISCREG_MAIR0;
-        int reg_as_int = flattenMiscRegNsBanked(reg, currState->tc,
-                                                !currState->isSecure);
+        int reg_as_int = snsBankedIndex(reg, currState->tc,
+                                        !currState->isSecure);
         uint32_t mair = currState->tc->readMiscReg(reg_as_int);
         attr = (mair >> (8 * (attrIndx % 4))) & 0xff;
         uint8_t attr_7_4 = bits(attr, 7, 4);
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index d3f44c316..3aebe3d59 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1328,28 +1328,28 @@ TLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType)
             stage2Req      = false;
         }
     } else {  // AArch32
-        sctlr  = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_SCTLR, tc,
+        sctlr  = tc->readMiscReg(snsBankedIndex(MISCREG_SCTLR, tc,
                                  !isSecure));
-        ttbcr  = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_TTBCR, tc,
+        ttbcr  = tc->readMiscReg(snsBankedIndex(MISCREG_TTBCR, tc,
                                  !isSecure));
         scr    = tc->readMiscReg(MISCREG_SCR);
         isPriv = cpsr.mode != MODE_USER;
         if (longDescFormatInUse(tc)) {
             uint64_t ttbr_asid = tc->readMiscReg(
-                flattenMiscRegNsBanked(ttbcr.a1 ? MISCREG_TTBR1
-                                                : MISCREG_TTBR0,
+                snsBankedIndex(ttbcr.a1 ? MISCREG_TTBR1 :
+                                          MISCREG_TTBR0,
                                        tc, !isSecure));
             asid = bits(ttbr_asid, 55, 48);
         } else { // Short-descriptor translation table format in use
-            CONTEXTIDR context_id = tc->readMiscReg(flattenMiscRegNsBanked(
+            CONTEXTIDR context_id = tc->readMiscReg(snsBankedIndex(
                 MISCREG_CONTEXTIDR, tc,!isSecure));
             asid = context_id.asid;
         }
-        prrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_PRRR, tc,
+        prrr = tc->readMiscReg(snsBankedIndex(MISCREG_PRRR, tc,
                                !isSecure));
-        nmrr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_NMRR, tc,
+        nmrr = tc->readMiscReg(snsBankedIndex(MISCREG_NMRR, tc,
                                !isSecure));
-        dacr = tc->readMiscReg(flattenMiscRegNsBanked(MISCREG_DACR, tc,
+        dacr = tc->readMiscReg(snsBankedIndex(MISCREG_DACR, tc,
                                !isSecure));
         hcr  = tc->readMiscReg(MISCREG_HCR);