added some comments

--HG--
extra : convert_revision : b33c94984f8d9ac2baf8d7b45fa79460846b1755

4 files changed, 33 insertions, 9 deletions

diff --git a/dev/tsunami.cc b/dev/tsunami.cc
index c6823ffa4..15f48914f 100644
--- a/dev/tsunami.cc
+++ b/dev/tsunami.cc
@@ -80,7 +80,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Tsunami)
     INIT_PARAM(ethernet, "ethernet controller"),
     INIT_PARAM(cons, "system console"),
     INIT_PARAM(intrctrl, "interrupt controller"),
-    INIT_PARAM_DFLT(interrupt_frequency, "frequency of interrupts", 1200)
+    INIT_PARAM_DFLT(interrupt_frequency, "frequency of interrupts", 1024)
 
 END_INIT_SIM_OBJECT_PARAMS(Tsunami)
 
diff --git a/dev/tsunami.hh b/dev/tsunami.hh
index f45bb2059..710cb4b49 100644
--- a/dev/tsunami.hh
+++ b/dev/tsunami.hh
@@ -28,8 +28,8 @@
 
 /**
  * @file
- * Declaration of top level class for the Tsunami chipset. This class just retains pointers
- * to all its children so the children can communicate
+ * Declaration of top level class for the Tsunami chipset. This class just
+ * retains pointers to all its children so the children can communicate.
  */
 
 #ifndef __TSUNAMI_HH__
@@ -45,7 +45,7 @@ class TlaserClock;
 class EtherDev;
 class TsunamiCChip;
 class TsunamiPChip;
-class TsunamiPCIConfig;
+class PCIConfigAll;
 
 /**
   * Top level class for Tsunami Chipset emulation.
@@ -87,7 +87,7 @@ class Tsunami : public SimObject
       * The config space in tsunami all needs to return
       * -1 if a device is not there.
       */
-    TsunamiPCIConfig *pciconfig;
+    PCIConfigAll *pciconfig;
 
     int intr_sum_type[Tsunami::Max_CPUs];
     int ipi_pending[Tsunami::Max_CPUs];
@@ -97,11 +97,15 @@ class Tsunami : public SimObject
   public:
     /**
       * Constructor for the Tsunami Class.
-      * @param
+      * @param name name of the object
+      * @param scsi pointer to scsi controller object
+      * @param con pointer to the console
+      * @param intrcontrol pointer to the interrupt controller
+      * @param intrFreq frequency that interrupts happen
       */
     Tsunami(const std::string &name, AdaptecController *scsi,
                EtherDev *ethernet,
-               SimConsole *, IntrControl *intctrl, int intrFreq);
+               SimConsole *con, IntrControl *intctrl, int intrFreq);
 
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);
diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc
index 17b0f1c48..ceac5300f 100644
--- a/dev/tsunami_cchip.cc
+++ b/dev/tsunami_cchip.cc
@@ -1,7 +1,7 @@
 /* $Id$ */
 
 /* @file
- * Tsunami CChip (processor, memory, or IO)
+ * Emulation of the Tsunami CChip CSRs
  */
 
 #include <deque>
diff --git a/dev/tsunami_cchip.hh b/dev/tsunami_cchip.hh
index a79e60cfc..16d795afb 100644
--- a/dev/tsunami_cchip.hh
+++ b/dev/tsunami_cchip.hh
@@ -27,7 +27,7 @@
  */
 
 /* @file
- * Turbolaser system bus node (processor, memory, or IO)
+ * Emulation of the Tsunami CChip CSRs
  */
 
 #ifndef __TSUNAMI_CCHIP_HH__
@@ -44,10 +44,30 @@ class TsunamiCChip : public MmapDevice
   public:
 
   protected:
+      /**
+       * pointer to the tsunami object.
+       * This is our access to all the other tsunami
+       * devices.
+       */
     Tsunami *tsunami;
+
+    /**
+     * The dims are device interrupt mask registers.
+     * One exists for each CPU, the DRIR X DIM = DIR
+     */
     uint64_t dim[Tsunami::Max_CPUs];
+
+    /**
+     * The dirs are device interrupt registers.
+     * One exists for each CPU, the DRIR X DIM = DIR
+     */
     uint64_t dir[Tsunami::Max_CPUs];
     bool dirInterrupting[Tsunami::Max_CPUs];
+
+    /**
+     * This register contains bits for each PCI interrupt
+     * that can occur.
+     */
     uint64_t drir;
 
   public: