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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2003-10-18 21:21:14 -0700 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2003-10-18 21:21:14 -0700 |
| commit | 83d32482dc126d028399ca6701642047f28276dd (patch) | |
| tree | 737a9f3e2a6974a559046a0da03c5b6db2db7a26 | |
| parent | 1bebc1ab2f49af51cf899be6cb88409abbd81461 (diff) | |
| download | gem5-83d32482dc126d028399ca6701642047f28276dd.tar.xz | |
Add comment to elaborate on store-conditional result code (and remove
stale reference to machine.def).
arch/alpha/isa_desc:
Add comment describing store-conditional result code
cpu/exec_context.hh:
update comments
--HG--
extra : convert_revision : ac59e0ad7a9440cb6656617fdf05495b59c68f55
| -rw-r--r-- | arch/alpha/isa_desc | 8 | ||||
| -rw-r--r-- | cpu/exec_context.hh | 13 |
2 files changed, 14 insertions, 7 deletions
diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index e9b93a895..b5536525d 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -1808,11 +1808,19 @@ decode OPCODE default Unknown::unknown() { 0x2e: stl_c({{ EA = Rb + disp; }}, {{ Mem.ul = Ra<31:0>; }}, {{ uint64_t tmp = Mem_write_result; + // see stq_c Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; }}, LOCKED); 0x2f: stq_c({{ EA = Rb + disp; }}, {{ Mem.uq = Ra; }}, {{ uint64_t tmp = Mem_write_result; + // If the write operation returns 0 or 1, then + // this was a conventional store conditional, + // and the value indicates the success/failure + // of the operation. If another value is + // returned, then this was a Turbolaser + // mailbox access, and we don't update the + // result register at all. Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; }}, LOCKED); } diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh index ddfc53684..4a2688f1c 100644 --- a/cpu/exec_context.hh +++ b/cpu/exec_context.hh @@ -218,7 +218,7 @@ class ExecContext cregs = &req->xc->regs.miscRegs; if (req->flags & UNCACHEABLE) { - // Don't update result register (see machine.def) + // Don't update result register (see stq_c in isa_desc) req->result = 2; req->xc->storeCondFailures = 0;//Needed? [RGD] } else { @@ -239,12 +239,11 @@ class ExecContext } } - // Need to clear any locked flags on other proccessors for this - // address - // Only do this for succsful Store Conditionals and all other - // stores (WH64?) - // Unsuccesful Store Conditionals would have returned above, - // and wouldn't fall through + // Need to clear any locked flags on other proccessors for + // this address. Only do this for succsful Store Conditionals + // and all other stores (WH64?). Unsuccessful Store + // Conditionals would have returned above, and wouldn't fall + // through. for (int i = 0; i < system->xcvec.size(); i++){ cregs = &system->xcvec[i]->regs.miscRegs; if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) { |