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| author | Binh Pham <binhpham@cs.rutgers.edu> | 2014-06-21 10:26:55 -0700 |
|---|---|---|
| committer | Binh Pham <binhpham@cs.rutgers.edu> | 2014-06-21 10:26:55 -0700 |
| commit | b72c8798682d307adfe9c1c2a77ac5a6d6240c15 (patch) | |
| tree | 0c3c1ad306709bd44d07f9eaca3dac63809f5409 | |
| parent | 0782d92286ded450b7e615fefbd5d6d5e738c8cd (diff) | |
| download | gem5-b72c8798682d307adfe9c1c2a77ac5a6d6240c15.tar.xz | |
o3: make dispatch LSQ full check more selective
Dispatch should not check LSQ size/LSQ stall for non load/store
instructions.
This work was done while Binh was an intern at AMD Research.
| -rw-r--r-- | src/cpu/o3/iew_impl.hh | 28 |
1 files changed, 7 insertions, 21 deletions
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh index 20d3a1c36..9c6a44bf2 100644 --- a/src/cpu/o3/iew_impl.hh +++ b/src/cpu/o3/iew_impl.hh @@ -793,25 +793,6 @@ DefaultIEW<Impl>::checkStall(ThreadID tid) } else if (instQueue.isFull(tid)) { DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); ret_val = true; - } else if (ldstQueue.isFull(tid)) { - DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); - - if (ldstQueue.numLoads(tid) > 0 ) { - - DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", - tid,ldstQueue.getLoadHeadSeqNum(tid)); - } - - if (ldstQueue.numStores(tid) > 0) { - - DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", - tid,ldstQueue.getStoreHeadSeqNum(tid)); - } - - ret_val = true; - } else if (ldstQueue.isStalled(tid)) { - DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); - ret_val = true; } return ret_val; @@ -1074,8 +1055,13 @@ DefaultIEW<Impl>::dispatchInsts(ThreadID tid) ++iewIQFullEvents; break; - } else if (ldstQueue.isFull(tid)) { - DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); + } + + // Check LSQ if inst is LD/ST + if ((inst->isLoad() && ldstQueue.lqFull(tid)) || + (inst->isStore() && ldstQueue.sqFull(tid))) { + DPRINTF(IEW, "[tid:%i]: Issue: %s has become full.\n",tid, + inst->isLoad() ? "LQ" : "SQ"); // Call function to start blocking. block(tid); |