diff options
author | Nathan Binkert <nate@binkert.org> | 2010-02-26 18:14:48 -0800 |
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committer | Nathan Binkert <nate@binkert.org> | 2010-02-26 18:14:48 -0800 |
commit | f0b4259e98773bee04cd0af5dda7bcfba5032589 (patch) | |
tree | 6507a2f53b7e645d7ab30fd43384afa4b6b98b48 | |
parent | ac106767c86e58af623c81ed04521ea40ad7b8a9 (diff) | |
download | gem5-f0b4259e98773bee04cd0af5dda7bcfba5032589.tar.xz |
cpu_models: get rid of cpu_models.py and move the stuff into SCons
-rw-r--r-- | SConstruct | 38 | ||||
-rw-r--r-- | src/arch/SConscript | 10 | ||||
-rw-r--r-- | src/cpu/SConscript | 8 | ||||
-rw-r--r-- | src/cpu/checker/SConsopts | 35 | ||||
-rw-r--r-- | src/cpu/cpu_models.py | 87 | ||||
-rw-r--r-- | src/cpu/inorder/SConsopts | 6 | ||||
-rw-r--r-- | src/cpu/o3/SConsopts | 6 | ||||
-rw-r--r-- | src/cpu/ozone/SConsopts | 8 | ||||
-rw-r--r-- | src/cpu/simple/SConsopts | 10 |
9 files changed, 90 insertions, 118 deletions
diff --git a/SConstruct b/SConstruct index 6ca3d6a14..55cf71876 100644 --- a/SConstruct +++ b/SConstruct @@ -612,10 +612,34 @@ main = conf.Finish() all_isa_list = [ ] Export('all_isa_list') -# Define the universe of supported CPU models -all_cpu_list = [ ] -default_cpus = [ ] -Export('all_cpu_list', 'default_cpus') +class CpuModel(object): + '''The CpuModel class encapsulates everything the ISA parser needs to + know about a particular CPU model.''' + + # Dict of available CPU model objects. Accessible as CpuModel.dict. + dict = {} + list = [] + defaults = [] + + # Constructor. Automatically adds models to CpuModel.dict. + def __init__(self, name, filename, includes, strings, default=False): + self.name = name # name of model + self.filename = filename # filename for output exec code + self.includes = includes # include files needed in exec file + # The 'strings' dict holds all the per-CPU symbols we can + # substitute into templates etc. + self.strings = strings + + # This cpu is enabled by default + self.default = default + + # Add self to dict + if name in CpuModel.dict: + raise AttributeError, "CpuModel '%s' already registered" % name + CpuModel.dict[name] = self + CpuModel.list.append(name) + +Export('CpuModel') # Sticky variables get saved in the variables file so they persist from # one invocation to the next (unless overridden, in which case the new @@ -640,13 +664,13 @@ for bdir in [ base_dir ] + extras_dir_list: SConscript(joinpath(root, 'SConsopts')) all_isa_list.sort() -all_cpu_list.sort() -default_cpus.sort() sticky_vars.AddVariables( EnumVariable('TARGET_ISA', 'Target ISA', 'alpha', all_isa_list), BoolVariable('FULL_SYSTEM', 'Full-system support', False), - ListVariable('CPU_MODELS', 'CPU models', default_cpus, all_cpu_list), + ListVariable('CPU_MODELS', 'CPU models', + sorted(n for n,m in CpuModel.dict.iteritems() if m.default), + sorted(CpuModel.list)), BoolVariable('NO_FAST_ALLOC', 'Disable fast object allocator', False), BoolVariable('FAST_ALLOC_DEBUG', 'Enable fast object allocator debugging', False), diff --git a/src/arch/SConscript b/src/arch/SConscript index 61b570313..adbf4c292 100644 --- a/src/arch/SConscript +++ b/src/arch/SConscript @@ -90,16 +90,6 @@ env.Append(SCANNERS = isa_scanner) # output from the ISA description (*.isa) files. # -# -# Grab the CPU Model information -# - -# Convert to File node to fix path -cpu_models_file = File('../cpu/cpu_models.py') - -# This sucks in the defintions of the CpuModel objects. -execfile(cpu_models_file.srcnode().abspath) - # The emitter patches up the sources & targets to include the # autogenerated files as targets and isa parser itself as a source. def isa_desc_emitter(target, source, env): diff --git a/src/cpu/SConscript b/src/cpu/SConscript index b89a589c6..6b4c43dc0 100644 --- a/src/cpu/SConscript +++ b/src/cpu/SConscript @@ -40,12 +40,6 @@ Import('*') # ################################################################# -# CPU model-specific data is contained in cpu_models.py -# Convert to SCons File node to get path handling -models_db = File('cpu_models.py') -# slurp in contents of file -execfile(models_db.srcnode().abspath) - # Template for execute() signature. exec_sig_template = ''' virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0; @@ -97,7 +91,7 @@ def gen_sigs_string(target, source, env): + ', '.join(temp_cpu_list) # Add command to generate header to environment. -env.Command('static_inst_exec_sigs.hh', models_db, +env.Command('static_inst_exec_sigs.hh', (), Action(gen_cpu_exec_signatures, gen_sigs_string, varlist = temp_cpu_list)) diff --git a/src/cpu/checker/SConsopts b/src/cpu/checker/SConsopts new file mode 100644 index 000000000..94d8e0e9f --- /dev/null +++ b/src/cpu/checker/SConsopts @@ -0,0 +1,35 @@ +# -*- mode:python -*- + +# Copyright (c) 2003-2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Steve Reinhardt + +Import('*') + +CpuModel('CheckerCPU', 'checker_cpu_exec.cc', + '#include "cpu/checker/cpu.hh"', + { 'CPU_exec_context': 'CheckerCPU' }) diff --git a/src/cpu/cpu_models.py b/src/cpu/cpu_models.py deleted file mode 100644 index 793f8c646..000000000 --- a/src/cpu/cpu_models.py +++ /dev/null @@ -1,87 +0,0 @@ -# Copyright (c) 2003-2006 The Regents of The University of Michigan -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Steve Reinhardt - -import os -import os.path -import sys - -################ -# CpuModel class -# -# The CpuModel class encapsulates everything the ISA parser needs to -# know about a particular CPU model. - -class CpuModel: - # Dict of available CPU model objects. Accessible as CpuModel.dict. - dict = {} - - # Constructor. Automatically adds models to CpuModel.dict. - def __init__(self, name, filename, includes, strings): - self.name = name - self.filename = filename # filename for output exec code - self.includes = includes # include files needed in exec file - # The 'strings' dict holds all the per-CPU symbols we can - # substitute into templates etc. - self.strings = strings - # Add self to dict - CpuModel.dict[name] = self - -# -# Define CPU models. -# -# Parameters are: -# - name of model -# - filename for generated ISA execution file -# - includes needed for generated ISA execution file -# - substitution strings for ISA description templates -# - -CpuModel('AtomicSimpleCPU', 'atomic_simple_cpu_exec.cc', - '#include "cpu/simple/atomic.hh"', - { 'CPU_exec_context': 'AtomicSimpleCPU' }) -CpuModel('TimingSimpleCPU', 'timing_simple_cpu_exec.cc', - '#include "cpu/simple/timing.hh"', - { 'CPU_exec_context': 'TimingSimpleCPU' }) -CpuModel('FullCPU', 'full_cpu_exec.cc', - '#include "encumbered/cpu/full/dyn_inst.hh"', - { 'CPU_exec_context': 'DynInst' }) -CpuModel('OzoneSimpleCPU', 'ozone_simple_exec.cc', - '#include "cpu/ozone/dyn_inst.hh"', - { 'CPU_exec_context': 'OzoneDynInst<SimpleImpl>' }) -CpuModel('OzoneCPU', 'ozone_exec.cc', - '#include "cpu/ozone/dyn_inst.hh"', - { 'CPU_exec_context': 'OzoneDynInst<OzoneImpl>' }) -CpuModel('CheckerCPU', 'checker_cpu_exec.cc', - '#include "cpu/checker/cpu.hh"', - { 'CPU_exec_context': 'CheckerCPU' }) -CpuModel('O3CPU', 'o3_cpu_exec.cc', - '#include "cpu/o3/isa_specific.hh"', - { 'CPU_exec_context': 'O3DynInst' }) -CpuModel('InOrderCPU', 'inorder_cpu_exec.cc', - '#include "cpu/inorder/inorder_dyn_inst.hh"', - { 'CPU_exec_context': 'InOrderDynInst' }) diff --git a/src/cpu/inorder/SConsopts b/src/cpu/inorder/SConsopts index e66119c6d..709051407 100644 --- a/src/cpu/inorder/SConsopts +++ b/src/cpu/inorder/SConsopts @@ -30,5 +30,7 @@ Import('*') -all_cpu_list.append('InOrderCPU') -default_cpus.append('InOrderCPU') +CpuModel('InOrderCPU', 'inorder_cpu_exec.cc', + '#include "cpu/inorder/inorder_dyn_inst.hh"', + { 'CPU_exec_context': 'InOrderDynInst' }, + default=True) diff --git a/src/cpu/o3/SConsopts b/src/cpu/o3/SConsopts index 040352e6a..b780f6b2a 100644 --- a/src/cpu/o3/SConsopts +++ b/src/cpu/o3/SConsopts @@ -30,5 +30,7 @@ Import('*') -all_cpu_list.append('O3CPU') -default_cpus.append('O3CPU') +CpuModel('O3CPU', 'o3_cpu_exec.cc', + '#include "cpu/o3/isa_specific.hh"', + { 'CPU_exec_context': 'O3DynInst' }, + default=True) diff --git a/src/cpu/ozone/SConsopts b/src/cpu/ozone/SConsopts index 341644dcd..adfda63a9 100644 --- a/src/cpu/ozone/SConsopts +++ b/src/cpu/ozone/SConsopts @@ -30,4 +30,10 @@ Import('*') -all_cpu_list.append('OzoneCPU') +CpuModel('OzoneSimpleCPU', 'ozone_simple_exec.cc', + '#include "cpu/ozone/dyn_inst.hh"', + { 'CPU_exec_context': 'OzoneDynInst<SimpleImpl>' }) +CpuModel('OzoneCPU', 'ozone_exec.cc', + '#include "cpu/ozone/dyn_inst.hh"', + { 'CPU_exec_context': 'OzoneDynInst<OzoneImpl>' }) + diff --git a/src/cpu/simple/SConsopts b/src/cpu/simple/SConsopts index 32dbda1a5..ab84144af 100644 --- a/src/cpu/simple/SConsopts +++ b/src/cpu/simple/SConsopts @@ -30,5 +30,11 @@ Import('*') -all_cpu_list.extend(('AtomicSimpleCPU', 'TimingSimpleCPU')) -default_cpus.extend(('AtomicSimpleCPU', 'TimingSimpleCPU')) +CpuModel('AtomicSimpleCPU', 'atomic_simple_cpu_exec.cc', + '#include "cpu/simple/atomic.hh"', + { 'CPU_exec_context': 'AtomicSimpleCPU' }, + default=True) +CpuModel('TimingSimpleCPU', 'timing_simple_cpu_exec.cc', + '#include "cpu/simple/timing.hh"', + { 'CPU_exec_context': 'TimingSimpleCPU' }, + default=True) |