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| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-08-19 03:52:24 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-08-19 03:52:24 -0400 |
| commit | 9b2effd9e2d30c5e2a72bfe78214cd88689d89d9 (patch) | |
| tree | 686c4d7fc155f4c69605d77e056a2e91af99d818 | |
| parent | cf56619b0ce0f6dc4cf3ee8af57533c169fb0123 (diff) | |
| download | gem5-9b2effd9e2d30c5e2a72bfe78214cd88689d89d9.tar.xz | |
cpu: Fix a bug in the O3 CPU introduced by the cache line patch
This patch fixes a bug in the O3 fetch stage that was introduced when
the cache line size was moved to the system. By mistake, the
initialisation and resetting of the fetch stage was merged and put in
the constructor. The resetting is now re-added where it should be.
| -rw-r--r-- | src/cpu/o3/fetch_impl.hh | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 0445de921..f6e46cc26 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -344,6 +344,11 @@ DefaultFetch<Impl>::resetStage() wroteToTimeBuffer = false; _status = Inactive; + + for (ThreadID tid = 0; tid < numThreads; tid++) { + cacheDataPC[tid] = 0; + cacheDataValid[tid] = false; + } } template<class Impl> |