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authorRon Dreslinski <rdreslin@umich.edu>2006-10-10 17:32:24 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-10-10 17:32:24 -0400
commit27c59dc370f2f851a8426d6024fa4d2acb296238 (patch)
tree9373e4e7feae294fdbd593c083719f89ae326b64
parent549412b33361629b03d9d85dac3bb3efa2f07baf (diff)
parentaff3d92c007f7c971eed8417b1d7602394755398 (diff)
downloadgem5-27c59dc370f2f851a8426d6024fa4d2acb296238.tar.xz
Merge zizzer:/n/wexford/x/gblack/m5/newmem_bus
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest --HG-- extra : convert_revision : 7b7a1b03ffed36bce49595962ea57c08d1d1a4ad
-rw-r--r--src/mem/cache/base_cache.cc2
-rw-r--r--src/mem/cache/base_cache.hh2
2 files changed, 3 insertions, 1 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 0141fa2a0..4df13fb2b 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -221,6 +221,7 @@ BaseCache::CacheEvent::process()
}
else if (!cachePort->isCpuSide)
{
+ assert(cachePort->cache->doMasterRequest());
//MSHR
pkt = cachePort->cache->getPacket();
MSHR* mshr = (MSHR*) pkt->senderState;
@@ -238,6 +239,7 @@ BaseCache::CacheEvent::process()
}
else
{
+ assert(cachePort->cache->doSlaveRequest());
//CSHR
pkt = cachePort->cache->getCoherencePacket();
bool success = cachePort->sendTiming(pkt);
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 41c28f3a1..563b1ca8b 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -467,7 +467,7 @@ class BaseCache : public MemObject
*/
void setMasterRequest(RequestCause cause, Tick time)
{
- if (!doMasterRequest() && memSidePort->drainList.empty())
+ if (!doMasterRequest() && !memSidePort->waitingOnRetry)
{
BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(memSidePort);
reqCpu->schedule(time);