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authorGabe Black <gblack@eecs.umich.edu>2008-06-12 00:58:13 -0400
committerGabe Black <gblack@eecs.umich.edu>2008-06-12 00:58:13 -0400
commitda20c0ec54d322cbffe3c7d0053ea4dc8be24d94 (patch)
treec758b6e68aae1c71d3eccd79c794ddffc39bca9a
parent1f5b992b582f0d8de792df24a81d4a25642b3e45 (diff)
downloadgem5-da20c0ec54d322cbffe3c7d0053ea4dc8be24d94.tar.xz
X86: Make sure there's something to catch when the kernel messes with ports "behind" the pci config magic ports.
-rw-r--r--src/dev/x86/PC.py5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/dev/x86/PC.py b/src/dev/x86/PC.py
index 86ae4c3ba..4ba9e7a8a 100644
--- a/src/dev/x86/PC.py
+++ b/src/dev/x86/PC.py
@@ -50,6 +50,10 @@ class PC(Platform):
# "Non-existant" port used for timing purposes by the linux kernel
i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)
+ # Ports behind the pci config and data regsiters. These don't do anything,
+ # but the linux kernel fiddles with them anway.
+ behind_pci = IsaFake(pio_addr=x86IOAddress(0xcf8), pio_size=8)
+
# Serial port and console
console = SimConsole()
com_1 = Uart8250()
@@ -59,6 +63,7 @@ class PC(Platform):
def attachIO(self, bus):
self.south_bridge.pio = bus.port
self.i_dont_exist.pio = bus.port
+ self.behind_pci.pio = bus.port
self.com_1.pio = bus.port
self.pciconfig.pio = bus.default
bus.responder_set = True