Merge zed.eecs.umich.edu:/.automount/zeep/z/saidi/work/m5.newmem

into  zed.eecs.umich.edu:/z/hsul/work/sparc/x86.m5

--HG--
extra : convert_revision : 9b8567bb775ed6fcc30096f1ab4cc37058bc7376

8 files changed, 111 insertions, 39 deletions

diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 2e1344a8f..bd1a44342 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -1079,6 +1079,9 @@ decode OP default Unknown::unknown()
                 //ASI_LDTX_N_L
                 0x2F: TwinLoad::ldtx_n_l(
                     {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
+                //ASI_LDTX_P
+                0xE2: TwinLoad::ldtx_p(
+                    {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
                 default: ldtwa({{
                         uint64_t val = Mem.udw;
                         RdLow = val<31:0>;
diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa
index 5d05dad03..32421a75f 100644
--- a/src/arch/sparc/isa/formats/mem/blockmem.isa
+++ b/src/arch/sparc/isa/formats/mem/blockmem.isa
@@ -1,4 +1,4 @@
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright (c) 2006-2007 The Regents of The University of Michigan
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -451,6 +451,8 @@ let {{
             flag_code = ''
             if (microPc == 7):
                 flag_code = "flags[IsLastMicroOp] = true;"
+            elif (microPc == 0):
+                flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;"
             else:
                 flag_code = "flags[IsDelayedCommit] = true;"
             pcedCode = matcher.sub("Frd_%d" % microPc, code)
@@ -492,7 +494,7 @@ let {{
                 flag_code = "flags[IsLastMicroOp] = true;"
                 pcedCode = matcher.sub("RdHigh", code)
             else:
-                flag_code = "flags[IsDelayedCommit] = true;"
+                flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;"
                 pcedCode = matcher.sub("RdLow", code)
             iop = InstObjParams(name, Name, 'TwinMem', pcedCode,
                     opt_flags, {"ea_code": addrCalcReg,
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 1cecb4ebb..612345300 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -81,21 +81,44 @@ TLB::insert(Addr va, int partition_id, int context_id, bool real,
 
     MapIter i;
     TlbEntry *new_entry = NULL;
-    TlbRange tr;
+//    TlbRange tr;
     int x;
 
     cacheValid = false;
-    tr.va = va;
+ /*   tr.va = va;
     tr.size = PTE.size() - 1;
     tr.contextId = context_id;
     tr.partitionId = partition_id;
     tr.real = real;
-
+*/
 
     DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
             va, PTE.paddr(), partition_id, context_id, (int)real, entry);
 
     // Demap any entry that conflicts
+    for (x = 0; x < size; x++) {
+        if (tlb[x].range.real == real &&
+            tlb[x].range.partitionId == partition_id &&
+            tlb[x].range.va < va + PTE.size() - 1 &&
+            tlb[x].range.va + tlb[x].range.size >= va &&
+            (real || tlb[x].range.contextId == context_id ))
+        {
+            if (tlb[x].valid) {
+                freeList.push_front(&tlb[x]);
+                DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x);
+
+                tlb[x].valid = false;
+                if (tlb[x].used) {
+                    tlb[x].used = false;
+                    usedEntries--;
+                }
+                lookupTable.erase(tlb[x].range);
+            }
+        }
+    }
+
+
+/*
     i = lookupTable.find(tr);
     if (i != lookupTable.end()) {
         i->second->valid = false;
@@ -108,7 +131,7 @@ TLB::insert(Addr va, int partition_id, int context_id, bool real,
                 i->second);
         lookupTable.erase(i);
     }
-
+*/
 
     if (entry != -1) {
         assert(entry < size && entry >= 0);
@@ -127,7 +150,6 @@ TLB::insert(Addr va, int partition_id, int context_id, bool real,
             } while (tlb[x].pte.locked());
             lastReplaced = x;
             new_entry = &tlb[x];
-            lookupTable.erase(new_entry->range);
         }
         /*
         for (x = 0; x < size; x++) {
@@ -142,10 +164,15 @@ insertAllLocked:
     // Update the last ently if their all locked
     if (!new_entry) {
         new_entry = &tlb[size-1];
-        lookupTable.erase(new_entry->range);
     }
 
     freeList.remove(new_entry);
+    if (new_entry->valid && new_entry->used)
+        usedEntries--;
+
+    lookupTable.erase(new_entry->range);
+
+
     DPRINTF(TLB, "Using entry: %#X\n", new_entry);
 
     assert(PTE.valid());
@@ -315,10 +342,12 @@ TLB::invalidateAll()
     cacheValid = false;
 
     freeList.clear();
+    lookupTable.clear();
     for (x = 0; x < size; x++) {
         if (tlb[x].valid == true)
             freeList.push_back(&tlb[x]);
         tlb[x].valid = false;
+        tlb[x].used = false;
     }
     usedEntries = 0;
 }
@@ -625,13 +654,12 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
             return new DataAccessException;
         }
 
-    } /*else if (hpriv) {*/
-        if (asi == ASI_P) {
-            ct = Primary;
-            context = pri_context;
-            goto continueDtbFlow;
-        }
-    //}
+    }
+    if (asi == ASI_P || asi == ASI_LDTX_P) {
+        ct = Primary;
+        context = pri_context;
+        goto continueDtbFlow;
+    }
 
     if (!implicit) {
         if (AsiIsLittle(asi))
@@ -640,10 +668,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
             panic("Block ASIs not supported\n");
         if (AsiIsNoFault(asi))
             panic("No Fault ASIs not supported\n");
-        if (write && asi == ASI_LDTX_P)
-            // block init store (like write hint64)
-            goto continueDtbFlow;
-        if (!write && asi == ASI_QUAD_LDD)
+        if (!write && (asi == ASI_QUAD_LDD || asi == ASI_LDTX_REAL))
             goto continueDtbFlow;
 
         if (AsiIsTwin(asi))
@@ -880,6 +905,9 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
             temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
             pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
             break;
+          case 0x18:
+            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR));
+            break;
           case 0x30:
             pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS));
             break;
@@ -893,6 +921,12 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
             temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
             pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
             break;
+          case 0x18:
+            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR));
+            break;
+          case 0x20:
+            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR));
+            break;
           case 0x30:
             pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS));
             break;
@@ -1074,6 +1108,9 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
         break;
       case ASI_IMMU:
         switch (va) {
+          case 0x18:
+            tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data);
+            break;
           case 0x30:
             tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data);
             break;
@@ -1145,6 +1182,9 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
         break;
       case ASI_DMMU:
         switch (va) {
+          case 0x18:
+            tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data);
+            break;
           case 0x30:
             tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
             break;
diff --git a/src/base/loader/raw_object.cc b/src/base/loader/raw_object.cc
index 2a52b0d6e..d002d9005 100644
--- a/src/base/loader/raw_object.cc
+++ b/src/base/loader/raw_object.cc
@@ -63,19 +63,19 @@ RawObject::RawObject(const std::string &_filename, int _fd, size_t _len,
 bool
 RawObject::loadGlobalSymbols(SymbolTable *symtab, Addr addrMask)
 {
-    int fnameStart = filename.rfind('/',filename.size()) + 1;
+/*    int fnameStart = filename.rfind('/',filename.size()) + 1;
     int extStart = filename.rfind('.',filename.size());
     symtab->insert(text.baseAddr & addrMask, filename.substr(fnameStart,
-                extStart-fnameStart) + "_start");
+                extStart-fnameStart) + "_start");*/
     return true;
 }
 
 bool
 RawObject::loadLocalSymbols(SymbolTable *symtab, Addr addrMask)
 {
-    int fnameStart = filename.rfind('/',filename.size()) + 1;
+/*    int fnameStart = filename.rfind('/',filename.size()) + 1;
     int extStart = filename.rfind('.',filename.size());
     symtab->insert(text.baseAddr & addrMask, filename.substr(fnameStart,
-                extStart-fnameStart) + "_start");
+                extStart-fnameStart) + "_start");*/
     return true;
 }
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 6e0bf6d33..87075c1ec 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -59,6 +59,7 @@ using namespace TheISA;
 
 #if THE_ISA == SPARC_ISA && FULL_SYSTEM
 static int diffcount = 0;
+static bool wasMicro = false;
 #endif
 
 namespace Trace {
@@ -124,6 +125,7 @@ inline void printLevelHeader(ostream & os, int level)
 void
 Trace::InstRecord::dump(ostream &outs)
 {
+    DPRINTF(Sparc, "Instruction: %#X\n", staticInst->machInst);
     if (flags[PRINT_REG_DELTA])
     {
 #if THE_ISA == SPARC_ISA
@@ -315,6 +317,24 @@ Trace::InstRecord::dump(ostream &outs)
         bool diffTlb = false;
         Addr m5Pc, lgnPc;
 
+        // We took a trap on a micro-op...
+        if (wasMicro && !staticInst->isMicroOp())
+        {
+            // let's skip comparing this cycle
+            while (!compared)
+                if (shared_data->flags == OWN_M5) {
+                    shared_data->flags = OWN_LEGION;
+                    compared = true;
+                }
+            compared = false;
+            wasMicro = false;
+        }
+
+        if (staticInst->isLastMicroOp())
+            wasMicro = false;
+        else if (staticInst->isMicroOp())
+            wasMicro = true;
+
 
         if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) {
             while (!compared) {
@@ -587,24 +607,28 @@ Trace::InstRecord::dump(ostream &outs)
                                     << endl;*/
                             }
                         }
-                        printColumnLabels(outs);
-                        char label[8];
-                        for (int x = 0; x < 64; x++) {
-                            if (shared_data->itb[x] !=  ULL(0xFFFFFFFFFFFFFFFF) ||
-                                thread->getITBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF))  {
-                                    sprintf(label, "I-TLB:%02d", x);
-                                    printRegPair(outs, label, thread->getITBPtr()->TteRead(x), shared_data->itb[x]);
+                        if (diffTlb) {
+                            printColumnLabels(outs);
+                            char label[8];
+                            for (int x = 0; x < 64; x++) {
+                                if (shared_data->itb[x] !=  ULL(0xFFFFFFFFFFFFFFFF) ||
+                                    thread->getITBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF))  {
+                                        sprintf(label, "I-TLB:%02d", x);
+                                        printRegPair(outs, label, thread->getITBPtr()->TteRead(x),
+                                                shared_data->itb[x]);
+                                }
                             }
-                        }
-                        for (int x = 0; x < 64; x++) {
-                            if (shared_data->dtb[x] !=  ULL(0xFFFFFFFFFFFFFFFF) ||
-                                thread->getDTBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF))  {
-                                    sprintf(label, "D-TLB:%02d", x);
-                                    printRegPair(outs, label, thread->getDTBPtr()->TteRead(x), shared_data->dtb[x]);
+                            for (int x = 0; x < 64; x++) {
+                                if (shared_data->dtb[x] !=  ULL(0xFFFFFFFFFFFFFFFF) ||
+                                    thread->getDTBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF))  {
+                                        sprintf(label, "D-TLB:%02d", x);
+                                        printRegPair(outs, label, thread->getDTBPtr()->TteRead(x),
+                                                shared_data->dtb[x]);
+                                }
                             }
+                            thread->getITBPtr()->dumpAll();
+                            thread->getDTBPtr()->dumpAll();
                         }
-                        thread->getITBPtr()->dumpAll();
-                        thread->getDTBPtr()->dumpAll();
 
                         diffcount++;
                         if (diffcount > 2)
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 8db864153..3b3536e44 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -497,7 +497,7 @@ AtomicSimpleCPU::tick()
 
             // @todo remove me after debugging with legion done
             if (curStaticInst && (!curStaticInst->isMicroOp() ||
-                        curStaticInst->isLastMicroOp()))
+                        curStaticInst->isFirstMicroOp()))
                 instCnt++;
 
             if (simulate_stalls) {
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 4e5754bbb..ddccc5a9b 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -437,6 +437,7 @@ void
 BaseSimpleCPU::advancePC(Fault fault)
 {
     if (fault != NoFault) {
+        curMacroStaticInst = StaticInst::nullStaticInstPtr;
         fault->invoke(tc);
     } else {
         //If we're at the last micro op for this instruction
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 523cfae40..5928eea76 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -146,6 +146,7 @@ class StaticInstBase : public RefCounted
         IsMicroOp,	///< Is a microop
         IsDelayedCommit,	///< This microop doesn't commit right away
         IsLastMicroOp,	///< This microop ends a microop sequence
+        IsFirstMicroOp,	///< This microop begins a microop sequence
         //This flag doesn't do anything yet
         IsMicroBranch,	///< This microop branches within the microcode for a macroop
 
@@ -244,6 +245,7 @@ class StaticInstBase : public RefCounted
     bool isMicroOp() const { return flags[IsMicroOp]; }
     bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
     bool isLastMicroOp() const { return flags[IsLastMicroOp]; }
+    bool isFirstMicroOp() const { return flags[IsFirstMicroOp]; }
     //This flag doesn't do anything yet
     bool isMicroBranch() const { return flags[IsMicroBranch]; }
     //@}