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authorGabe Black <gblack@eecs.umich.edu>2006-12-16 07:10:58 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-12-16 07:10:58 -0500
commit181f4f32f6a2ffd19700e54cd5581fce19ec04a5 (patch)
tree0771cd4bd003a1f71492c7f40a872e39ccabe7bb
parent6aa06a26b7e0c1e44427aa5360cba5662f2907c9 (diff)
downloadgem5-181f4f32f6a2ffd19700e54cd5581fce19ec04a5.tar.xz
Made changes to CWP be non speculative.
--HG-- extra : convert_revision : 43899bc97061c33e67a53179c23e46b079118117
-rw-r--r--src/arch/sparc/isa/operands.isa2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index 9a5fda6ff..256f2fa43 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -123,7 +123,7 @@ def operands {{
'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59),
'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60),
'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61),
- 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing']), 62),
+ 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 62),
# 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63),
# 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64),
# 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65),