diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:18:45 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:18:45 -0800 |
| commit | 1bfab291f1899a3e241977425339c799dc96fa9d (patch) | |
| tree | 5ce83cb49bca9aea30550505099f8e59e2082d28 | |
| parent | da61c4b3ee4571d43f7133640eeda2cf51e21cd9 (diff) | |
| download | gem5-1bfab291f1899a3e241977425339c799dc96fa9d.tar.xz | |
CPU: Update stats now that there's no fetch in the middle of macroops.
21 files changed, 273 insertions, 270 deletions
diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout index d7c279dee..12ee4624b 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:17:12 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:50:17 -M5 executing on zizzer +M5 compiled Feb 24 2009 01:30:29 +M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch +M5 started Feb 24 2009 01:30:33 +M5 executing on tater command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py long/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -43,4 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2080416155000 because target called exit() +Exiting @ tick 2076000961000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 5a55fc3e0..9a15c39dd 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1502574 # Simulator instruction rate (inst/s) -host_mem_usage 205236 # Number of bytes of host memory used -host_seconds 991.31 # Real time elapsed on the host -host_tick_rate 2098643273 # Simulator tick rate (ticks/s) +host_inst_rate 779483 # Simulator instruction rate (inst/s) +host_mem_usage 204800 # Number of bytes of host memory used +host_seconds 1910.91 # Real time elapsed on the host +host_tick_rate 1086392421 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489523295 # Number of instructions simulated -sim_seconds 2.080416 # Number of seconds simulated -sim_ticks 2080416155000 # Number of ticks simulated +sim_seconds 2.076001 # Number of seconds simulated +sim_ticks 2076000961000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 402512844 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 21085.814994 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18085.814994 # average ReadReq mshr miss latency @@ -77,14 +77,14 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 449125 # number of replacements system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.205833 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.229973 # Cycle average of tags in use system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 596368000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 567696000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 316420 # number of writebacks -system.cpu.icache.ReadReq_accesses 1489528206 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 1485113012 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 55848.238482 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1489527099 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 1485111905 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 61824000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 1107 # number of ReadReq misses @@ -93,16 +93,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # ms system.cpu.icache.ReadReq_mshr_misses 1107 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1345552.934959 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1341564.503162 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1489528206 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 1485113012 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 55848.238482 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency -system.cpu.icache.demand_hits 1489527099 # number of demand (read+write) hits +system.cpu.icache.demand_hits 1485111905 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 61824000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_misses 1107 # number of demand (read+write) misses @@ -113,11 +113,11 @@ system.cpu.icache.demand_mshr_misses 1107 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1489528206 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 1485113012 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1489527099 # number of overall hits +system.cpu.icache.overall_hits 1485111905 # number of overall hits system.cpu.icache.overall_miss_latency 61824000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_misses 1107 # number of overall misses @@ -130,8 +130,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 118 # number of replacements system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 906.330613 # Cycle average of tags in use -system.cpu.icache.total_refs 1489527099 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 906.413769 # Cycle average of tags in use +system.cpu.icache.total_refs 1485111905 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -204,12 +204,12 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 82905 # number of replacements system.cpu.l2cache.sampled_refs 98339 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16356.207611 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 16358.028924 # Cycle average of tags in use system.cpu.l2cache.total_refs 337181 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 61861 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4160832310 # number of cpu cycles simulated +system.cpu.numCycles 4152001922 # number of cpu cycles simulated system.cpu.num_insts 1489523295 # Number of instructions executed system.cpu.num_refs 569365767 # Number of memory references system.cpu.workload.PROG:num_syscalls 49 # Number of system calls diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout index 1d076eebd..21fdf6d28 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout @@ -26,6 +26,7 @@ Uncompressed data compared correctly Compressing Input Data, level 3 Compressed data 97831 bytes in length Uncompressing Data +info: Increasing stack size by one page. Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Compressing Input Data, level 5 diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout index f6eeaa6d1..1a67dff68 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 23 2009 23:45:19 -M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch -M5 started Feb 23 2009 23:48:10 +M5 compiled Feb 24 2009 01:30:29 +M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch +M5 started Feb 24 2009 01:41:46 M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py long/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -44,4 +44,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2554084828000 because target called exit() +Exiting @ tick 1814744167000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt index f6f018cc6..44628642c 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 751612 # Simulator instruction rate (inst/s) -host_mem_usage 204588 # Number of bytes of host memory used -host_seconds 2154.53 # Real time elapsed on the host -host_tick_rate 1185451424 # Simulator tick rate (ticks/s) +host_inst_rate 759916 # Simulator instruction rate (inst/s) +host_mem_usage 204700 # Number of bytes of host memory used +host_seconds 2130.98 # Real time elapsed on the host +host_tick_rate 851601124 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1619365942 # Number of instructions simulated -sim_seconds 2.554085 # Number of seconds simulated -sim_ticks 2554084828000 # Number of ticks simulated +sim_seconds 1.814744 # Number of seconds simulated +sim_ticks 1814744167000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 418962758 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 21035.291697 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18035.291697 # average ReadReq mshr miss latency @@ -67,61 +67,61 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 439707 # number of replacements system.cpu.dcache.sampled_refs 443803 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.610676 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.900260 # Cycle average of tags in use system.cpu.dcache.total_refs 606705011 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1592465000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 779366000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 308507 # number of writebacks -system.cpu.icache.ReadReq_accesses 1925857355 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 1186516694 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1925856634 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 1186515973 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 40376000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 721 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 38213000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 721 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2671091.031900 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1645653.221914 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1925857355 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 1186516694 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 1925856634 # number of demand (read+write) hits +system.cpu.icache.demand_hits 1186515973 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 40376000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_misses 721 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 38213000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 721 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1925857355 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 1186516694 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1925856634 # number of overall hits +system.cpu.icache.overall_hits 1186515973 # number of overall hits system.cpu.icache.overall_miss_latency 40376000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_misses 721 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 38213000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 721 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 4 # number of replacements system.cpu.icache.sampled_refs 721 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 658.724808 # Cycle average of tags in use -system.cpu.icache.total_refs 1925856634 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 659.165920 # Cycle average of tags in use +system.cpu.icache.total_refs 1186515973 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -194,12 +194,12 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 82097 # number of replacements system.cpu.l2cache.sampled_refs 97587 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16428.009263 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 16488.807758 # Cycle average of tags in use system.cpu.l2cache.total_refs 332264 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 61702 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5108169656 # number of cpu cycles simulated +system.cpu.numCycles 3629488334 # number of cpu cycles simulated system.cpu.num_insts 1619365942 # Number of instructions executed system.cpu.num_refs 607148814 # Number of memory references system.cpu.workload.PROG:num_syscalls 48 # Number of system calls diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout index 380022b15..3aaf04828 100755 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:17:12 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:53:06 -M5 executing on zizzer +M5 compiled Feb 24 2009 01:30:29 +M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch +M5 started Feb 24 2009 01:31:11 +M5 executing on tater command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py long/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -28,4 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 366445521000 because target called exit() +Exiting @ tick 366435406000 because target called exit() diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt index ac46d4baa..61025e455 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1327795 # Simulator instruction rate (inst/s) -host_mem_usage 337424 # Number of bytes of host memory used -host_seconds 183.64 # Real time elapsed on the host -host_tick_rate 1995461602 # Simulator tick rate (ticks/s) +host_inst_rate 712663 # Simulator instruction rate (inst/s) +host_mem_usage 336988 # Number of bytes of host memory used +host_seconds 342.15 # Real time elapsed on the host +host_tick_rate 1070988197 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 243835278 # Number of instructions simulated -sim_seconds 0.366446 # Number of seconds simulated -sim_ticks 366445521000 # Number of ticks simulated +sim_seconds 0.366435 # Number of seconds simulated +sim_ticks 366435406000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 82220434 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 14009.690242 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11009.690242 # average ReadReq mshr miss latency @@ -77,14 +77,14 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 935475 # number of replacements system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3569.547350 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3569.622607 # Cycle average of tags in use system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 134389803000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 134379688000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 94875 # number of writebacks -system.cpu.icache.ReadReq_accesses 244431627 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 244421512 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 55904.761905 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 52904.761905 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 244430745 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 244420630 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 49308000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 882 # number of ReadReq misses @@ -93,16 +93,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # ms system.cpu.icache.ReadReq_mshr_misses 882 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 277132.363946 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 244431627 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 244421512 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 55904.761905 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency -system.cpu.icache.demand_hits 244430745 # number of demand (read+write) hits +system.cpu.icache.demand_hits 244420630 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 49308000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses system.cpu.icache.demand_misses 882 # number of demand (read+write) misses @@ -113,11 +113,11 @@ system.cpu.icache.demand_mshr_misses 882 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 244431627 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 244421512 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55904.761905 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 244430745 # number of overall hits +system.cpu.icache.overall_hits 244420630 # number of overall hits system.cpu.icache.overall_miss_latency 49308000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses system.cpu.icache.overall_misses 882 # number of overall misses @@ -130,8 +130,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 25 # number of replacements system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 726.233997 # Cycle average of tags in use -system.cpu.icache.total_refs 244430745 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 726.242454 # Cycle average of tags in use +system.cpu.icache.total_refs 244420630 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -204,12 +204,12 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 891 # number of replacements system.cpu.l2cache.sampled_refs 15559 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 8958.603097 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 8958.837724 # Cycle average of tags in use system.cpu.l2cache.total_refs 802210 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 41 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 732891042 # number of cpu cycles simulated +system.cpu.numCycles 732870812 # number of cpu cycles simulated system.cpu.num_insts 243835278 # Number of instructions executed system.cpu.num_refs 105711442 # Number of memory references system.cpu.workload.PROG:num_syscalls 443 # Number of system calls diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout index ea464f620..160928f1d 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 23 2009 23:45:19 -M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch -M5 started Feb 23 2009 23:48:10 +M5 compiled Feb 24 2009 01:30:29 +M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch +M5 started Feb 24 2009 01:36:40 M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py long/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -28,4 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 493318720000 because target called exit() +Exiting @ tick 381620498000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt index f7746cc78..cc9d82b6a 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 472092 # Simulator instruction rate (inst/s) -host_mem_usage 339120 # Number of bytes of host memory used -host_seconds 571.26 # Real time elapsed on the host -host_tick_rate 863564130 # Simulator tick rate (ticks/s) +host_inst_rate 587866 # Simulator instruction rate (inst/s) +host_mem_usage 339232 # Number of bytes of host memory used +host_seconds 458.76 # Real time elapsed on the host +host_tick_rate 831860032 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 269686773 # Number of instructions simulated -sim_seconds 0.493319 # Number of seconds simulated -sim_ticks 493318720000 # Number of ticks simulated +sim_seconds 0.381620 # Number of seconds simulated +sim_ticks 381620498000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 90779443 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 15899.099984 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12899.099984 # average ReadReq mshr miss latency @@ -67,61 +67,61 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 2049944 # number of replacements system.cpu.dcache.sampled_refs 2054040 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4078.561270 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4079.427520 # Cycle average of tags in use system.cpu.dcache.total_refs 120165153 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 165886080000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 127225609000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 229129 # number of writebacks -system.cpu.icache.ReadReq_accesses 329394385 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 217696163 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 329393578 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 217695356 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 45192000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 807 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 42771000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 807 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 408170.480793 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 269758.805452 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 329394385 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 217696163 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 329393578 # number of demand (read+write) hits +system.cpu.icache.demand_hits 217695356 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 45192000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses system.cpu.icache.demand_misses 807 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 42771000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 807 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 329394385 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 217696163 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 329393578 # number of overall hits +system.cpu.icache.overall_hits 217695356 # number of overall hits system.cpu.icache.overall_miss_latency 45192000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses system.cpu.icache.overall_misses 807 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 42771000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 807 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.sampled_refs 807 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 665.896527 # Cycle average of tags in use -system.cpu.icache.total_refs 329393578 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 666.511426 # Cycle average of tags in use +system.cpu.icache.total_refs 217695356 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -194,12 +194,12 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 108885 # number of replacements system.cpu.l2cache.sampled_refs 132827 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18017.047263 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 18002.978067 # Cycle average of tags in use system.cpu.l2cache.total_refs 1816837 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 70892 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 986637440 # number of cpu cycles simulated +system.cpu.numCycles 763240996 # number of cpu cycles simulated system.cpu.num_insts 269686773 # Number of instructions executed system.cpu.num_refs 122219131 # Number of memory references system.cpu.workload.PROG:num_syscalls 444 # Number of system calls diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout index bc32d8a8e..e9b88174e 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 23 2009 23:45:19 -M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch -M5 started Feb 23 2009 23:48:10 +M5 compiled Feb 24 2009 01:30:29 +M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch +M5 started Feb 24 2009 01:46:46 M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py long/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -74,4 +74,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 2390957741000 because target called exit() +Exiting @ tick 1722352498000 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt index c30384fe4..422faa1c9 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 732305 # Simulator instruction rate (inst/s) -host_mem_usage 208264 # Number of bytes of host memory used -host_seconds 2042.16 # Real time elapsed on the host -host_tick_rate 1170799737 # Simulator tick rate (ticks/s) +host_inst_rate 782704 # Simulator instruction rate (inst/s) +host_mem_usage 208376 # Number of bytes of host memory used +host_seconds 1910.66 # Real time elapsed on the host +host_tick_rate 901442913 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1495482356 # Number of instructions simulated -sim_seconds 2.390958 # Number of seconds simulated -sim_ticks 2390957741000 # Number of ticks simulated +sim_seconds 1.722352 # Number of seconds simulated +sim_ticks 1722352498000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 384102182 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 24147.662775 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21147.661617 # average ReadReq mshr miss latency @@ -67,61 +67,61 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 2513875 # number of replacements system.cpu.dcache.sampled_refs 2517971 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4086.149487 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4086.831321 # Cycle average of tags in use system.cpu.dcache.total_refs 530744411 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12270471000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 8217698000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 1463913 # number of writebacks -system.cpu.icache.ReadReq_accesses 1736952307 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 1068347064 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 48415.215073 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 45415.215073 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1736949494 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 1068344251 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 136192000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 2813 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 127753000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 2813 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 617472.269463 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 379788.215784 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1736952307 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 1068347064 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 48415.215073 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency -system.cpu.icache.demand_hits 1736949494 # number of demand (read+write) hits +system.cpu.icache.demand_hits 1068344251 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 136192000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses system.cpu.icache.demand_misses 2813 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 127753000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 2813 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1736952307 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 1068347064 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 48415.215073 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 45415.215073 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1736949494 # number of overall hits +system.cpu.icache.overall_hits 1068344251 # number of overall hits system.cpu.icache.overall_miss_latency 136192000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses system.cpu.icache.overall_misses 2813 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 127753000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 2813 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 1253 # number of replacements system.cpu.icache.sampled_refs 2813 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 873.828248 # Cycle average of tags in use -system.cpu.icache.total_refs 1736949494 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 886.488028 # Cycle average of tags in use +system.cpu.icache.total_refs 1068344251 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -194,12 +194,12 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 663512 # number of replacements system.cpu.l2cache.sampled_refs 679920 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 17171.450430 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 17216.029598 # Cycle average of tags in use system.cpu.l2cache.total_refs 2330814 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 1312958337000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 921771430000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 481430 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4781915482 # number of cpu cycles simulated +system.cpu.numCycles 3444704996 # number of cpu cycles simulated system.cpu.num_insts 1495482356 # Number of instructions executed system.cpu.num_refs 533262337 # Number of memory references system.cpu.workload.PROG:num_syscalls 551 # Number of system calls diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout index 22ae99950..d6b904f84 100755 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:17:12 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:54:04 -M5 executing on zizzer +M5 compiled Feb 24 2009 01:30:29 +M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch +M5 started Feb 24 2009 01:30:32 +M5 executing on tater command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py long/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 205116920000 because target called exit() +Exiting @ tick 203376692000 because target called exit() diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 0cca434c3..3d50b13ca 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1934138 # Simulator instruction rate (inst/s) -host_mem_usage 214132 # Number of bytes of host memory used -host_seconds 70.39 # Real time elapsed on the host -host_tick_rate 2914099932 # Simulator tick rate (ticks/s) +host_inst_rate 683746 # Simulator instruction rate (inst/s) +host_mem_usage 213692 # Number of bytes of host memory used +host_seconds 199.11 # Real time elapsed on the host +host_tick_rate 1021439068 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136139203 # Number of instructions simulated -sim_seconds 0.205117 # Number of seconds simulated -sim_ticks 205116920000 # Number of ticks simulated +sim_seconds 0.203377 # Number of seconds simulated +sim_ticks 203376692000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 38620.848810 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35620.848810 # average ReadReq mshr miss latency @@ -77,62 +77,62 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 146582 # number of replacements system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4087.433110 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4087.609698 # Cycle average of tags in use system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 821750000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 778280000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 107271 # number of writebacks -system.cpu.icache.ReadReq_accesses 136293812 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 134553584 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 16936.029600 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 13936.029600 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 136106788 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 134366560 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 3167444000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.001372 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.001390 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 2606372000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.001372 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 727.750385 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 718.445547 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 136293812 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 134553584 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 16936.029600 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency -system.cpu.icache.demand_hits 136106788 # number of demand (read+write) hits +system.cpu.icache.demand_hits 134366560 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 3167444000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.001372 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.001390 # miss rate for demand accesses system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 2606372000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.001372 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.001390 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 136293812 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 134553584 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 16936.029600 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 136106788 # number of overall hits +system.cpu.icache.overall_hits 134366560 # number of overall hits system.cpu.icache.overall_miss_latency 3167444000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.001372 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.001390 # miss rate for overall accesses system.cpu.icache.overall_misses 187024 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 2606372000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.001372 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.001390 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 184976 # number of replacements system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 2004.068304 # Cycle average of tags in use -system.cpu.icache.total_refs 136106788 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 146097762000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 2004.715107 # Cycle average of tags in use +system.cpu.icache.total_refs 134366560 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 144812317000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadExReq_accesses 105179 # number of ReadExReq accesses(hits+misses) @@ -204,12 +204,12 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 120486 # number of replacements system.cpu.l2cache.sampled_refs 139196 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 19311.746813 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 19319.557750 # Cycle average of tags in use system.cpu.l2cache.total_refs 199586 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 87413 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 410233840 # number of cpu cycles simulated +system.cpu.numCycles 406753384 # number of cpu cycles simulated system.cpu.num_insts 136139203 # Number of instructions executed system.cpu.num_refs 58160249 # Number of memory references system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout index 3f9a5b324..bdea83ec4 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 23 2009 23:45:19 -M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch -M5 started Feb 23 2009 23:48:10 +M5 compiled Feb 24 2009 01:30:29 +M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch +M5 started Feb 24 2009 01:30:32 M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py long/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -29,4 +29,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 7633159262000 because target called exit() +Exiting @ tick 5988064029000 because target called exit() diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt index bf04eb747..55231f8a8 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 953941 # Simulator instruction rate (inst/s) -host_mem_usage 204484 # Number of bytes of host memory used -host_seconds 4877.84 # Real time elapsed on the host -host_tick_rate 1564863626 # Simulator tick rate (ticks/s) +host_inst_rate 929786 # Simulator instruction rate (inst/s) +host_mem_usage 204596 # Number of bytes of host memory used +host_seconds 5004.56 # Real time elapsed on the host +host_tick_rate 1196520405 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4653176258 # Number of instructions simulated -sim_seconds 7.633159 # Number of seconds simulated -sim_ticks 7633159262000 # Number of ticks simulated +sim_seconds 5.988064 # Number of seconds simulated +sim_ticks 5988064029000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1239184742 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 25017.713978 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22017.713978 # average ReadReq mshr miss latency @@ -67,14 +67,14 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 9108982 # number of replacements system.cpu.dcache.sampled_refs 9113078 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4084.359780 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4084.778559 # Cycle average of tags in use system.cpu.dcache.total_refs 1668600000 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 78018940000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 58863922000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2244013 # number of writebacks -system.cpu.icache.ReadReq_accesses 5658328114 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 4013232881 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5658327439 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 4013232206 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses @@ -83,16 +83,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # ms system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 8382707.317037 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5945529.194074 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5658328114 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 4013232881 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 5658327439 # number of demand (read+write) hits +system.cpu.icache.demand_hits 4013232206 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses system.cpu.icache.demand_misses 675 # number of demand (read+write) misses @@ -103,11 +103,11 @@ system.cpu.icache.demand_mshr_misses 675 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 5658328114 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 4013232881 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5658327439 # number of overall hits +system.cpu.icache.overall_hits 4013232206 # number of overall hits system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses system.cpu.icache.overall_misses 675 # number of overall misses @@ -120,8 +120,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 10 # number of replacements system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 555.303019 # Cycle average of tags in use -system.cpu.icache.total_refs 5658327439 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 555.573306 # Cycle average of tags in use +system.cpu.icache.total_refs 4013232206 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -194,12 +194,12 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 2772128 # number of replacements system.cpu.l2cache.sampled_refs 2798338 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 25736.997763 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 25742.940427 # Cycle average of tags in use system.cpu.l2cache.total_refs 6663406 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 6030002809000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 4737814303000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 1199171 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 15266318524 # number of cpu cycles simulated +system.cpu.numCycles 11976128058 # number of cpu cycles simulated system.cpu.num_insts 4653176258 # Number of instructions executed system.cpu.num_refs 1677713078 # Number of memory references system.cpu.workload.PROG:num_syscalls 46 # Number of system calls diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout index 5a804eb57..b27d83682 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout @@ -5,11 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:17:12 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:56:10 -M5 executing on zizzer +M5 compiled Feb 24 2009 01:30:29 +M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch +M5 started Feb 24 2009 01:33:08 +M5 executing on tater command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re tests/run.py long/70.twolf/sparc/linux/simple-timing +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav +Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -26,4 +28,4 @@ Authors: Carl Sechen, Bill Swartz 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 info: Increasing stack size by one page. -122 123 124 Exiting @ tick 270578573000 because target called exit() +122 123 124 Exiting @ tick 270578335000 because target called exit() diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 571ff6af8..f73a0dcbf 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1319897 # Simulator instruction rate (inst/s) -host_mem_usage 209760 # Number of bytes of host memory used -host_seconds 146.56 # Real time elapsed on the host -host_tick_rate 1846186883 # Simulator tick rate (ticks/s) +host_inst_rate 732316 # Simulator instruction rate (inst/s) +host_mem_usage 209324 # Number of bytes of host memory used +host_seconds 264.15 # Real time elapsed on the host +host_tick_rate 1024317022 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193444769 # Number of instructions simulated -sim_seconds 0.270579 # Number of seconds simulated -sim_ticks 270578573000 # Number of ticks simulated +sim_seconds 0.270578 # Number of seconds simulated +sim_ticks 270578335000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 57735069 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -77,14 +77,14 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 2 # number of replacements system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1237.193452 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1237.193190 # Cycle average of tags in use system.cpu.dcache.total_refs 76732338 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2 # number of writebacks -system.cpu.icache.ReadReq_accesses 193445787 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 193445549 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 26294.433594 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 23294.433594 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 193433499 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 193433261 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 323106000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000064 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 12288 # number of ReadReq misses @@ -93,16 +93,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # ms system.cpu.icache.ReadReq_mshr_misses 12288 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 15741.658447 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 15741.639079 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 193445787 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 193445549 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 26294.433594 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency -system.cpu.icache.demand_hits 193433499 # number of demand (read+write) hits +system.cpu.icache.demand_hits 193433261 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 323106000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000064 # miss rate for demand accesses system.cpu.icache.demand_misses 12288 # number of demand (read+write) misses @@ -113,11 +113,11 @@ system.cpu.icache.demand_mshr_misses 12288 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 193445787 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 193445549 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 26294.433594 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 193433499 # number of overall hits +system.cpu.icache.overall_hits 193433261 # number of overall hits system.cpu.icache.overall_miss_latency 323106000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000064 # miss rate for overall accesses system.cpu.icache.overall_misses 12288 # number of overall misses @@ -130,8 +130,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 10362 # number of replacements system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1591.566927 # Cycle average of tags in use -system.cpu.icache.total_refs 193433499 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1591.566647 # Cycle average of tags in use +system.cpu.icache.total_refs 193433261 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -204,12 +204,12 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 4072 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2657.329033 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2657.327979 # Cycle average of tags in use system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 541157146 # number of cpu cycles simulated +system.cpu.numCycles 541156670 # number of cpu cycles simulated system.cpu.num_insts 193444769 # Number of instructions executed system.cpu.num_refs 76733959 # Number of memory references system.cpu.workload.PROG:num_syscalls 401 # Number of system calls diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout index 4e1b45a86..2a43627aa 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 23 2009 23:45:19 -M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch -M5 started Feb 23 2009 23:57:42 +M5 compiled Feb 24 2009 01:30:29 +M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch +M5 started Feb 24 2009 01:58:47 M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py long/70.twolf/x86/linux/simple-timing Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sav @@ -29,4 +29,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 337469588000 because target called exit() +122 123 124 Exiting @ tick 250945484000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt index a85a5c18f..3d7cbb069 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 565225 # Simulator instruction rate (inst/s) -host_mem_usage 211860 # Number of bytes of host memory used -host_seconds 386.74 # Real time elapsed on the host -host_tick_rate 872598896 # Simulator tick rate (ticks/s) +host_inst_rate 660588 # Simulator instruction rate (inst/s) +host_mem_usage 211972 # Number of bytes of host memory used +host_seconds 330.91 # Real time elapsed on the host +host_tick_rate 758349031 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 218595300 # Number of instructions simulated -sim_seconds 0.337470 # Number of seconds simulated -sim_ticks 337469588000 # Number of ticks simulated +sim_seconds 0.250945 # Number of seconds simulated +sim_ticks 250945484000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 56649600 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 55873.040752 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52873.040752 # average ReadReq mshr miss latency @@ -67,61 +67,61 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 27 # number of replacements system.cpu.dcache.sampled_refs 1894 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1362.541257 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1362.582924 # Cycle average of tags in use system.cpu.dcache.total_refs 77163435 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2 # number of writebacks -system.cpu.icache.ReadReq_accesses 260018470 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 173494366 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 39408.800341 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 36408.693799 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 260013777 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 173489673 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 184945500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 4693 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 170866000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000018 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 4693 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 55404.597699 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 36967.754741 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 260018470 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 173494366 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 39408.800341 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency -system.cpu.icache.demand_hits 260013777 # number of demand (read+write) hits +system.cpu.icache.demand_hits 173489673 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 184945500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.000027 # miss rate for demand accesses system.cpu.icache.demand_misses 4693 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 170866000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000018 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 4693 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 260018470 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 173494366 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 39408.800341 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 260013777 # number of overall hits +system.cpu.icache.overall_hits 173489673 # number of overall hits system.cpu.icache.overall_miss_latency 184945500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses system.cpu.icache.overall_misses 4693 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 170866000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000018 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 4693 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 2835 # number of replacements system.cpu.icache.sampled_refs 4693 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1453.991353 # Cycle average of tags in use -system.cpu.icache.total_refs 260013777 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1454.285546 # Cycle average of tags in use +system.cpu.icache.total_refs 173489673 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -194,12 +194,12 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 3133 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2031.720804 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 2032.147267 # Cycle average of tags in use system.cpu.l2cache.total_refs 1855 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 674939176 # number of cpu cycles simulated +system.cpu.numCycles 501890968 # number of cpu cycles simulated system.cpu.num_insts 218595300 # Number of instructions executed system.cpu.num_refs 77165298 # Number of memory references system.cpu.workload.PROG:num_syscalls 400 # Number of system calls diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout index 03584f0f8..a84f40e19 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 23 2009 23:45:19 -M5 revision 046e9580158a+ 5888+ default qtip tip delayedmissstats.patch -M5 started Feb 23 2009 23:59:10 +M5 compiled Feb 24 2009 01:30:29 +M5 revision 652016638b82 5907 default qtip tip nofetchonmicrostats.patch +M5 started Feb 24 2009 01:37:33 M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py quick/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 33815000 because target called exit() +Exiting @ tick 29717000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt index d6a4a1186..b8a17302a 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 184291 # Simulator instruction rate (inst/s) -host_mem_usage 200284 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 654707739 # Simulator tick rate (ticks/s) +host_inst_rate 139542 # Simulator instruction rate (inst/s) +host_mem_usage 200396 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 436046426 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9484 # Number of instructions simulated -sim_seconds 0.000034 # Number of seconds simulated -sim_ticks 33815000 # Number of ticks simulated +sim_seconds 0.000030 # Number of seconds simulated +sim_ticks 29717000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1053 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency @@ -67,61 +67,61 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 133 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 81.615734 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 80.867418 # Cycle average of tags in use system.cpu.dcache.total_refs 1854 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_accesses 10971 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 6873 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 10743 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 6645 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.020782 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate 0.033173 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.020782 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate 0.033173 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 47.118421 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 29.144737 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 10971 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 6873 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency -system.cpu.icache.demand_hits 10743 # number of demand (read+write) hits +system.cpu.icache.demand_hits 6645 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.020782 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate 0.033173 # miss rate for demand accesses system.cpu.icache.demand_misses 228 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 12042000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.020782 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate 0.033173 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 228 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 10971 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 6873 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 10743 # number of overall hits +system.cpu.icache.overall_hits 6645 # number of overall hits system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.020782 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate 0.033173 # miss rate for overall accesses system.cpu.icache.overall_misses 228 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 12042000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.020782 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate 0.033173 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 107.556413 # Cycle average of tags in use -system.cpu.icache.total_refs 10743 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 106.639571 # Cycle average of tags in use +system.cpu.icache.total_refs 6645 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -192,12 +192,12 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 262 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 129.158632 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 128.121989 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 67630 # number of cpu cycles simulated +system.cpu.numCycles 59434 # number of cpu cycles simulated system.cpu.num_insts 9484 # Number of instructions executed system.cpu.num_refs 1987 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls |