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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-02-27 09:25:02 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-02-27 09:25:02 -0800 |
| commit | 1d18eb9043d5d2e69d3885be8dd59695ad80a92d (patch) | |
| tree | 577e8cfd5779decd3dad1e9d9e3cb887182914ad | |
| parent | 79bc1b37400ffc4aacfbf19b64aed4c7d568c941 (diff) | |
| download | gem5-1d18eb9043d5d2e69d3885be8dd59695ad80a92d.tar.xz | |
X86: Make instructions that use intseg preserve all 8 bytes of their addresses.
| -rw-r--r-- | src/arch/x86/isa/insts/general_purpose/input_output/general_io.py | 8 | ||||
| -rw-r--r-- | src/arch/x86/isa/insts/system/msrs.py | 4 |
2 files changed, 6 insertions, 6 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py index 924bfcb6e..4e3c9b316 100644 --- a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py +++ b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py @@ -85,22 +85,22 @@ microcode = ''' def macroop IN_R_I { .adjust_imm trimImm(8) limm t1, imm, dataSize=asz - ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=4 + ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8 }; def macroop IN_R_R { zexti t2, regm, 15, dataSize=8 - ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=4 + ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8 }; def macroop OUT_I_R { .adjust_imm trimImm(8) limm t1, imm, dataSize=8 - st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=4 + st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8 }; def macroop OUT_R_R { zexti t2, reg, 15, dataSize=8 - st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=4 + st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8 }; ''' diff --git a/src/arch/x86/isa/insts/system/msrs.py b/src/arch/x86/isa/insts/system/msrs.py index f3c867398..7f283c8c1 100644 --- a/src/arch/x86/isa/insts/system/msrs.py +++ b/src/arch/x86/isa/insts/system/msrs.py @@ -85,7 +85,7 @@ microcode = ''' def macroop RDMSR { ld t2, intseg, [8, rcx, t0], "IntAddrPrefixMSR << 3", \ - dataSize=8, addressSize=4 + dataSize=8, addressSize=8 mov rax, rax, t2, dataSize=4 srli t2, t2, 32, dataSize=8 mov rdx, rdx, t2, dataSize=4 @@ -97,7 +97,7 @@ def macroop WRMSR slli t3, rdx, 32, dataSize=8 or t2, t2, t3, dataSize=8 st t2, intseg, [8, rcx, t0], "IntAddrPrefixMSR << 3", \ - dataSize=8, addressSize=4 + dataSize=8, addressSize=8 }; def macroop RDTSC |