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| author | Ron Dreslinski <rdreslin@umich.edu> | 2004-03-01 21:17:28 -0500 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2004-03-01 21:17:28 -0500 |
| commit | 3a0db71f02a4aa96f8ff47a02debb78a0d53b80d (patch) | |
| tree | 6e7741f5d14940fa37460298255483a7bef705d4 | |
| parent | e943bedeaa407af06bf406e92d854137d7dfc8cd (diff) | |
| download | gem5-3a0db71f02a4aa96f8ff47a02debb78a0d53b80d.tar.xz | |
Add support for two buses to the DMA, allows header splitting
The two busses are labeled header/payload. The header_size
designates the number of cache blocks to send on the header bus.
--HG--
extra : convert_revision : 930411052d2183311f9be7a10087c77552a35b37
0 files changed, 0 insertions, 0 deletions