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author | Ali Saidi <saidi@eecs.umich.edu> | 2006-06-11 17:21:02 -0400 |
---|---|---|
committer | Ali Saidi <saidi@eecs.umich.edu> | 2006-06-11 17:21:02 -0400 |
commit | 4ab8e881edecd47ae3f2ba5fda345f7ff9788870 (patch) | |
tree | 2d5ad596249ebcee7481f4dd06179aef95207bd5 | |
parent | bb58e4b85163f263ebf5ea54fee5dba0109eb88c (diff) | |
download | gem5-4ab8e881edecd47ae3f2ba5fda345f7ff9788870.tar.xz |
Fix compiling for SPARC_SE:
- change include from exec_context.hh -> threadcontext.hh
- g++ 4.0.3 complaint about broken code (which it was).
- bad merge thread_context -> exec_context
src/arch/sparc/isa/includes.isa:
Fix SPARC_SE for exec_context->thread_context switch
src/arch/sparc/regfile.hh:
fix g++ 4.0.3 complaint about broken code (which it was).
src/cpu/thread_context.hh:
fix bad merge
--HG--
extra : convert_revision : f5bab822d5c25177756e9890e143b0ad8d704201
-rw-r--r-- | src/arch/sparc/isa/includes.isa | 2 | ||||
-rw-r--r-- | src/arch/sparc/regfile.hh | 25 | ||||
-rw-r--r-- | src/cpu/thread_context.hh | 2 |
3 files changed, 20 insertions, 9 deletions
diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa index 762de243a..40afb3722 100644 --- a/src/arch/sparc/isa/includes.isa +++ b/src/arch/sparc/isa/includes.isa @@ -48,7 +48,7 @@ output header {{ output decoder {{ #include "base/cprintf.hh" #include "base/loader/symtab.hh" -#include "cpu/exec_context.hh" // for Jump::branchTarget() +#include "cpu/thread_context.hh" // for Jump::branchTarget() #include <math.h> #if defined(linux) diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh index 760edc41e..cbeb3c7b9 100644 --- a/src/arch/sparc/regfile.hh +++ b/src/arch/sparc/regfile.hh @@ -244,17 +244,22 @@ namespace SparcISA //In each of these cases, we have to copy the value into a temporary //variable. This is because we may otherwise try to access an //unaligned portion of memory. + + uint32_t result32; + uint64_t result64; switch(width) { case SingleWidth: - uint32_t result32 = gtoh((uint32_t)val); + result32 = gtoh((uint32_t)val); memcpy(regSpace + 4 * floatReg, &result32, width); + break; case DoubleWidth: - uint64_t result64 = gtoh((uint64_t)val); + result64 = gtoh((uint64_t)val); memcpy(regSpace + 4 * floatReg, &result64, width); + break; case QuadWidth: - uint64_t result128 = gtoh((uint64_t)val); - memcpy(regSpace + 4 * floatReg, &result128, width); + panic("Quad width FP not implemented."); + break; default: panic("Attempted to read a %d bit floating point register!", width); } @@ -266,17 +271,21 @@ namespace SparcISA //In each of these cases, we have to copy the value into a temporary //variable. This is because we may otherwise try to access an //unaligned portion of memory. + uint32_t result32; + uint64_t result64; switch(width) { case SingleWidth: - uint32_t result32 = gtoh((uint32_t)val); + result32 = gtoh((uint32_t)val); memcpy(regSpace + 4 * floatReg, &result32, width); + break; case DoubleWidth: - uint64_t result64 = gtoh((uint64_t)val); + result64 = gtoh((uint64_t)val); memcpy(regSpace + 4 * floatReg, &result64, width); + break; case QuadWidth: - uint64_t result128 = gtoh((uint64_t)val); - memcpy(regSpace + 4 * floatReg, &result128, width); + panic("Quad width FP not implemented."); + break; default: panic("Attempted to read a %d bit floating point register!", width); } diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index e3bb7d9c3..48c8fa28d 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -245,6 +245,7 @@ class ThreadContext virtual void setSyscallReturn(SyscallReturn return_value) = 0; + virtual void syscall(int64_t callnum) = 0; // Same with st cond failures. virtual Counter readFuncExeInst() = 0; @@ -431,6 +432,7 @@ class ProxyThreadContext : public ThreadContext void setSyscallReturn(SyscallReturn return_value) { actualTC->setSyscallReturn(return_value); } + void syscall(int64_t callnum) { actualTC->syscall(callnum); } Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } #endif |