diff options
| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-10-31 14:24:26 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-11-07 15:22:43 +0000 |
| commit | 4e02b9219d18fba0923b6624b12cf283bd238216 (patch) | |
| tree | ba5973029424c95f4c617d0e6e12c8bda86cef72 | |
| parent | 351c7ee8533a09a09e2bf17a3c8d2f349af06448 (diff) | |
| download | gem5-4e02b9219d18fba0923b6624b12cf283bd238216.tar.xz | |
arch-arm: Remove MISCREG commented numbers
Having an enum number might be useful in case we wanted to know how many
miscregs we have, but on the other hand it makes it tedious to update
the register list, since every commented number must be bumped. This
patch is removing the comments holding the MISCREG numbers
Change-Id: Ic5aba93885e4b8d6cb3bd6a4c49900b9e5474276
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13996
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
| -rw-r--r-- | src/arch/arm/miscregs.hh | 1214 |
1 files changed, 607 insertions, 607 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index ab3fc8f7f..dcaaa7fe3 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -55,634 +55,634 @@ class ThreadContext; namespace ArmISA { enum MiscRegIndex { - MISCREG_CPSR = 0, // 0 - MISCREG_SPSR, // 1 - MISCREG_SPSR_FIQ, // 2 - MISCREG_SPSR_IRQ, // 3 - MISCREG_SPSR_SVC, // 4 - MISCREG_SPSR_MON, // 5 - MISCREG_SPSR_ABT, // 6 - MISCREG_SPSR_HYP, // 7 - MISCREG_SPSR_UND, // 8 - MISCREG_ELR_HYP, // 9 - MISCREG_FPSID, // 10 - MISCREG_FPSCR, // 11 - MISCREG_MVFR1, // 12 - MISCREG_MVFR0, // 13 - MISCREG_FPEXC, // 14 + MISCREG_CPSR = 0, + MISCREG_SPSR, + MISCREG_SPSR_FIQ, + MISCREG_SPSR_IRQ, + MISCREG_SPSR_SVC, + MISCREG_SPSR_MON, + MISCREG_SPSR_ABT, + MISCREG_SPSR_HYP, + MISCREG_SPSR_UND, + MISCREG_ELR_HYP, + MISCREG_FPSID, + MISCREG_FPSCR, + MISCREG_MVFR1, + MISCREG_MVFR0, + MISCREG_FPEXC, // Helper registers - MISCREG_CPSR_MODE, // 15 - MISCREG_CPSR_Q, // 16 - MISCREG_FPSCR_EXC, // 17 - MISCREG_FPSCR_QC, // 18 - MISCREG_LOCKADDR, // 19 - MISCREG_LOCKFLAG, // 20 - MISCREG_PRRR_MAIR0, // 21 - MISCREG_PRRR_MAIR0_NS, // 22 - MISCREG_PRRR_MAIR0_S, // 23 - MISCREG_NMRR_MAIR1, // 24 - MISCREG_NMRR_MAIR1_NS, // 25 - MISCREG_NMRR_MAIR1_S, // 26 - MISCREG_PMXEVTYPER_PMCCFILTR, // 27 - MISCREG_SCTLR_RST, // 28 - MISCREG_SEV_MAILBOX, // 29 + MISCREG_CPSR_MODE, + MISCREG_CPSR_Q, + MISCREG_FPSCR_EXC, + MISCREG_FPSCR_QC, + MISCREG_LOCKADDR, + MISCREG_LOCKFLAG, + MISCREG_PRRR_MAIR0, + MISCREG_PRRR_MAIR0_NS, + MISCREG_PRRR_MAIR0_S, + MISCREG_NMRR_MAIR1, + MISCREG_NMRR_MAIR1_NS, + MISCREG_NMRR_MAIR1_S, + MISCREG_PMXEVTYPER_PMCCFILTR, + MISCREG_SCTLR_RST, + MISCREG_SEV_MAILBOX, // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control) - MISCREG_DBGDIDR, // 30 - MISCREG_DBGDSCRint, // 31 - MISCREG_DBGDCCINT, // 32 - MISCREG_DBGDTRTXint, // 33 - MISCREG_DBGDTRRXint, // 34 - MISCREG_DBGWFAR, // 35 - MISCREG_DBGVCR, // 36 - MISCREG_DBGDTRRXext, // 37 - MISCREG_DBGDSCRext, // 38 - MISCREG_DBGDTRTXext, // 39 - MISCREG_DBGOSECCR, // 40 - MISCREG_DBGBVR0, // 41 - MISCREG_DBGBVR1, // 42 - MISCREG_DBGBVR2, // 43 - MISCREG_DBGBVR3, // 44 - MISCREG_DBGBVR4, // 45 - MISCREG_DBGBVR5, // 46 - MISCREG_DBGBCR0, // 47 - MISCREG_DBGBCR1, // 48 - MISCREG_DBGBCR2, // 49 - MISCREG_DBGBCR3, // 50 - MISCREG_DBGBCR4, // 51 - MISCREG_DBGBCR5, // 52 - MISCREG_DBGWVR0, // 53 - MISCREG_DBGWVR1, // 54 - MISCREG_DBGWVR2, // 55 - MISCREG_DBGWVR3, // 56 - MISCREG_DBGWCR0, // 57 - MISCREG_DBGWCR1, // 58 - MISCREG_DBGWCR2, // 59 - MISCREG_DBGWCR3, // 60 - MISCREG_DBGDRAR, // 61 - MISCREG_DBGBXVR4, // 62 - MISCREG_DBGBXVR5, // 63 - MISCREG_DBGOSLAR, // 64 - MISCREG_DBGOSLSR, // 65 - MISCREG_DBGOSDLR, // 66 - MISCREG_DBGPRCR, // 67 - MISCREG_DBGDSAR, // 68 - MISCREG_DBGCLAIMSET, // 69 - MISCREG_DBGCLAIMCLR, // 70 - MISCREG_DBGAUTHSTATUS, // 71 - MISCREG_DBGDEVID2, // 72 - MISCREG_DBGDEVID1, // 73 - MISCREG_DBGDEVID0, // 74 - MISCREG_TEECR, // 75, not in ARM DDI 0487A.b+ - MISCREG_JIDR, // 76 - MISCREG_TEEHBR, // 77, not in ARM DDI 0487A.b+ - MISCREG_JOSCR, // 78 - MISCREG_JMCR, // 79 + MISCREG_DBGDIDR, + MISCREG_DBGDSCRint, + MISCREG_DBGDCCINT, + MISCREG_DBGDTRTXint, + MISCREG_DBGDTRRXint, + MISCREG_DBGWFAR, + MISCREG_DBGVCR, + MISCREG_DBGDTRRXext, + MISCREG_DBGDSCRext, + MISCREG_DBGDTRTXext, + MISCREG_DBGOSECCR, + MISCREG_DBGBVR0, + MISCREG_DBGBVR1, + MISCREG_DBGBVR2, + MISCREG_DBGBVR3, + MISCREG_DBGBVR4, + MISCREG_DBGBVR5, + MISCREG_DBGBCR0, + MISCREG_DBGBCR1, + MISCREG_DBGBCR2, + MISCREG_DBGBCR3, + MISCREG_DBGBCR4, + MISCREG_DBGBCR5, + MISCREG_DBGWVR0, + MISCREG_DBGWVR1, + MISCREG_DBGWVR2, + MISCREG_DBGWVR3, + MISCREG_DBGWCR0, + MISCREG_DBGWCR1, + MISCREG_DBGWCR2, + MISCREG_DBGWCR3, + MISCREG_DBGDRAR, + MISCREG_DBGBXVR4, + MISCREG_DBGBXVR5, + MISCREG_DBGOSLAR, + MISCREG_DBGOSLSR, + MISCREG_DBGOSDLR, + MISCREG_DBGPRCR, + MISCREG_DBGDSAR, + MISCREG_DBGCLAIMSET, + MISCREG_DBGCLAIMCLR, + MISCREG_DBGAUTHSTATUS, + MISCREG_DBGDEVID2, + MISCREG_DBGDEVID1, + MISCREG_DBGDEVID0, + MISCREG_TEECR, // not in ARM DDI 0487A.b+ + MISCREG_JIDR, + MISCREG_TEEHBR, // not in ARM DDI 0487A.b+ + MISCREG_JOSCR, + MISCREG_JMCR, // AArch32 CP15 registers (system control) - MISCREG_MIDR, // 80 - MISCREG_CTR, // 81 - MISCREG_TCMTR, // 82 - MISCREG_TLBTR, // 83 - MISCREG_MPIDR, // 84 - MISCREG_REVIDR, // 85 - MISCREG_ID_PFR0, // 86 - MISCREG_ID_PFR1, // 87 - MISCREG_ID_DFR0, // 88 - MISCREG_ID_AFR0, // 89 - MISCREG_ID_MMFR0, // 90 - MISCREG_ID_MMFR1, // 91 - MISCREG_ID_MMFR2, // 92 - MISCREG_ID_MMFR3, // 93 - MISCREG_ID_ISAR0, // 94 - MISCREG_ID_ISAR1, // 95 - MISCREG_ID_ISAR2, // 96 - MISCREG_ID_ISAR3, // 97 - MISCREG_ID_ISAR4, // 98 - MISCREG_ID_ISAR5, // 99 - MISCREG_CCSIDR, // 100 - MISCREG_CLIDR, // 101 - MISCREG_AIDR, // 102 - MISCREG_CSSELR, // 103 - MISCREG_CSSELR_NS, // 104 - MISCREG_CSSELR_S, // 105 - MISCREG_VPIDR, // 106 - MISCREG_VMPIDR, // 107 - MISCREG_SCTLR, // 108 - MISCREG_SCTLR_NS, // 109 - MISCREG_SCTLR_S, // 110 - MISCREG_ACTLR, // 111 - MISCREG_ACTLR_NS, // 112 - MISCREG_ACTLR_S, // 113 - MISCREG_CPACR, // 114 - MISCREG_SCR, // 115 - MISCREG_SDER, // 116 - MISCREG_NSACR, // 117 - MISCREG_HSCTLR, // 118 - MISCREG_HACTLR, // 119 - MISCREG_HCR, // 120 - MISCREG_HDCR, // 121 - MISCREG_HCPTR, // 122 - MISCREG_HSTR, // 123 - MISCREG_HACR, // 124 - MISCREG_TTBR0, // 125 - MISCREG_TTBR0_NS, // 126 - MISCREG_TTBR0_S, // 127 - MISCREG_TTBR1, // 128 - MISCREG_TTBR1_NS, // 129 - MISCREG_TTBR1_S, // 130 - MISCREG_TTBCR, // 131 - MISCREG_TTBCR_NS, // 132 - MISCREG_TTBCR_S, // 133 - MISCREG_HTCR, // 134 - MISCREG_VTCR, // 135 - MISCREG_DACR, // 136 - MISCREG_DACR_NS, // 137 - MISCREG_DACR_S, // 138 - MISCREG_DFSR, // 139 - MISCREG_DFSR_NS, // 140 - MISCREG_DFSR_S, // 141 - MISCREG_IFSR, // 142 - MISCREG_IFSR_NS, // 143 - MISCREG_IFSR_S, // 144 - MISCREG_ADFSR, // 145 - MISCREG_ADFSR_NS, // 146 - MISCREG_ADFSR_S, // 147 - MISCREG_AIFSR, // 148 - MISCREG_AIFSR_NS, // 149 - MISCREG_AIFSR_S, // 150 - MISCREG_HADFSR, // 151 - MISCREG_HAIFSR, // 152 - MISCREG_HSR, // 153 - MISCREG_DFAR, // 154 - MISCREG_DFAR_NS, // 155 - MISCREG_DFAR_S, // 156 - MISCREG_IFAR, // 157 - MISCREG_IFAR_NS, // 158 - MISCREG_IFAR_S, // 159 - MISCREG_HDFAR, // 160 - MISCREG_HIFAR, // 161 - MISCREG_HPFAR, // 162 - MISCREG_ICIALLUIS, // 163 - MISCREG_BPIALLIS, // 164 - MISCREG_PAR, // 165 - MISCREG_PAR_NS, // 166 - MISCREG_PAR_S, // 167 - MISCREG_ICIALLU, // 168 - MISCREG_ICIMVAU, // 169 - MISCREG_CP15ISB, // 170 - MISCREG_BPIALL, // 171 - MISCREG_BPIMVA, // 172 - MISCREG_DCIMVAC, // 173 - MISCREG_DCISW, // 174 - MISCREG_ATS1CPR, // 175 - MISCREG_ATS1CPW, // 176 - MISCREG_ATS1CUR, // 177 - MISCREG_ATS1CUW, // 178 - MISCREG_ATS12NSOPR, // 179 - MISCREG_ATS12NSOPW, // 180 - MISCREG_ATS12NSOUR, // 181 - MISCREG_ATS12NSOUW, // 182 - MISCREG_DCCMVAC, // 183 - MISCREG_DCCSW, // 184 - MISCREG_CP15DSB, // 185 - MISCREG_CP15DMB, // 186 - MISCREG_DCCMVAU, // 187 - MISCREG_DCCIMVAC, // 188 - MISCREG_DCCISW, // 189 - MISCREG_ATS1HR, // 190 - MISCREG_ATS1HW, // 191 - MISCREG_TLBIALLIS, // 192 - MISCREG_TLBIMVAIS, // 193 - MISCREG_TLBIASIDIS, // 194 - MISCREG_TLBIMVAAIS, // 195 - MISCREG_TLBIMVALIS, // 196 - MISCREG_TLBIMVAALIS, // 197 - MISCREG_ITLBIALL, // 198 - MISCREG_ITLBIMVA, // 199 - MISCREG_ITLBIASID, // 200 - MISCREG_DTLBIALL, // 201 - MISCREG_DTLBIMVA, // 202 - MISCREG_DTLBIASID, // 203 - MISCREG_TLBIALL, // 204 - MISCREG_TLBIMVA, // 205 - MISCREG_TLBIASID, // 206 - MISCREG_TLBIMVAA, // 207 - MISCREG_TLBIMVAL, // 208 - MISCREG_TLBIMVAAL, // 209 - MISCREG_TLBIIPAS2IS, // 210 - MISCREG_TLBIIPAS2LIS, // 211 - MISCREG_TLBIALLHIS, // 212 - MISCREG_TLBIMVAHIS, // 213 - MISCREG_TLBIALLNSNHIS, // 214 - MISCREG_TLBIMVALHIS, // 215 - MISCREG_TLBIIPAS2, // 216 - MISCREG_TLBIIPAS2L, // 217 - MISCREG_TLBIALLH, // 218 - MISCREG_TLBIMVAH, // 219 - MISCREG_TLBIALLNSNH, // 220 - MISCREG_TLBIMVALH, // 221 - MISCREG_PMCR, // 222 - MISCREG_PMCNTENSET, // 223 - MISCREG_PMCNTENCLR, // 224 - MISCREG_PMOVSR, // 225 - MISCREG_PMSWINC, // 226 - MISCREG_PMSELR, // 227 - MISCREG_PMCEID0, // 228 - MISCREG_PMCEID1, // 229 - MISCREG_PMCCNTR, // 230 - MISCREG_PMXEVTYPER, // 231 - MISCREG_PMCCFILTR, // 232 - MISCREG_PMXEVCNTR, // 233 - MISCREG_PMUSERENR, // 234 - MISCREG_PMINTENSET, // 235 - MISCREG_PMINTENCLR, // 236 - MISCREG_PMOVSSET, // 237 - MISCREG_L2CTLR, // 238 - MISCREG_L2ECTLR, // 239 - MISCREG_PRRR, // 240 - MISCREG_PRRR_NS, // 241 - MISCREG_PRRR_S, // 242 - MISCREG_MAIR0, // 243 - MISCREG_MAIR0_NS, // 244 - MISCREG_MAIR0_S, // 245 - MISCREG_NMRR, // 246 - MISCREG_NMRR_NS, // 247 - MISCREG_NMRR_S, // 248 - MISCREG_MAIR1, // 249 - MISCREG_MAIR1_NS, // 250 - MISCREG_MAIR1_S, // 251 - MISCREG_AMAIR0, // 252 - MISCREG_AMAIR0_NS, // 253 - MISCREG_AMAIR0_S, // 254 - MISCREG_AMAIR1, // 255 - MISCREG_AMAIR1_NS, // 256 - MISCREG_AMAIR1_S, // 257 - MISCREG_HMAIR0, // 258 - MISCREG_HMAIR1, // 259 - MISCREG_HAMAIR0, // 260 - MISCREG_HAMAIR1, // 261 - MISCREG_VBAR, // 262 - MISCREG_VBAR_NS, // 263 - MISCREG_VBAR_S, // 264 - MISCREG_MVBAR, // 265 - MISCREG_RMR, // 266 - MISCREG_ISR, // 267 - MISCREG_HVBAR, // 268 - MISCREG_FCSEIDR, // 269 - MISCREG_CONTEXTIDR, // 270 - MISCREG_CONTEXTIDR_NS, // 271 - MISCREG_CONTEXTIDR_S, // 272 - MISCREG_TPIDRURW, // 273 - MISCREG_TPIDRURW_NS, // 274 - MISCREG_TPIDRURW_S, // 275 - MISCREG_TPIDRURO, // 276 - MISCREG_TPIDRURO_NS, // 277 - MISCREG_TPIDRURO_S, // 278 - MISCREG_TPIDRPRW, // 279 - MISCREG_TPIDRPRW_NS, // 280 - MISCREG_TPIDRPRW_S, // 281 - MISCREG_HTPIDR, // 282 - MISCREG_CNTFRQ, // 283 - MISCREG_CNTKCTL, // 284 - MISCREG_CNTP_TVAL, // 285 - MISCREG_CNTP_TVAL_NS, // 286 - MISCREG_CNTP_TVAL_S, // 287 - MISCREG_CNTP_CTL, // 288 - MISCREG_CNTP_CTL_NS, // 289 - MISCREG_CNTP_CTL_S, // 290 - MISCREG_CNTV_TVAL, // 291 - MISCREG_CNTV_CTL, // 292 - MISCREG_CNTHCTL, // 293 - MISCREG_CNTHP_TVAL, // 294 - MISCREG_CNTHP_CTL, // 295 - MISCREG_IL1DATA0, // 296 - MISCREG_IL1DATA1, // 297 - MISCREG_IL1DATA2, // 298 - MISCREG_IL1DATA3, // 299 - MISCREG_DL1DATA0, // 300 - MISCREG_DL1DATA1, // 301 - MISCREG_DL1DATA2, // 302 - MISCREG_DL1DATA3, // 303 - MISCREG_DL1DATA4, // 304 - MISCREG_RAMINDEX, // 305 - MISCREG_L2ACTLR, // 306 - MISCREG_CBAR, // 307 - MISCREG_HTTBR, // 308 - MISCREG_VTTBR, // 309 - MISCREG_CNTPCT, // 310 - MISCREG_CNTVCT, // 311 - MISCREG_CNTP_CVAL, // 312 - MISCREG_CNTP_CVAL_NS, // 313 - MISCREG_CNTP_CVAL_S, // 314 - MISCREG_CNTV_CVAL, // 315 - MISCREG_CNTVOFF, // 316 - MISCREG_CNTHP_CVAL, // 317 - MISCREG_CPUMERRSR, // 318 - MISCREG_L2MERRSR, // 319 + MISCREG_MIDR, + MISCREG_CTR, + MISCREG_TCMTR, + MISCREG_TLBTR, + MISCREG_MPIDR, + MISCREG_REVIDR, + MISCREG_ID_PFR0, + MISCREG_ID_PFR1, + MISCREG_ID_DFR0, + MISCREG_ID_AFR0, + MISCREG_ID_MMFR0, + MISCREG_ID_MMFR1, + MISCREG_ID_MMFR2, + MISCREG_ID_MMFR3, + MISCREG_ID_ISAR0, + MISCREG_ID_ISAR1, + MISCREG_ID_ISAR2, + MISCREG_ID_ISAR3, + MISCREG_ID_ISAR4, + MISCREG_ID_ISAR5, + MISCREG_CCSIDR, + MISCREG_CLIDR, + MISCREG_AIDR, + MISCREG_CSSELR, + MISCREG_CSSELR_NS, + MISCREG_CSSELR_S, + MISCREG_VPIDR, + MISCREG_VMPIDR, + MISCREG_SCTLR, + MISCREG_SCTLR_NS, + MISCREG_SCTLR_S, + MISCREG_ACTLR, + MISCREG_ACTLR_NS, + MISCREG_ACTLR_S, + MISCREG_CPACR, + MISCREG_SCR, + MISCREG_SDER, + MISCREG_NSACR, + MISCREG_HSCTLR, + MISCREG_HACTLR, + MISCREG_HCR, + MISCREG_HDCR, + MISCREG_HCPTR, + MISCREG_HSTR, + MISCREG_HACR, + MISCREG_TTBR0, + MISCREG_TTBR0_NS, + MISCREG_TTBR0_S, + MISCREG_TTBR1, + MISCREG_TTBR1_NS, + MISCREG_TTBR1_S, + MISCREG_TTBCR, + MISCREG_TTBCR_NS, + MISCREG_TTBCR_S, + MISCREG_HTCR, + MISCREG_VTCR, + MISCREG_DACR, + MISCREG_DACR_NS, + MISCREG_DACR_S, + MISCREG_DFSR, + MISCREG_DFSR_NS, + MISCREG_DFSR_S, + MISCREG_IFSR, + MISCREG_IFSR_NS, + MISCREG_IFSR_S, + MISCREG_ADFSR, + MISCREG_ADFSR_NS, + MISCREG_ADFSR_S, + MISCREG_AIFSR, + MISCREG_AIFSR_NS, + MISCREG_AIFSR_S, + MISCREG_HADFSR, + MISCREG_HAIFSR, + MISCREG_HSR, + MISCREG_DFAR, + MISCREG_DFAR_NS, + MISCREG_DFAR_S, + MISCREG_IFAR, + MISCREG_IFAR_NS, + MISCREG_IFAR_S, + MISCREG_HDFAR, + MISCREG_HIFAR, + MISCREG_HPFAR, + MISCREG_ICIALLUIS, + MISCREG_BPIALLIS, + MISCREG_PAR, + MISCREG_PAR_NS, + MISCREG_PAR_S, + MISCREG_ICIALLU, + MISCREG_ICIMVAU, + MISCREG_CP15ISB, + MISCREG_BPIALL, + MISCREG_BPIMVA, + MISCREG_DCIMVAC, + MISCREG_DCISW, + MISCREG_ATS1CPR, + MISCREG_ATS1CPW, + MISCREG_ATS1CUR, + MISCREG_ATS1CUW, + MISCREG_ATS12NSOPR, + MISCREG_ATS12NSOPW, + MISCREG_ATS12NSOUR, + MISCREG_ATS12NSOUW, + MISCREG_DCCMVAC, + MISCREG_DCCSW, + MISCREG_CP15DSB, + MISCREG_CP15DMB, + MISCREG_DCCMVAU, + MISCREG_DCCIMVAC, + MISCREG_DCCISW, + MISCREG_ATS1HR, + MISCREG_ATS1HW, + MISCREG_TLBIALLIS, + MISCREG_TLBIMVAIS, + MISCREG_TLBIASIDIS, + MISCREG_TLBIMVAAIS, + MISCREG_TLBIMVALIS, + MISCREG_TLBIMVAALIS, + MISCREG_ITLBIALL, + MISCREG_ITLBIMVA, + MISCREG_ITLBIASID, + MISCREG_DTLBIALL, + MISCREG_DTLBIMVA, + MISCREG_DTLBIASID, + MISCREG_TLBIALL, + MISCREG_TLBIMVA, + MISCREG_TLBIASID, + MISCREG_TLBIMVAA, + MISCREG_TLBIMVAL, + MISCREG_TLBIMVAAL, + MISCREG_TLBIIPAS2IS, + MISCREG_TLBIIPAS2LIS, + MISCREG_TLBIALLHIS, + MISCREG_TLBIMVAHIS, + MISCREG_TLBIALLNSNHIS, + MISCREG_TLBIMVALHIS, + MISCREG_TLBIIPAS2, + MISCREG_TLBIIPAS2L, + MISCREG_TLBIALLH, + MISCREG_TLBIMVAH, + MISCREG_TLBIALLNSNH, + MISCREG_TLBIMVALH, + MISCREG_PMCR, + MISCREG_PMCNTENSET, + MISCREG_PMCNTENCLR, + MISCREG_PMOVSR, + MISCREG_PMSWINC, + MISCREG_PMSELR, + MISCREG_PMCEID0, + MISCREG_PMCEID1, + MISCREG_PMCCNTR, + MISCREG_PMXEVTYPER, + MISCREG_PMCCFILTR, + MISCREG_PMXEVCNTR, + MISCREG_PMUSERENR, + MISCREG_PMINTENSET, + MISCREG_PMINTENCLR, + MISCREG_PMOVSSET, + MISCREG_L2CTLR, + MISCREG_L2ECTLR, + MISCREG_PRRR, + MISCREG_PRRR_NS, + MISCREG_PRRR_S, + MISCREG_MAIR0, + MISCREG_MAIR0_NS, + MISCREG_MAIR0_S, + MISCREG_NMRR, + MISCREG_NMRR_NS, + MISCREG_NMRR_S, + MISCREG_MAIR1, + MISCREG_MAIR1_NS, + MISCREG_MAIR1_S, + MISCREG_AMAIR0, + MISCREG_AMAIR0_NS, + MISCREG_AMAIR0_S, + MISCREG_AMAIR1, + MISCREG_AMAIR1_NS, + MISCREG_AMAIR1_S, + MISCREG_HMAIR0, + MISCREG_HMAIR1, + MISCREG_HAMAIR0, + MISCREG_HAMAIR1, + MISCREG_VBAR, + MISCREG_VBAR_NS, + MISCREG_VBAR_S, + MISCREG_MVBAR, + MISCREG_RMR, + MISCREG_ISR, + MISCREG_HVBAR, + MISCREG_FCSEIDR, + MISCREG_CONTEXTIDR, + MISCREG_CONTEXTIDR_NS, + MISCREG_CONTEXTIDR_S, + MISCREG_TPIDRURW, + MISCREG_TPIDRURW_NS, + MISCREG_TPIDRURW_S, + MISCREG_TPIDRURO, + MISCREG_TPIDRURO_NS, + MISCREG_TPIDRURO_S, + MISCREG_TPIDRPRW, + MISCREG_TPIDRPRW_NS, + MISCREG_TPIDRPRW_S, + MISCREG_HTPIDR, + MISCREG_CNTFRQ, + MISCREG_CNTKCTL, + MISCREG_CNTP_TVAL, + MISCREG_CNTP_TVAL_NS, + MISCREG_CNTP_TVAL_S, + MISCREG_CNTP_CTL, + MISCREG_CNTP_CTL_NS, + MISCREG_CNTP_CTL_S, + MISCREG_CNTV_TVAL, + MISCREG_CNTV_CTL, + MISCREG_CNTHCTL, + MISCREG_CNTHP_TVAL, + MISCREG_CNTHP_CTL, + MISCREG_IL1DATA0, + MISCREG_IL1DATA1, + MISCREG_IL1DATA2, + MISCREG_IL1DATA3, + MISCREG_DL1DATA0, + MISCREG_DL1DATA1, + MISCREG_DL1DATA2, + MISCREG_DL1DATA3, + MISCREG_DL1DATA4, + MISCREG_RAMINDEX, + MISCREG_L2ACTLR, + MISCREG_CBAR, + MISCREG_HTTBR, + MISCREG_VTTBR, + MISCREG_CNTPCT, + MISCREG_CNTVCT, + MISCREG_CNTP_CVAL, + MISCREG_CNTP_CVAL_NS, + MISCREG_CNTP_CVAL_S, + MISCREG_CNTV_CVAL, + MISCREG_CNTVOFF, + MISCREG_CNTHP_CVAL, + MISCREG_CPUMERRSR, + MISCREG_L2MERRSR, // AArch64 registers (Op0=2) - MISCREG_MDCCINT_EL1, // 320 - MISCREG_OSDTRRX_EL1, // 321 - MISCREG_MDSCR_EL1, // 322 - MISCREG_OSDTRTX_EL1, // 323 - MISCREG_OSECCR_EL1, // 324 - MISCREG_DBGBVR0_EL1, // 325 - MISCREG_DBGBVR1_EL1, // 326 - MISCREG_DBGBVR2_EL1, // 327 - MISCREG_DBGBVR3_EL1, // 328 - MISCREG_DBGBVR4_EL1, // 329 - MISCREG_DBGBVR5_EL1, // 330 - MISCREG_DBGBCR0_EL1, // 331 - MISCREG_DBGBCR1_EL1, // 332 - MISCREG_DBGBCR2_EL1, // 333 - MISCREG_DBGBCR3_EL1, // 334 - MISCREG_DBGBCR4_EL1, // 335 - MISCREG_DBGBCR5_EL1, // 336 - MISCREG_DBGWVR0_EL1, // 337 - MISCREG_DBGWVR1_EL1, // 338 - MISCREG_DBGWVR2_EL1, // 339 - MISCREG_DBGWVR3_EL1, // 340 - MISCREG_DBGWCR0_EL1, // 341 - MISCREG_DBGWCR1_EL1, // 342 - MISCREG_DBGWCR2_EL1, // 343 - MISCREG_DBGWCR3_EL1, // 344 - MISCREG_MDCCSR_EL0, // 345 - MISCREG_MDDTR_EL0, // 346 - MISCREG_MDDTRTX_EL0, // 347 - MISCREG_MDDTRRX_EL0, // 348 - MISCREG_DBGVCR32_EL2, // 349 - MISCREG_MDRAR_EL1, // 350 - MISCREG_OSLAR_EL1, // 351 - MISCREG_OSLSR_EL1, // 352 - MISCREG_OSDLR_EL1, // 353 - MISCREG_DBGPRCR_EL1, // 354 - MISCREG_DBGCLAIMSET_EL1, // 355 - MISCREG_DBGCLAIMCLR_EL1, // 356 - MISCREG_DBGAUTHSTATUS_EL1, // 357 - MISCREG_TEECR32_EL1, // 358, not in ARM DDI 0487A.b+ - MISCREG_TEEHBR32_EL1, // 359, not in ARM DDI 0487A.b+ + MISCREG_MDCCINT_EL1, + MISCREG_OSDTRRX_EL1, + MISCREG_MDSCR_EL1, + MISCREG_OSDTRTX_EL1, + MISCREG_OSECCR_EL1, + MISCREG_DBGBVR0_EL1, + MISCREG_DBGBVR1_EL1, + MISCREG_DBGBVR2_EL1, + MISCREG_DBGBVR3_EL1, + MISCREG_DBGBVR4_EL1, + MISCREG_DBGBVR5_EL1, + MISCREG_DBGBCR0_EL1, + MISCREG_DBGBCR1_EL1, + MISCREG_DBGBCR2_EL1, + MISCREG_DBGBCR3_EL1, + MISCREG_DBGBCR4_EL1, + MISCREG_DBGBCR5_EL1, + MISCREG_DBGWVR0_EL1, + MISCREG_DBGWVR1_EL1, + MISCREG_DBGWVR2_EL1, + MISCREG_DBGWVR3_EL1, + MISCREG_DBGWCR0_EL1, + MISCREG_DBGWCR1_EL1, + MISCREG_DBGWCR2_EL1, + MISCREG_DBGWCR3_EL1, + MISCREG_MDCCSR_EL0, + MISCREG_MDDTR_EL0, + MISCREG_MDDTRTX_EL0, + MISCREG_MDDTRRX_EL0, + MISCREG_DBGVCR32_EL2, + MISCREG_MDRAR_EL1, + MISCREG_OSLAR_EL1, + MISCREG_OSLSR_EL1, + MISCREG_OSDLR_EL1, + MISCREG_DBGPRCR_EL1, + MISCREG_DBGCLAIMSET_EL1, + MISCREG_DBGCLAIMCLR_EL1, + MISCREG_DBGAUTHSTATUS_EL1, + MISCREG_TEECR32_EL1, // not in ARM DDI 0487A.b+ + MISCREG_TEEHBR32_EL1, // not in ARM DDI 0487A.b+ // AArch64 registers (Op0=1,3) - MISCREG_MIDR_EL1, // 360 - MISCREG_MPIDR_EL1, // 361 - MISCREG_REVIDR_EL1, // 362 - MISCREG_ID_PFR0_EL1, // 363 - MISCREG_ID_PFR1_EL1, // 364 - MISCREG_ID_DFR0_EL1, // 365 - MISCREG_ID_AFR0_EL1, // 366 - MISCREG_ID_MMFR0_EL1, // 367 - MISCREG_ID_MMFR1_EL1, // 368 - MISCREG_ID_MMFR2_EL1, // 369 - MISCREG_ID_MMFR3_EL1, // 370 - MISCREG_ID_ISAR0_EL1, // 371 - MISCREG_ID_ISAR1_EL1, // 372 - MISCREG_ID_ISAR2_EL1, // 373 - MISCREG_ID_ISAR3_EL1, // 374 - MISCREG_ID_ISAR4_EL1, // 375 - MISCREG_ID_ISAR5_EL1, // 376 - MISCREG_MVFR0_EL1, // 377 - MISCREG_MVFR1_EL1, // 378 - MISCREG_MVFR2_EL1, // 379 - MISCREG_ID_AA64PFR0_EL1, // 380 - MISCREG_ID_AA64PFR1_EL1, // 381 - MISCREG_ID_AA64DFR0_EL1, // 382 - MISCREG_ID_AA64DFR1_EL1, // 383 - MISCREG_ID_AA64AFR0_EL1, // 384 - MISCREG_ID_AA64AFR1_EL1, // 385 - MISCREG_ID_AA64ISAR0_EL1, // 386 - MISCREG_ID_AA64ISAR1_EL1, // 387 - MISCREG_ID_AA64MMFR0_EL1, // 388 - MISCREG_ID_AA64MMFR1_EL1, // 389 - MISCREG_CCSIDR_EL1, // 390 - MISCREG_CLIDR_EL1, // 391 - MISCREG_AIDR_EL1, // 392 - MISCREG_CSSELR_EL1, // 393 - MISCREG_CTR_EL0, // 394 - MISCREG_DCZID_EL0, // 395 - MISCREG_VPIDR_EL2, // 396 - MISCREG_VMPIDR_EL2, // 397 - MISCREG_SCTLR_EL1, // 398 - MISCREG_ACTLR_EL1, // 399 - MISCREG_CPACR_EL1, // 400 - MISCREG_SCTLR_EL2, // 401 - MISCREG_ACTLR_EL2, // 402 - MISCREG_HCR_EL2, // 403 - MISCREG_MDCR_EL2, // 404 - MISCREG_CPTR_EL2, // 405 - MISCREG_HSTR_EL2, // 406 - MISCREG_HACR_EL2, // 407 - MISCREG_SCTLR_EL3, // 408 - MISCREG_ACTLR_EL3, // 409 - MISCREG_SCR_EL3, // 410 - MISCREG_SDER32_EL3, // 411 - MISCREG_CPTR_EL3, // 412 - MISCREG_MDCR_EL3, // 413 - MISCREG_TTBR0_EL1, // 414 - MISCREG_TTBR1_EL1, // 415 - MISCREG_TCR_EL1, // 416 - MISCREG_TTBR0_EL2, // 417 - MISCREG_TCR_EL2, // 418 - MISCREG_VTTBR_EL2, // 419 - MISCREG_VTCR_EL2, // 420 - MISCREG_TTBR0_EL3, // 421 - MISCREG_TCR_EL3, // 422 - MISCREG_DACR32_EL2, // 423 - MISCREG_SPSR_EL1, // 424 - MISCREG_ELR_EL1, // 425 - MISCREG_SP_EL0, // 426 - MISCREG_SPSEL, // 427 - MISCREG_CURRENTEL, // 428 - MISCREG_NZCV, // 429 - MISCREG_DAIF, // 430 - MISCREG_FPCR, // 431 - MISCREG_FPSR, // 432 - MISCREG_DSPSR_EL0, // 433 - MISCREG_DLR_EL0, // 434 - MISCREG_SPSR_EL2, // 435 - MISCREG_ELR_EL2, // 436 - MISCREG_SP_EL1, // 437 - MISCREG_SPSR_IRQ_AA64, // 438 - MISCREG_SPSR_ABT_AA64, // 439 - MISCREG_SPSR_UND_AA64, // 440 - MISCREG_SPSR_FIQ_AA64, // 441 - MISCREG_SPSR_EL3, // 442 - MISCREG_ELR_EL3, // 443 - MISCREG_SP_EL2, // 444 - MISCREG_AFSR0_EL1, // 445 - MISCREG_AFSR1_EL1, // 446 - MISCREG_ESR_EL1, // 447 - MISCREG_IFSR32_EL2, // 448 - MISCREG_AFSR0_EL2, // 449 - MISCREG_AFSR1_EL2, // 450 - MISCREG_ESR_EL2, // 451 - MISCREG_FPEXC32_EL2, // 452 - MISCREG_AFSR0_EL3, // 453 - MISCREG_AFSR1_EL3, // 454 - MISCREG_ESR_EL3, // 455 - MISCREG_FAR_EL1, // 456 - MISCREG_FAR_EL2, // 457 - MISCREG_HPFAR_EL2, // 458 - MISCREG_FAR_EL3, // 459 - MISCREG_IC_IALLUIS, // 460 - MISCREG_PAR_EL1, // 461 - MISCREG_IC_IALLU, // 462 - MISCREG_DC_IVAC_Xt, // 463 - MISCREG_DC_ISW_Xt, // 464 - MISCREG_AT_S1E1R_Xt, // 465 - MISCREG_AT_S1E1W_Xt, // 466 - MISCREG_AT_S1E0R_Xt, // 467 - MISCREG_AT_S1E0W_Xt, // 468 - MISCREG_DC_CSW_Xt, // 469 - MISCREG_DC_CISW_Xt, // 470 - MISCREG_DC_ZVA_Xt, // 471 - MISCREG_IC_IVAU_Xt, // 472 - MISCREG_DC_CVAC_Xt, // 473 - MISCREG_DC_CVAU_Xt, // 474 - MISCREG_DC_CIVAC_Xt, // 475 - MISCREG_AT_S1E2R_Xt, // 476 - MISCREG_AT_S1E2W_Xt, // 477 - MISCREG_AT_S12E1R_Xt, // 478 - MISCREG_AT_S12E1W_Xt, // 479 - MISCREG_AT_S12E0R_Xt, // 480 - MISCREG_AT_S12E0W_Xt, // 481 - MISCREG_AT_S1E3R_Xt, // 482 - MISCREG_AT_S1E3W_Xt, // 483 - MISCREG_TLBI_VMALLE1IS, // 484 - MISCREG_TLBI_VAE1IS_Xt, // 485 - MISCREG_TLBI_ASIDE1IS_Xt, // 486 - MISCREG_TLBI_VAAE1IS_Xt, // 487 - MISCREG_TLBI_VALE1IS_Xt, // 488 - MISCREG_TLBI_VAALE1IS_Xt, // 489 - MISCREG_TLBI_VMALLE1, // 490 - MISCREG_TLBI_VAE1_Xt, // 491 - MISCREG_TLBI_ASIDE1_Xt, // 492 - MISCREG_TLBI_VAAE1_Xt, // 493 - MISCREG_TLBI_VALE1_Xt, // 494 - MISCREG_TLBI_VAALE1_Xt, // 495 - MISCREG_TLBI_IPAS2E1IS_Xt, // 496 - MISCREG_TLBI_IPAS2LE1IS_Xt, // 497 - MISCREG_TLBI_ALLE2IS, // 498 - MISCREG_TLBI_VAE2IS_Xt, // 499 - MISCREG_TLBI_ALLE1IS, // 500 - MISCREG_TLBI_VALE2IS_Xt, // 501 - MISCREG_TLBI_VMALLS12E1IS, // 502 - MISCREG_TLBI_IPAS2E1_Xt, // 503 - MISCREG_TLBI_IPAS2LE1_Xt, // 504 - MISCREG_TLBI_ALLE2, // 505 - MISCREG_TLBI_VAE2_Xt, // 506 - MISCREG_TLBI_ALLE1, // 507 - MISCREG_TLBI_VALE2_Xt, // 508 - MISCREG_TLBI_VMALLS12E1, // 509 - MISCREG_TLBI_ALLE3IS, // 510 - MISCREG_TLBI_VAE3IS_Xt, // 511 - MISCREG_TLBI_VALE3IS_Xt, // 512 - MISCREG_TLBI_ALLE3, // 513 - MISCREG_TLBI_VAE3_Xt, // 514 - MISCREG_TLBI_VALE3_Xt, // 515 - MISCREG_PMINTENSET_EL1, // 516 - MISCREG_PMINTENCLR_EL1, // 517 - MISCREG_PMCR_EL0, // 518 - MISCREG_PMCNTENSET_EL0, // 519 - MISCREG_PMCNTENCLR_EL0, // 520 - MISCREG_PMOVSCLR_EL0, // 521 - MISCREG_PMSWINC_EL0, // 522 - MISCREG_PMSELR_EL0, // 523 - MISCREG_PMCEID0_EL0, // 524 - MISCREG_PMCEID1_EL0, // 525 - MISCREG_PMCCNTR_EL0, // 526 - MISCREG_PMXEVTYPER_EL0, // 527 - MISCREG_PMCCFILTR_EL0, // 528 - MISCREG_PMXEVCNTR_EL0, // 529 - MISCREG_PMUSERENR_EL0, // 530 - MISCREG_PMOVSSET_EL0, // 531 - MISCREG_MAIR_EL1, // 532 - MISCREG_AMAIR_EL1, // 533 - MISCREG_MAIR_EL2, // 534 - MISCREG_AMAIR_EL2, // 535 - MISCREG_MAIR_EL3, // 536 - MISCREG_AMAIR_EL3, // 537 - MISCREG_L2CTLR_EL1, // 538 - MISCREG_L2ECTLR_EL1, // 539 - MISCREG_VBAR_EL1, // 540 - MISCREG_RVBAR_EL1, // 541 - MISCREG_ISR_EL1, // 542 - MISCREG_VBAR_EL2, // 543 - MISCREG_RVBAR_EL2, // 544 - MISCREG_VBAR_EL3, // 545 - MISCREG_RVBAR_EL3, // 546 - MISCREG_RMR_EL3, // 547 - MISCREG_CONTEXTIDR_EL1, // 548 - MISCREG_TPIDR_EL1, // 549 - MISCREG_TPIDR_EL0, // 550 - MISCREG_TPIDRRO_EL0, // 551 - MISCREG_TPIDR_EL2, // 552 - MISCREG_TPIDR_EL3, // 553 - MISCREG_CNTKCTL_EL1, // 554 - MISCREG_CNTFRQ_EL0, // 555 - MISCREG_CNTPCT_EL0, // 556 - MISCREG_CNTVCT_EL0, // 557 - MISCREG_CNTP_TVAL_EL0, // 558 - MISCREG_CNTP_CTL_EL0, // 559 - MISCREG_CNTP_CVAL_EL0, // 560 - MISCREG_CNTV_TVAL_EL0, // 561 - MISCREG_CNTV_CTL_EL0, // 562 - MISCREG_CNTV_CVAL_EL0, // 563 - MISCREG_PMEVCNTR0_EL0, // 564 - MISCREG_PMEVCNTR1_EL0, // 565 - MISCREG_PMEVCNTR2_EL0, // 566 - MISCREG_PMEVCNTR3_EL0, // 567 - MISCREG_PMEVCNTR4_EL0, // 568 - MISCREG_PMEVCNTR5_EL0, // 569 - MISCREG_PMEVTYPER0_EL0, // 570 - MISCREG_PMEVTYPER1_EL0, // 571 - MISCREG_PMEVTYPER2_EL0, // 572 - MISCREG_PMEVTYPER3_EL0, // 573 - MISCREG_PMEVTYPER4_EL0, // 574 - MISCREG_PMEVTYPER5_EL0, // 575 - MISCREG_CNTVOFF_EL2, // 576 - MISCREG_CNTHCTL_EL2, // 577 - MISCREG_CNTHP_TVAL_EL2, // 578 - MISCREG_CNTHP_CTL_EL2, // 579 - MISCREG_CNTHP_CVAL_EL2, // 580 - MISCREG_CNTPS_TVAL_EL1, // 581 - MISCREG_CNTPS_CTL_EL1, // 582 - MISCREG_CNTPS_CVAL_EL1, // 583 - MISCREG_IL1DATA0_EL1, // 584 - MISCREG_IL1DATA1_EL1, // 585 - MISCREG_IL1DATA2_EL1, // 586 - MISCREG_IL1DATA3_EL1, // 587 - MISCREG_DL1DATA0_EL1, // 588 - MISCREG_DL1DATA1_EL1, // 589 - MISCREG_DL1DATA2_EL1, // 590 - MISCREG_DL1DATA3_EL1, // 591 - MISCREG_DL1DATA4_EL1, // 592 - MISCREG_L2ACTLR_EL1, // 593 - MISCREG_CPUACTLR_EL1, // 594 - MISCREG_CPUECTLR_EL1, // 595 - MISCREG_CPUMERRSR_EL1, // 596 - MISCREG_L2MERRSR_EL1, // 597 - MISCREG_CBAR_EL1, // 598 - MISCREG_CONTEXTIDR_EL2, // 599 + MISCREG_MIDR_EL1, + MISCREG_MPIDR_EL1, + MISCREG_REVIDR_EL1, + MISCREG_ID_PFR0_EL1, + MISCREG_ID_PFR1_EL1, + MISCREG_ID_DFR0_EL1, + MISCREG_ID_AFR0_EL1, + MISCREG_ID_MMFR0_EL1, + MISCREG_ID_MMFR1_EL1, + MISCREG_ID_MMFR2_EL1, + MISCREG_ID_MMFR3_EL1, + MISCREG_ID_ISAR0_EL1, + MISCREG_ID_ISAR1_EL1, + MISCREG_ID_ISAR2_EL1, + MISCREG_ID_ISAR3_EL1, + MISCREG_ID_ISAR4_EL1, + MISCREG_ID_ISAR5_EL1, + MISCREG_MVFR0_EL1, + MISCREG_MVFR1_EL1, + MISCREG_MVFR2_EL1, + MISCREG_ID_AA64PFR0_EL1, + MISCREG_ID_AA64PFR1_EL1, + MISCREG_ID_AA64DFR0_EL1, + MISCREG_ID_AA64DFR1_EL1, + MISCREG_ID_AA64AFR0_EL1, + MISCREG_ID_AA64AFR1_EL1, + MISCREG_ID_AA64ISAR0_EL1, + MISCREG_ID_AA64ISAR1_EL1, + MISCREG_ID_AA64MMFR0_EL1, + MISCREG_ID_AA64MMFR1_EL1, + MISCREG_CCSIDR_EL1, + MISCREG_CLIDR_EL1, + MISCREG_AIDR_EL1, + MISCREG_CSSELR_EL1, + MISCREG_CTR_EL0, + MISCREG_DCZID_EL0, + MISCREG_VPIDR_EL2, + MISCREG_VMPIDR_EL2, + MISCREG_SCTLR_EL1, + MISCREG_ACTLR_EL1, + MISCREG_CPACR_EL1, + MISCREG_SCTLR_EL2, + MISCREG_ACTLR_EL2, + MISCREG_HCR_EL2, + MISCREG_MDCR_EL2, + MISCREG_CPTR_EL2, + MISCREG_HSTR_EL2, + MISCREG_HACR_EL2, + MISCREG_SCTLR_EL3, + MISCREG_ACTLR_EL3, + MISCREG_SCR_EL3, + MISCREG_SDER32_EL3, + MISCREG_CPTR_EL3, + MISCREG_MDCR_EL3, + MISCREG_TTBR0_EL1, + MISCREG_TTBR1_EL1, + MISCREG_TCR_EL1, + MISCREG_TTBR0_EL2, + MISCREG_TCR_EL2, + MISCREG_VTTBR_EL2, + MISCREG_VTCR_EL2, + MISCREG_TTBR0_EL3, + MISCREG_TCR_EL3, + MISCREG_DACR32_EL2, + MISCREG_SPSR_EL1, + MISCREG_ELR_EL1, + MISCREG_SP_EL0, + MISCREG_SPSEL, + MISCREG_CURRENTEL, + MISCREG_NZCV, + MISCREG_DAIF, + MISCREG_FPCR, + MISCREG_FPSR, + MISCREG_DSPSR_EL0, + MISCREG_DLR_EL0, + MISCREG_SPSR_EL2, + MISCREG_ELR_EL2, + MISCREG_SP_EL1, + MISCREG_SPSR_IRQ_AA64, + MISCREG_SPSR_ABT_AA64, + MISCREG_SPSR_UND_AA64, + MISCREG_SPSR_FIQ_AA64, + MISCREG_SPSR_EL3, + MISCREG_ELR_EL3, + MISCREG_SP_EL2, + MISCREG_AFSR0_EL1, + MISCREG_AFSR1_EL1, + MISCREG_ESR_EL1, + MISCREG_IFSR32_EL2, + MISCREG_AFSR0_EL2, + MISCREG_AFSR1_EL2, + MISCREG_ESR_EL2, + MISCREG_FPEXC32_EL2, + MISCREG_AFSR0_EL3, + MISCREG_AFSR1_EL3, + MISCREG_ESR_EL3, + MISCREG_FAR_EL1, + MISCREG_FAR_EL2, + MISCREG_HPFAR_EL2, + MISCREG_FAR_EL3, + MISCREG_IC_IALLUIS, + MISCREG_PAR_EL1, + MISCREG_IC_IALLU, + MISCREG_DC_IVAC_Xt, + MISCREG_DC_ISW_Xt, + MISCREG_AT_S1E1R_Xt, + MISCREG_AT_S1E1W_Xt, + MISCREG_AT_S1E0R_Xt, + MISCREG_AT_S1E0W_Xt, + MISCREG_DC_CSW_Xt, + MISCREG_DC_CISW_Xt, + MISCREG_DC_ZVA_Xt, + MISCREG_IC_IVAU_Xt, + MISCREG_DC_CVAC_Xt, + MISCREG_DC_CVAU_Xt, + MISCREG_DC_CIVAC_Xt, + MISCREG_AT_S1E2R_Xt, + MISCREG_AT_S1E2W_Xt, + MISCREG_AT_S12E1R_Xt, + MISCREG_AT_S12E1W_Xt, + MISCREG_AT_S12E0R_Xt, + MISCREG_AT_S12E0W_Xt, + MISCREG_AT_S1E3R_Xt, + MISCREG_AT_S1E3W_Xt, + MISCREG_TLBI_VMALLE1IS, + MISCREG_TLBI_VAE1IS_Xt, + MISCREG_TLBI_ASIDE1IS_Xt, + MISCREG_TLBI_VAAE1IS_Xt, + MISCREG_TLBI_VALE1IS_Xt, + MISCREG_TLBI_VAALE1IS_Xt, + MISCREG_TLBI_VMALLE1, + MISCREG_TLBI_VAE1_Xt, + MISCREG_TLBI_ASIDE1_Xt, + MISCREG_TLBI_VAAE1_Xt, + MISCREG_TLBI_VALE1_Xt, + MISCREG_TLBI_VAALE1_Xt, + MISCREG_TLBI_IPAS2E1IS_Xt, + MISCREG_TLBI_IPAS2LE1IS_Xt, + MISCREG_TLBI_ALLE2IS, + MISCREG_TLBI_VAE2IS_Xt, + MISCREG_TLBI_ALLE1IS, + MISCREG_TLBI_VALE2IS_Xt, + MISCREG_TLBI_VMALLS12E1IS, + MISCREG_TLBI_IPAS2E1_Xt, + MISCREG_TLBI_IPAS2LE1_Xt, + MISCREG_TLBI_ALLE2, + MISCREG_TLBI_VAE2_Xt, + MISCREG_TLBI_ALLE1, + MISCREG_TLBI_VALE2_Xt, + MISCREG_TLBI_VMALLS12E1, + MISCREG_TLBI_ALLE3IS, + MISCREG_TLBI_VAE3IS_Xt, + MISCREG_TLBI_VALE3IS_Xt, + MISCREG_TLBI_ALLE3, + MISCREG_TLBI_VAE3_Xt, + MISCREG_TLBI_VALE3_Xt, + MISCREG_PMINTENSET_EL1, + MISCREG_PMINTENCLR_EL1, + MISCREG_PMCR_EL0, + MISCREG_PMCNTENSET_EL0, + MISCREG_PMCNTENCLR_EL0, + MISCREG_PMOVSCLR_EL0, + MISCREG_PMSWINC_EL0, + MISCREG_PMSELR_EL0, + MISCREG_PMCEID0_EL0, + MISCREG_PMCEID1_EL0, + MISCREG_PMCCNTR_EL0, + MISCREG_PMXEVTYPER_EL0, + MISCREG_PMCCFILTR_EL0, + MISCREG_PMXEVCNTR_EL0, + MISCREG_PMUSERENR_EL0, + MISCREG_PMOVSSET_EL0, + MISCREG_MAIR_EL1, + MISCREG_AMAIR_EL1, + MISCREG_MAIR_EL2, + MISCREG_AMAIR_EL2, + MISCREG_MAIR_EL3, + MISCREG_AMAIR_EL3, + MISCREG_L2CTLR_EL1, + MISCREG_L2ECTLR_EL1, + MISCREG_VBAR_EL1, + MISCREG_RVBAR_EL1, + MISCREG_ISR_EL1, + MISCREG_VBAR_EL2, + MISCREG_RVBAR_EL2, + MISCREG_VBAR_EL3, + MISCREG_RVBAR_EL3, + MISCREG_RMR_EL3, + MISCREG_CONTEXTIDR_EL1, + MISCREG_TPIDR_EL1, + MISCREG_TPIDR_EL0, + MISCREG_TPIDRRO_EL0, + MISCREG_TPIDR_EL2, + MISCREG_TPIDR_EL3, + MISCREG_CNTKCTL_EL1, + MISCREG_CNTFRQ_EL0, + MISCREG_CNTPCT_EL0, + MISCREG_CNTVCT_EL0, + MISCREG_CNTP_TVAL_EL0, + MISCREG_CNTP_CTL_EL0, + MISCREG_CNTP_CVAL_EL0, + MISCREG_CNTV_TVAL_EL0, + MISCREG_CNTV_CTL_EL0, + MISCREG_CNTV_CVAL_EL0, + MISCREG_PMEVCNTR0_EL0, + MISCREG_PMEVCNTR1_EL0, + MISCREG_PMEVCNTR2_EL0, + MISCREG_PMEVCNTR3_EL0, + MISCREG_PMEVCNTR4_EL0, + MISCREG_PMEVCNTR5_EL0, + MISCREG_PMEVTYPER0_EL0, + MISCREG_PMEVTYPER1_EL0, + MISCREG_PMEVTYPER2_EL0, + MISCREG_PMEVTYPER3_EL0, + MISCREG_PMEVTYPER4_EL0, + MISCREG_PMEVTYPER5_EL0, + MISCREG_CNTVOFF_EL2, + MISCREG_CNTHCTL_EL2, + MISCREG_CNTHP_TVAL_EL2, + MISCREG_CNTHP_CTL_EL2, + MISCREG_CNTHP_CVAL_EL2, + MISCREG_CNTPS_TVAL_EL1, + MISCREG_CNTPS_CTL_EL1, + MISCREG_CNTPS_CVAL_EL1, + MISCREG_IL1DATA0_EL1, + MISCREG_IL1DATA1_EL1, + MISCREG_IL1DATA2_EL1, + MISCREG_IL1DATA3_EL1, + MISCREG_DL1DATA0_EL1, + MISCREG_DL1DATA1_EL1, + MISCREG_DL1DATA2_EL1, + MISCREG_DL1DATA3_EL1, + MISCREG_DL1DATA4_EL1, + MISCREG_L2ACTLR_EL1, + MISCREG_CPUACTLR_EL1, + MISCREG_CPUECTLR_EL1, + MISCREG_CPUMERRSR_EL1, + MISCREG_L2MERRSR_EL1, + MISCREG_CBAR_EL1, + MISCREG_CONTEXTIDR_EL2, // Introduced in ARMv8.1 - MISCREG_TTBR1_EL2, // 600 - MISCREG_CNTHV_CTL_EL2, // 601 - MISCREG_CNTHV_CVAL_EL2, // 602 - MISCREG_CNTHV_TVAL_EL2, // 603 + MISCREG_TTBR1_EL2, + MISCREG_CNTHV_CTL_EL2, + MISCREG_CNTHV_CVAL_EL2, + MISCREG_CNTHV_TVAL_EL2, - MISCREG_ID_AA64MMFR2_EL1, // 604 + MISCREG_ID_AA64MMFR2_EL1, // These MISCREG_FREESLOT are available Misc Register // slots for future registers to be implemented. - MISCREG_FREESLOT_1, // 605 + MISCREG_FREESLOT_1, // NUM_PHYS_MISCREGS specifies the number of actual physical // registers, not considering the following pseudo-registers // (dummy registers), like UNKNOWN, CP15_UNIMPL, MISCREG_IMPDEF_UNIMPL. // Checkpointing should use this physical index when // saving/restoring register values. - NUM_PHYS_MISCREGS = 606, // 606 + NUM_PHYS_MISCREGS, // Dummy registers MISCREG_NOP, |