make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way as the twin 64 bit loads

src/arch/isa_parser.py:
src/arch/sparc/isa/decoder.isa:
src/arch/sparc/isa/operands.isa:
src/base/bigint.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/mem/packet_access.hh:
    make ldtw(a) Twin 32 bit load work correctly

--HG--
extra : convert_revision : 2646b269d58cc1774e896065875a56cf5e313b42

7 files changed, 45 insertions, 10 deletions

diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index 39500df36..9b63c8842 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -1124,9 +1124,12 @@ def buildOperandTypeMap(userDict, lineno):
                 ctype = 'float'
             elif size == 64:
                 ctype = 'double'
-        elif desc == 'twin int':
+        elif desc == 'twin64 int':
             is_signed = 0
             ctype = 'Twin64_t'
+        elif desc == 'twin32 int':
+            is_signed = 0
+            ctype = 'Twin32_t'
         if ctype == '':
             error(lineno, 'Unrecognized type description "%s" in userDict')
         operandTypeMap[ext] = (size, ctype, is_signed)
@@ -1159,7 +1162,7 @@ class Operand(object):
         # template must be careful not to use it if it doesn't apply.
         if self.isMem():
             self.mem_acc_size = self.makeAccSize()
-            if self.ctype == 'Twin64_t':
+            if self.ctype in ['Twin32_t', 'Twin64_t']:
                 self.mem_acc_type = 'Twin'
             else:
                 self.mem_acc_type = 'uint'
@@ -1392,7 +1395,7 @@ class MemOperand(Operand):
         # Note that initializations in the declarations are solely
         # to avoid 'uninitialized variable' errors from the compiler.
         # Declare memory data variable.
-        if self.ctype == 'Twin64_t':
+        if self.ctype in ['Twin32_t','Twin64_t']:
             return "%s %s; %s.a = 0; %s.b = 0;\n" % (self.ctype, self.base_name,
                     self.base_name, self.base_name)
         c = '%s %s = 0;\n' % (self.ctype, self.base_name)
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 36b9d1caa..2e85e1274 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -1160,9 +1160,8 @@ decode OP default Unknown::unknown()
             0x01: ldub({{Rd = Mem.ub;}});
             0x02: lduh({{Rd = Mem.uhw;}});
             0x03: ldtw({{
-                uint64_t val = Mem.udw;
-                RdLow = val<31:0>;
-                RdHigh = val<63:32>;
+                        RdLow = (Mem.tuw).a;
+                        RdHigh = (Mem.tuw).b;
             }});
         }
         format Store {
@@ -1250,9 +1249,8 @@ decode OP default Unknown::unknown()
                     {{RdLow.udw = (Mem.tudw).a;
                       RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
                 default: ldtwa({{
-                        uint64_t val = Mem.udw;
-                        RdLow = val<31:0>;
-                        RdHigh = val<63:32>;
+                        RdLow = (Mem.tuw).a;
+                        RdHigh = (Mem.tuw).b;
                         }}, {{EXT_ASI}});
             }
         }
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index 092544aab..038919bd1 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -37,7 +37,8 @@ def operand_types {{
     'uw' : ('unsigned int', 32),
     'sdw' : ('signed int', 64),
     'udw' : ('unsigned int', 64),
-    'tudw' : ('twin int', 64),
+    'tudw' : ('twin64 int', 64),
+    'tuw' : ('twin32 int', 32),
     'sf' : ('float', 32),
     'df' : ('float', 64),
     'qf' : ('float', 128)
diff --git a/src/base/bigint.hh b/src/base/bigint.hh
index aa60eeb04..d533e662a 100644
--- a/src/base/bigint.hh
+++ b/src/base/bigint.hh
@@ -42,9 +42,22 @@ struct m5_twin64_t {
     }
 };
 
+struct m5_twin32_t {
+    uint32_t a;
+    uint32_t b;
+    inline m5_twin32_t& operator=(const uint32_t x)
+    {
+        a = x;
+        b = x;
+        return *this;
+    }
+};
+
+
 // This is for twin loads (two 64 bit values), not 1 128 bit value (as far as
 // endian conversion is concerned!
 typedef m5_twin64_t Twin64_t;
+typedef m5_twin32_t Twin32_t;
 
 
 #endif // __BASE_BIGINT_HH__
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 3001241fe..df7e780e6 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -321,6 +321,10 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
 
 template
 Fault
+AtomicSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
+
+template
+Fault
 AtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
 
 template
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index ff3606a74..7f857c68d 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -317,6 +317,10 @@ TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
 
 template
 Fault
+TimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
+
+template
+Fault
 TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
 
 template
diff --git a/src/mem/packet_access.hh b/src/mem/packet_access.hh
index 882aa98d0..552b6dd27 100644
--- a/src/mem/packet_access.hh
+++ b/src/mem/packet_access.hh
@@ -53,6 +53,18 @@ Packet::get()
     return d;
 }
 
+template<>
+inline Twin32_t
+Packet::get()
+{
+    Twin32_t d;
+    assert(staticData || dynamicData);
+    assert(sizeof(Twin32_t) <= size);
+    d.a = TheISA::gtoh(*(uint32_t*)data);
+    d.b = TheISA::gtoh(*((uint32_t*)data + 1));
+    return d;
+}
+
 
 /** return the value of what is pointed to in the packet. */
 template <typename T>