diff options
author | Korey Sewell <ksewell@umich.edu> | 2006-06-30 20:49:31 -0400 |
---|---|---|
committer | Korey Sewell <ksewell@umich.edu> | 2006-06-30 20:49:31 -0400 |
commit | 51261196bde3403544631cdb4895c2d2a51c3f1e (patch) | |
tree | 77c746e80636bd65a1648d5c1fc87459540d6f33 | |
parent | d9ef772e8d43ebfd2a4bece76f33cc62d71258a6 (diff) | |
download | gem5-51261196bde3403544631cdb4895c2d2a51c3f1e.tar.xz |
now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
src/cpu/o3/alpha/cpu.cc:
src/cpu/o3/alpha/cpu_impl.hh:
src/cpu/o3/alpha/impl.hh:
filenames
src/cpu/o3/alpha/thread_context.hh:
public
src/cpu/o3/base_dyn_inst.cc:
src/cpu/o3/bpred_unit.cc:
src/cpu/o3/commit.cc:
src/cpu/o3/cpu.cc:
src/cpu/o3/decode.cc:
src/cpu/o3/fetch.cc:
src/cpu/o3/iew.cc:
src/cpu/o3/inst_queue.cc:
src/cpu/o3/lsq.cc:
src/cpu/o3/lsq_unit.cc:
src/cpu/o3/mem_dep_unit.cc:
src/cpu/o3/rename.cc:
src/cpu/o3/rob.cc:
use O3CPUImpl ... not Alpha
src/cpu/o3/checker_builder.cc:
filename
--HG--
extra : convert_revision : 6eb739909699ade1e2a9d63637b182413ceebc69
-rw-r--r-- | src/cpu/o3/alpha/cpu.cc | 2 | ||||
-rw-r--r-- | src/cpu/o3/alpha/cpu_impl.hh | 4 | ||||
-rw-r--r-- | src/cpu/o3/alpha/impl.hh | 8 | ||||
-rw-r--r-- | src/cpu/o3/alpha/thread_context.hh | 1 | ||||
-rw-r--r-- | src/cpu/o3/base_dyn_inst.cc | 4 | ||||
-rw-r--r-- | src/cpu/o3/bpred_unit.cc | 2 | ||||
-rw-r--r-- | src/cpu/o3/checker_builder.cc | 4 | ||||
-rw-r--r-- | src/cpu/o3/commit.cc | 2 | ||||
-rw-r--r-- | src/cpu/o3/cpu.cc | 2 | ||||
-rw-r--r-- | src/cpu/o3/decode.cc | 2 | ||||
-rw-r--r-- | src/cpu/o3/fetch.cc | 2 | ||||
-rw-r--r-- | src/cpu/o3/iew.cc | 2 | ||||
-rw-r--r-- | src/cpu/o3/inst_queue.cc | 2 | ||||
-rw-r--r-- | src/cpu/o3/lsq.cc | 2 | ||||
-rw-r--r-- | src/cpu/o3/lsq_unit.cc | 2 | ||||
-rw-r--r-- | src/cpu/o3/mem_dep_unit.cc | 10 | ||||
-rw-r--r-- | src/cpu/o3/rename.cc | 2 | ||||
-rw-r--r-- | src/cpu/o3/rob.cc | 2 |
18 files changed, 31 insertions, 24 deletions
diff --git a/src/cpu/o3/alpha/cpu.cc b/src/cpu/o3/alpha/cpu.cc index 87a4d03a7..ed10b2fd1 100644 --- a/src/cpu/o3/alpha/cpu.cc +++ b/src/cpu/o3/alpha/cpu.cc @@ -28,7 +28,7 @@ * Authors: Kevin Lim */ -#include "cpu/o3/alphaimpl.hh" +#include "cpu/o3/alpha/impl.hh" #include "cpu/o3/alpha/cpu_impl.hh" #include "cpu/o3/alpha/dyn_inst.hh" diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index 2da683398..0473e60c2 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -40,7 +40,7 @@ #include "cpu/o3/alpha/cpu.hh" #include "cpu/o3/alpha/params.hh" -#include "cpu/o3/alpha/tc.hh" +#include "cpu/o3/alpha/thread_context.hh" #include "cpu/o3/comm.hh" #include "cpu/o3/thread_state.hh" @@ -120,7 +120,7 @@ AlphaO3CPU<Impl>::AlphaO3CPU(Params *params) // CheckerThreadContext. #if USE_CHECKER if (params->checker) { - tc = new CheckerThreadContext<AlphaTC<Impl>>( + tc = new CheckerThreadContext<AlphaTC<Impl> >( alpha_tc, this->checker); } #endif diff --git a/src/cpu/o3/alpha/impl.hh b/src/cpu/o3/alpha/impl.hh index cdcdff34a..8cd8692c6 100644 --- a/src/cpu/o3/alpha/impl.hh +++ b/src/cpu/o3/alpha/impl.hh @@ -81,8 +81,14 @@ struct AlphaSimpleImpl enum { MaxWidth = 8, - MaxThreads = 2 + MaxThreads = 4 }; }; +/** The O3Impl to be used. */ +typedef AlphaSimpleImpl O3CPUImpl; + +/** The O3Impl to be used. */ +typedef DynInst O3DynInst; + #endif // __CPU_O3_ALPHA_IMPL_HH__ diff --git a/src/cpu/o3/alpha/thread_context.hh b/src/cpu/o3/alpha/thread_context.hh index 890bff3ff..57190d65e 100644 --- a/src/cpu/o3/alpha/thread_context.hh +++ b/src/cpu/o3/alpha/thread_context.hh @@ -34,6 +34,7 @@ template <class Impl> class AlphaTC : public O3ThreadContext<Impl> { + public: #if FULL_SYSTEM /** Returns a pointer to the ITB. */ virtual AlphaITB *getITBPtr() { return cpu->itb; } diff --git a/src/cpu/o3/base_dyn_inst.cc b/src/cpu/o3/base_dyn_inst.cc index a0089fb8b..0979c5c8f 100644 --- a/src/cpu/o3/base_dyn_inst.cc +++ b/src/cpu/o3/base_dyn_inst.cc @@ -32,8 +32,8 @@ #include "cpu/o3/isa_specific.hh" // Explicit instantiation -template class BaseDynInst<AlphaSimpleImpl>; +template class BaseDynInst<O3CPUImpl>; template <> int -BaseDynInst<AlphaSimpleImpl>::instcount = 0; +BaseDynInst<O3CPUImpl>::instcount = 0; diff --git a/src/cpu/o3/bpred_unit.cc b/src/cpu/o3/bpred_unit.cc index 4087fa07b..08fd4e8ea 100644 --- a/src/cpu/o3/bpred_unit.cc +++ b/src/cpu/o3/bpred_unit.cc @@ -31,4 +31,4 @@ #include "cpu/o3/bpred_unit_impl.hh" #include "cpu/o3/isa_specific.hh" -template class BPredUnit<AlphaSimpleImpl>; +template class BPredUnit<O3CPUImpl>; diff --git a/src/cpu/o3/checker_builder.cc b/src/cpu/o3/checker_builder.cc index 58c40d00c..782d963b0 100644 --- a/src/cpu/o3/checker_builder.cc +++ b/src/cpu/o3/checker_builder.cc @@ -32,8 +32,8 @@ #include "cpu/checker/cpu_impl.hh" #include "cpu/inst_seq.hh" -#include "cpu/o3/alpha_dyn_inst.hh" -#include "cpu/o3/alpha_impl.hh" +#include "cpu/o3/alpha/dyn_inst.hh" +#include "cpu/o3/alpha/impl.hh" #include "sim/builder.hh" #include "sim/process.hh" #include "sim/sim_object.hh" diff --git a/src/cpu/o3/commit.cc b/src/cpu/o3/commit.cc index 9bbb526dc..637d59f52 100644 --- a/src/cpu/o3/commit.cc +++ b/src/cpu/o3/commit.cc @@ -31,4 +31,4 @@ #include "cpu/o3/isa_specific.hh" #include "cpu/o3/commit_impl.hh" -template class DefaultCommit<AlphaSimpleImpl>; +template class DefaultCommit<O3CPUImpl>; diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index c2282d617..87fee8361 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -1211,4 +1211,4 @@ FullO3CPU<Impl>::updateThreadPriority() } // Forward declaration of FullO3CPU. -template class FullO3CPU<AlphaSimpleImpl>; +template class FullO3CPU<O3CPUImpl>; diff --git a/src/cpu/o3/decode.cc b/src/cpu/o3/decode.cc index 52d55983a..896e38331 100644 --- a/src/cpu/o3/decode.cc +++ b/src/cpu/o3/decode.cc @@ -31,4 +31,4 @@ #include "cpu/o3/isa_specific.hh" #include "cpu/o3/decode_impl.hh" -template class DefaultDecode<AlphaSimpleImpl>; +template class DefaultDecode<O3CPUImpl>; diff --git a/src/cpu/o3/fetch.cc b/src/cpu/o3/fetch.cc index 39b9879a4..d809b07e4 100644 --- a/src/cpu/o3/fetch.cc +++ b/src/cpu/o3/fetch.cc @@ -31,4 +31,4 @@ #include "cpu/o3/isa_specific.hh" #include "cpu/o3/fetch_impl.hh" -template class DefaultFetch<AlphaSimpleImpl>; +template class DefaultFetch<O3CPUImpl>; diff --git a/src/cpu/o3/iew.cc b/src/cpu/o3/iew.cc index bf8eb61ac..f99be7fe0 100644 --- a/src/cpu/o3/iew.cc +++ b/src/cpu/o3/iew.cc @@ -32,4 +32,4 @@ #include "cpu/o3/iew_impl.hh" #include "cpu/o3/inst_queue.hh" -template class DefaultIEW<AlphaSimpleImpl>; +template class DefaultIEW<O3CPUImpl>; diff --git a/src/cpu/o3/inst_queue.cc b/src/cpu/o3/inst_queue.cc index 88f3f33a0..a539066f9 100644 --- a/src/cpu/o3/inst_queue.cc +++ b/src/cpu/o3/inst_queue.cc @@ -32,4 +32,4 @@ #include "cpu/o3/inst_queue_impl.hh" // Force instantiation of InstructionQueue. -template class InstructionQueue<AlphaSimpleImpl>; +template class InstructionQueue<O3CPUImpl>; diff --git a/src/cpu/o3/lsq.cc b/src/cpu/o3/lsq.cc index 872576c32..527947281 100644 --- a/src/cpu/o3/lsq.cc +++ b/src/cpu/o3/lsq.cc @@ -32,5 +32,5 @@ #include "cpu/o3/lsq_impl.hh" // Force the instantiation of LDSTQ for all the implementations we care about. -template class LSQ<AlphaSimpleImpl>; +template class LSQ<O3CPUImpl>; diff --git a/src/cpu/o3/lsq_unit.cc b/src/cpu/o3/lsq_unit.cc index 9b244ac71..3ca3fa667 100644 --- a/src/cpu/o3/lsq_unit.cc +++ b/src/cpu/o3/lsq_unit.cc @@ -33,5 +33,5 @@ #include "cpu/o3/lsq_unit_impl.hh" // Force the instantiation of LDSTQ for all the implementations we care about. -template class LSQUnit<AlphaSimpleImpl>; +template class LSQUnit<O3CPUImpl>; diff --git a/src/cpu/o3/mem_dep_unit.cc b/src/cpu/o3/mem_dep_unit.cc index 3edac95ac..6a14dcbff 100644 --- a/src/cpu/o3/mem_dep_unit.cc +++ b/src/cpu/o3/mem_dep_unit.cc @@ -33,17 +33,17 @@ #include "cpu/o3/mem_dep_unit_impl.hh" // Force instantation of memory dependency unit using store sets and -// AlphaSimpleImpl. -template class MemDepUnit<StoreSet, AlphaSimpleImpl>; +// O3CPUImpl. +template class MemDepUnit<StoreSet, O3CPUImpl>; #ifdef DEBUG template <> int -MemDepUnit<StoreSet, AlphaSimpleImpl>::MemDepEntry::memdep_count = 0; +MemDepUnit<StoreSet, O3CPUImpl>::MemDepEntry::memdep_count = 0; template <> int -MemDepUnit<StoreSet, AlphaSimpleImpl>::MemDepEntry::memdep_insert = 0; +MemDepUnit<StoreSet, O3CPUImpl>::MemDepEntry::memdep_insert = 0; template <> int -MemDepUnit<StoreSet, AlphaSimpleImpl>::MemDepEntry::memdep_erase = 0; +MemDepUnit<StoreSet, O3CPUImpl>::MemDepEntry::memdep_erase = 0; #endif diff --git a/src/cpu/o3/rename.cc b/src/cpu/o3/rename.cc index f972190b7..443ada0cb 100644 --- a/src/cpu/o3/rename.cc +++ b/src/cpu/o3/rename.cc @@ -31,4 +31,4 @@ #include "cpu/o3/isa_specific.hh" #include "cpu/o3/rename_impl.hh" -template class DefaultRename<AlphaSimpleImpl>; +template class DefaultRename<O3CPUImpl>; diff --git a/src/cpu/o3/rob.cc b/src/cpu/o3/rob.cc index ccef6b155..9976049cd 100644 --- a/src/cpu/o3/rob.cc +++ b/src/cpu/o3/rob.cc @@ -33,4 +33,4 @@ #include "cpu/o3/rob_impl.hh" // Force instantiation of InstructionQueue. -template class ROB<AlphaSimpleImpl>; +template class ROB<O3CPUImpl>; |