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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2005-03-01 00:39:57 -0500 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2005-03-01 00:39:57 -0500 |
| commit | 58c29640b7f9ab9f4d1724b6f2c432c2146175f2 (patch) | |
| tree | f94537d1cd6b0df653a0490338235a06f4947ccb | |
| parent | 89dc94f3bc82b9acf9163d437ab132d74bca42d0 (diff) | |
| download | gem5-58c29640b7f9ab9f4d1724b6f2c432c2146175f2.tar.xz | |
Add a new operation class for IPR accesses, and have IPR-accessing
instructions use it (instead of IntALU, as before). Default config
has a single non-pipelined 3-cycle unit. A bit conservative for the
ev6 (some are 1, some are 3).
arch/alpha/isa_desc:
Make hw_mfpr and hw_mtpr use IprAccessOp op class.
cpu/full_cpu/op_class.hh:
Add IprAccess.
--HG--
extra : convert_revision : d4103da3343a586936839e29981fd15d6930d442
| -rw-r--r-- | arch/alpha/isa_desc | 3 | ||||
| -rw-r--r-- | cpu/full_cpu/op_class.hh | 1 |
2 files changed, 3 insertions, 1 deletions
diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index 5308efaae..6a6bca4fe 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -1610,7 +1610,8 @@ output decoder {{ }}; def format HwMoveIPR(code) {{ - iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code)) + iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code), + ['IprAccessOp']) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) decode_block = BasicDecode.subst(iop) diff --git a/cpu/full_cpu/op_class.hh b/cpu/full_cpu/op_class.hh index a14ccfaed..8e85e8d8a 100644 --- a/cpu/full_cpu/op_class.hh +++ b/cpu/full_cpu/op_class.hh @@ -51,6 +51,7 @@ enum OpClass { FloatSqrtOp, /* floating point square root */ MemReadOp, /* memory read port */ MemWriteOp, /* memory write port */ + IprAccessOp, /* Internal Processor Register read/write port */ InstPrefetchOp, /* instruction prefetch port (on I-cache) */ Num_OpClasses /* total functional unit classes */ }; |