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authorKevin Lim <ktlim@umich.edu>2006-11-06 13:27:45 -0500
committerKevin Lim <ktlim@umich.edu>2006-11-06 13:27:45 -0500
commit652281a61c6be7210b575e50566e7efdc82ab6ba (patch)
treeee9532bc451a62a5cc68cb41646794f5165fe14a
parent257e09d62622676b84b5166854850024a5f72bcc (diff)
downloadgem5-652281a61c6be7210b575e50566e7efdc82ab6ba.tar.xz
Clean up clock phase drift code a bit.
src/cpu/base.cc: Move clock phase drift code to the base CPU so that any CPU model can use it. src/cpu/base.hh: Added two functions to help get the next cycle the CPU should be scheduled. src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: Use the function now in BaseCPU. --HG-- extra : convert_revision : 444494b66ffc85fc473c23f57683c5f9458ad80c
-rw-r--r--src/cpu/base.cc20
-rw-r--r--src/cpu/base.hh14
-rw-r--r--src/cpu/simple/atomic.cc12
-rw-r--r--src/cpu/simple/timing.cc18
4 files changed, 45 insertions, 19 deletions
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index ea4b03bf2..55ceea8fb 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -259,6 +259,26 @@ BaseCPU::regStats()
#endif
}
+Tick
+BaseCPU::nextCycle()
+{
+ Tick next_tick = curTick + clock - 1;
+ next_tick -= (next_tick % clock);
+ return next_tick;
+}
+
+Tick
+BaseCPU::nextCycle(Tick begin_tick)
+{
+ Tick next_tick = begin_tick;
+
+ while (next_tick < curTick)
+ next_tick += clock;
+
+ next_tick -= (next_tick % clock);
+ assert(next_tick >= curTick);
+ return next_tick;
+}
void
BaseCPU::registerThreadContexts()
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 75e0d86af..df665ed23 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -73,6 +73,20 @@ class BaseCPU : public MemObject
inline Tick cycles(int numCycles) const { return clock * numCycles; }
inline Tick curCycle() const { return curTick / clock; }
+ /** The next cycle the CPU should be scheduled, given a cache
+ * access or quiesce event returning on this cycle. This function
+ * may return curTick if the CPU should run on the current cycle.
+ */
+ Tick nextCycle();
+
+ /** The next cycle the CPU should be scheduled, given a cache
+ * access or quiesce event returning on the given Tick. This
+ * function may return curTick if the CPU should run on the
+ * current cycle.
+ * @param begin_tick The tick that the event is completing on.
+ */
+ Tick nextCycle(Tick begin_tick);
+
#if FULL_SYSTEM
protected:
uint64_t interrupts[TheISA::NumInterruptLevels];
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 72249be41..4f68cfd6f 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -180,9 +180,7 @@ AtomicSimpleCPU::resume()
changeState(SimObject::Running);
if (thread->status() == ThreadContext::Active) {
if (!tickEvent.scheduled()) {
- Tick nextTick = curTick + cycles(1) - 1;
- nextTick -= (nextTick % (cycles(1)));
- tickEvent.schedule(nextTick);
+ tickEvent.schedule(nextCycle());
}
}
}
@@ -211,9 +209,7 @@ AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
ThreadContext *tc = threadContexts[i];
if (tc->status() == ThreadContext::Active && _status != Running) {
_status = Running;
- Tick nextTick = curTick + cycles(1) - 1;
- nextTick -= (nextTick % (cycles(1)));
- tickEvent.schedule(nextTick);
+ tickEvent.schedule(nextCycle());
break;
}
}
@@ -231,9 +227,7 @@ AtomicSimpleCPU::activateContext(int thread_num, int delay)
notIdleFraction++;
//Make sure ticks are still on multiples of cycles
- Tick nextTick = curTick + cycles(delay + 1) - 1;
- nextTick -= (nextTick % (cycles(1)));
- tickEvent.schedule(nextTick);
+ tickEvent.schedule(nextCycle(curTick + cycles(delay)));
_status = Running;
}
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 4d57bf6d5..abf316095 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -532,14 +532,13 @@ TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
{
if (pkt->isResponse()) {
// delay processing of returned data until next CPU clock edge
- Tick time = pkt->req->getTime();
- while (time < curTick)
- time += lat;
+ Tick mem_time = pkt->req->getTime();
+ Tick next_tick = cpu->nextCycle(mem_time);
- if (time == curTick)
+ if (next_tick == curTick)
cpu->completeIfetch(pkt);
else
- tickEvent.schedule(pkt, time);
+ tickEvent.schedule(pkt, next_tick);
return true;
}
@@ -610,14 +609,13 @@ TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
{
if (pkt->isResponse()) {
// delay processing of returned data until next CPU clock edge
- Tick time = pkt->req->getTime();
- while (time < curTick)
- time += lat;
+ Tick mem_time = pkt->req->getTime();
+ Tick next_tick = cpu->nextCycle(mem_time);
- if (time == curTick)
+ if (next_tick == curTick)
cpu->completeDataAccess(pkt);
else
- tickEvent.schedule(pkt, time);
+ tickEvent.schedule(pkt, next_tick);
return true;
}