Edit Fetch DPRINT in simple CPU

src/arch/mips/isa/formats/mt.isa:
    change copyright to 2006
src/cpu/simple/base.cc:
    Only DPRINT NNPC if we are not using ALPHA
src/cpu/static_inst.hh:
    Take Out MIPS Specific functions ...

--HG--
extra : convert_revision : 7a69e80cd1564fa3b778b9dade0e9fe3cef94e64

3 files changed, 15 insertions, 13 deletions

diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa
index 521b01123..96435f8c9 100644
--- a/src/arch/mips/isa/formats/mt.isa
+++ b/src/arch/mips/isa/formats/mt.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2003-2006 The Regents of The University of Michigan
+// Copyright (c) 2006 The Regents of The University of Michigan
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -35,14 +35,15 @@
 
 output header {{
         /**
-         * Base class for integer operations.
+         * Base class for MIPS MT ASE operations.
          */
         class MT : public MipsStaticInst
         {
                 protected:
 
                 /// Constructor
-                MT(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
+                MT(const char *mnem, MachInst _machInst, OpClass __opClass) :
+                    MipsStaticInst(mnem, _machInst, __opClass)
                 {
                 }
 
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index c1ecf3967..b854dfab2 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -26,6 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Steve Reinhardt
+ *          Korey Sewell
  */
 
 #include "arch/utility.hh"
@@ -358,8 +359,13 @@ Fault
 BaseSimpleCPU::setupFetchRequest(Request *req)
 {
     // set up memory request for instruction fetch
+#if THE_ISA == ALPHA_ISA
+    DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(),
+            thread->readNextPC());
+#else
     DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",thread->readPC(),
             thread->readNextPC(),thread->readNextNPC());
+#endif
 
     req->setVirt(0, thread->readPC() & ~3, sizeof(MachInst),
                  (FULL_SYSTEM && (thread->readPC() & 1)) ? PHYSICAL : 0,
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index bea52f510..a98078634 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -34,6 +34,7 @@
 #include <bitset>
 #include <string>
 
+#include "base/bitfield.hh"
 #include "base/hashmap.hh"
 #include "base/misc.hh"
 #include "base/refcnt.hh"
@@ -411,16 +412,10 @@ class StaticInst : public StaticInstBase
     //This is defined as inline below.
     static StaticInstPtr decode(ExtMachInst mach_inst);
 
-    //MIPS Decoder Debug Functions
-    int getOpcode() { return (machInst & 0xFC000000) >> 26 ; }//31..26
-    int getRs() {     return (machInst & 0x03E00000) >> 21; }    //25...21
-    int getRt() {     return (machInst & 0x001F0000) >> 16;  }    //20...16
-    int getRd() {     return (machInst & 0x0000F800) >> 11; }    //15...11
-    int getImm() {  return (machInst & 0x0000FFFF); }    //15...0
-    int getFunction(){  return (machInst & 0x0000003F); }//5...0
-    int getBranch(){  return (machInst & 0x0000FFFF); }//15...0
-    int getJump(){    return (machInst & 0x03FFFFFF); }//5...0
-    int getHint(){    return (machInst & 0x000007C0) >> 6; }  //10...6
+    /// Return opcode of machine instruction
+    uint32_t getOpcode() { return bits(machInst, 31, 26);}
+
+    /// Return name of machine instruction
     std::string getName() { return mnemonic; }
 };