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authorGabe Black <gblack@eecs.umich.edu>2008-10-12 20:38:22 -0700
committerGabe Black <gblack@eecs.umich.edu>2008-10-12 20:38:22 -0700
commit6b46e5204d52c8e46b48541d5112f7e9a1cadc43 (patch)
treec989f46f642d591b5550cf3706f2510e898c9eac
parent30feb90c1cba922a7dac38204900e29b4788b935 (diff)
downloadgem5-6b46e5204d52c8e46b48541d5112f7e9a1cadc43.tar.xz
X86: Implement the chks check of interrupt gate target code segments.
-rw-r--r--src/arch/x86/isa/microops/regop.isa10
1 files changed, 8 insertions, 2 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 0d019729f..ba996060c 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -1076,8 +1076,14 @@ let {{
break;
}
case SegIntCSCheck:
- panic("CS selector checks for interrupts and exceptions"
- "not implemented.\\n");
+ if (m5reg.mode == LongMode) {
+ if (desc.l != 1 || desc.d != 0) {
+ return new GeneralProtection(selector);
+ }
+ } else {
+ panic("Interrupt CS checks not implemented "
+ "in legacy mode.\\n");
+ }
break;
default:
panic("Undefined segment check type.\\n");