diff options
| author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-09-05 16:24:47 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-09-05 16:24:47 -0400 |
| commit | 6c7a490c2b779ea45adfc5708f50aa16718582e4 (patch) | |
| tree | 3633153645f9f885e8155ba740ef7aaa1a221650 | |
| parent | 89f0bc9e4c6e1c0bc58f5f5a88cdac5889758b1f (diff) | |
| download | gem5-6c7a490c2b779ea45adfc5708f50aa16718582e4.tar.xz | |
Update reference config.ini files to include port mappings.
--HG--
extra : convert_revision : f9e91a60fa09b707d2a26be57f265b7ab1c07263
46 files changed, 350 insertions, 100 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 2b85e53f6..c3a59fbce 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -121,6 +121,8 @@ trapLatency=13 wbDepth=1 wbWidth=8 workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache @@ -159,6 +161,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] [system.cpu.fuPool] type=FUPool @@ -334,6 +338,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] [system.cpu.l2cache] type=BaseCache @@ -372,10 +378,13 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] type=LiveProcess @@ -389,12 +398,14 @@ system=system [system.membus] type=Bus bus_id=0 +port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= latency=1 range=0:134217727 +port=system.membus.port[0] [trace] bufsize=0 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index 3814e38d1..5d4f9235a 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 420 # Nu global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted global.BPredUnit.lookups 2256 # Number of BP lookups global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. -host_inst_rate 34296 # Simulator instruction rate (inst/s) -host_mem_usage 160076 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host -host_tick_rate 41824 # Simulator tick rate (ticks/s) +host_inst_rate 41797 # Simulator instruction rate (inst/s) +host_mem_usage 160344 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +host_tick_rate 50948 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. @@ -170,8 +170,8 @@ system.cpu.icache.ReadReq_mshr_hits 6 # nu system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index 907b15392..fbb329a2f 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 1 2006 16:10:44 -M5 started Fri Sep 1 16:23:41 2006 +M5 compiled Sep 5 2006 15:28:48 +M5 started Tue Sep 5 15:42:12 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing Exiting @ tick 6870 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini index a530874f5..f84372165 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -68,6 +68,8 @@ simulate_stalls=false system=system width=1 workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess @@ -81,12 +83,14 @@ system=system [system.membus] type=Bus bus_id=0 +port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= latency=1 range=0:134217727 +port=system.membus.port[0] [trace] bufsize=0 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt index 72cf4f4f2..e3cd05fb0 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 108728 # Simulator instruction rate (inst/s) -host_mem_usage 147156 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 107873 # Simulator tick rate (ticks/s) +host_inst_rate 74000 # Simulator instruction rate (inst/s) +host_mem_usage 148088 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +host_tick_rate 73591 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout index 88509858c..17eea9aed 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 24 2006 13:09:55 -M5 started Thu Aug 24 14:29:33 2006 +M5 compiled Sep 5 2006 15:28:48 +M5 started Tue Sep 5 15:42:14 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic Exiting @ tick 5641 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index fe8183125..80d2a27e1 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -66,6 +66,8 @@ max_loads_any_thread=0 mem=system.cpu.dcache system=system workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache @@ -104,6 +106,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] [system.cpu.icache] type=BaseCache @@ -142,6 +146,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] [system.cpu.l2cache] type=BaseCache @@ -180,10 +186,13 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] type=LiveProcess @@ -197,12 +206,14 @@ system=system [system.membus] type=Bus bus_id=0 +port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= latency=1 range=0:134217727 +port=system.membus.port[0] [trace] bufsize=0 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index 2397e59b5..fe2cd43a5 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 73848 # Simulator instruction rate (inst/s) -host_mem_usage 159612 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 107959 # Simulator tick rate (ticks/s) +host_inst_rate 113478 # Simulator instruction rate (inst/s) +host_mem_usage 159608 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 165749 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated @@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 1802 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 2.876471 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1632 # number of overall hits system.cpu.dcache.overall_miss_latency 489 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.094340 # miss rate for overall accesses @@ -178,7 +178,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 1.968610 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits system.cpu.l2cache.overall_miss_latency 878 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.997763 # miss rate for overall accesses diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout index be2f32831..7104aa0ce 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 21 2006 14:18:48 -M5 started Mon Aug 21 14:19:14 2006 +M5 compiled Sep 5 2006 15:28:48 +M5 started Tue Sep 5 15:42:15 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing Exiting @ tick 8312 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index 388ddf7b6..790ae6ab3 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -121,6 +121,8 @@ trapLatency=13 wbDepth=1 wbWidth=8 workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache @@ -159,6 +161,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] [system.cpu.fuPool] type=FUPool @@ -334,6 +338,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] [system.cpu.l2cache] type=BaseCache @@ -372,10 +378,13 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] type=LiveProcess @@ -389,12 +398,14 @@ system=system [system.membus] type=Bus bus_id=0 +port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= latency=1 range=0:134217727 +port=system.membus.port[0] [trace] bufsize=0 diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index 5c59263ac..db582e731 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 222 # Nu global.BPredUnit.condPredicted 441 # Number of conditional branches predicted global.BPredUnit.lookups 888 # Number of BP lookups global.BPredUnit.usedRAS 160 # Number of times the RAS was used to get a target. -host_inst_rate 22611 # Simulator instruction rate (inst/s) -host_mem_usage 159596 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host -host_tick_rate 27259 # Simulator tick rate (ticks/s) +host_inst_rate 26468 # Simulator instruction rate (inst/s) +host_mem_usage 159864 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 31894 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 9 # Number of conflicting loads. memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. memdepunit.memDep.insertedLoads 675 # Number of loads inserted to the mem dependence unit. diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout index 04a06d3ab..708b9587a 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 1 2006 16:10:44 -M5 started Fri Sep 1 16:23:45 2006 +M5 compiled Sep 5 2006 15:28:48 +M5 started Tue Sep 5 15:42:16 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing Exiting @ tick 2886 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini index d845c0efb..1ec052afb 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -68,6 +68,8 @@ simulate_stalls=false system=system width=1 workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess @@ -81,12 +83,14 @@ system=system [system.membus] type=Bus bus_id=0 +port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= latency=1 range=0:134217727 +port=system.membus.port[0] [trace] bufsize=0 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt index 2317e88dc..b4747f1f4 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 58510 # Simulator instruction rate (inst/s) -host_mem_usage 146720 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 57971 # Simulator tick rate (ticks/s) +host_inst_rate 46556 # Simulator instruction rate (inst/s) +host_mem_usage 147672 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 46204 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout index d7cbe766c..438e330f5 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 18 2006 00:06:43 -M5 started Fri Aug 18 00:12:48 2006 +M5 compiled Sep 5 2006 15:28:48 +M5 started Tue Sep 5 15:42:18 2006 M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic Exiting @ tick 2577 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index 5f05f07dd..e833d841e 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -66,6 +66,8 @@ max_loads_any_thread=0 mem=system.cpu.dcache system=system workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache @@ -104,6 +106,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] [system.cpu.icache] type=BaseCache @@ -142,6 +146,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] [system.cpu.l2cache] type=BaseCache @@ -180,10 +186,13 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] type=LiveProcess @@ -197,12 +206,14 @@ system=system [system.membus] type=Bus bus_id=0 +port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= latency=1 range=0:134217727 +port=system.membus.port[0] [trace] bufsize=0 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt index ee76bf8d8..47bcc1b3c 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 5953 # Simulator instruction rate (inst/s) -host_mem_usage 159132 # Number of bytes of host memory used -host_seconds 0.43 # Real time elapsed on the host -host_tick_rate 8713 # Simulator tick rate (ticks/s) +host_inst_rate 73626 # Simulator instruction rate (inst/s) +host_mem_usage 159128 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 106590 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout index f4d7a3959..4a02e57f0 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 21 2006 14:18:48 -M5 started Mon Aug 21 14:19:22 2006 +M5 compiled Sep 5 2006 15:28:48 +M5 started Tue Sep 5 15:42:18 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing Exiting @ tick 3777 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini index f0eb69e7f..2c82b8c1a 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -68,6 +68,8 @@ simulate_stalls=false system=system width=1 workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess @@ -81,12 +83,14 @@ system=system [system.membus] type=Bus bus_id=0 +port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= latency=1 range=0:134217727 +port=system.membus.port[0] [trace] bufsize=0 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt index a45e5a877..b70a6ee17 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 124620 # Simulator instruction rate (inst/s) -host_mem_usage 147356 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 122794 # Simulator tick rate (ticks/s) +host_inst_rate 90956 # Simulator instruction rate (inst/s) +host_mem_usage 147380 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 90353 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5657 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout index 12a95eebc..f5b9c8fd7 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 18 2006 00:09:15 -M5 started Fri Aug 18 00:12:56 2006 +M5 compiled Sep 5 2006 15:37:09 +M5 started Tue Sep 5 15:46:32 2006 M5 executing on zizzer.eecs.umich.edu command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic Exiting @ tick 5656 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index ab77b14a7..040735f2c 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -66,6 +66,8 @@ max_loads_any_thread=0 mem=system.cpu.dcache system=system workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache @@ -104,6 +106,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] [system.cpu.icache] type=BaseCache @@ -142,6 +146,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] [system.cpu.l2cache] type=BaseCache @@ -180,10 +186,13 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] type=LiveProcess @@ -197,12 +206,14 @@ system=system [system.membus] type=Bus bus_id=0 +port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= latency=1 range=0:134217727 +port=system.membus.port[0] [trace] bufsize=0 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt index 54771832b..5d054b950 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 289509 # Simulator instruction rate (inst/s) +host_inst_rate 129834 # Simulator instruction rate (inst/s) host_mem_usage 158964 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 429531 # Simulator tick rate (ticks/s) +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 194881 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5657 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated @@ -90,8 +90,8 @@ system.cpu.icache.ReadReq_misses 303 # nu system.cpu.icache.ReadReq_mshr_miss_latency 604 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_refs 17.673267 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout index fd27ee686..11009935d 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 21 2006 14:43:46 -M5 started Mon Aug 21 14:44:00 2006 +M5 compiled Sep 5 2006 15:37:09 +M5 started Tue Sep 5 15:46:32 2006 M5 executing on zizzer.eecs.umich.edu command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing Exiting @ tick 8573 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini index c22373526..082415a7f 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -68,6 +68,8 @@ simulate_stalls=false system=system width=1 workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess @@ -81,12 +83,14 @@ system=system [system.membus] type=Bus bus_id=0 +port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= latency=1 range=0:134217727 +port=system.membus.port[0] [trace] bufsize=0 diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt index 52a75def4..9bfb2fec9 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 79435 # Simulator instruction rate (inst/s) -host_mem_usage 147292 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 78854 # Simulator tick rate (ticks/s) +host_inst_rate 61348 # Simulator instruction rate (inst/s) +host_mem_usage 147288 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 60991 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4483 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout index 0730d4b3e..38eb82c8b 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 24 2006 13:31:50 -M5 started Thu Aug 24 14:29:35 2006 +M5 compiled Sep 5 2006 15:39:50 +M5 started Tue Sep 5 15:49:24 2006 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic Exiting @ tick 4482 because target called exit() diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index fdd1f3de1..3f0a85931 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -67,6 +67,8 @@ delay=0 queue_size_a=16 queue_size_b=16 write_ack=false +side_a=system.iobus.port[0] +side_b=system.membus.port[0] [system.cpu0] type=AtomicSimpleCPU @@ -87,6 +89,8 @@ profile=0 simulate_stalls=false system=system width=1 +dcache_port=system.membus.port[3] +icache_port=system.membus.port[2] [system.cpu0.dtb] type=AlphaDTB @@ -115,6 +119,8 @@ profile=0 simulate_stalls=false system=system width=1 +dcache_port=system.membus.port[5] +icache_port=system.membus.port[4] [system.cpu1.dtb] type=AlphaDTB @@ -169,16 +175,20 @@ cpu=system.cpu0 [system.iobus] type=Bus bus_id=0 +default=system.tsunami.pciconfig.pio +port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ide.dma system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.dma system.tsunami.ethernet.config [system.membus] type=Bus bus_id=1 +port=system.bridge.side_b system.physmem.port system.cpu0.icache_port system.cpu0.dcache_port system.cpu1.icache_port system.cpu1.dcache_port [system.physmem] type=PhysicalMemory file= latency=1 range=0:134217727 +port=system.membus.port[1] [system.sim_console] type=SimConsole @@ -217,6 +227,7 @@ pio_latency=2 platform=system.tsunami system=system tsunami=system.tsunami +pio=system.iobus.port[1] [system.tsunami.console] type=AlphaConsole @@ -227,6 +238,7 @@ pio_latency=2 platform=system.tsunami sim_console=system.sim_console system=system +pio=system.iobus.port[25] [system.tsunami.etherint] type=NSGigEInt @@ -262,6 +274,9 @@ system=system tx_delay=2000 tx_fifo_size=524288 tx_thread=false +config=system.iobus.port[31] +dma=system.iobus.port[30] +pio=system.iobus.port[29] [system.tsunami.ethernet.configdata] type=PciConfigData @@ -305,6 +320,7 @@ pio_latency=2 pio_size=393216 platform=system.tsunami system=system +pio=system.iobus.port[9] [system.tsunami.fake_ata0] type=IsaFake @@ -313,6 +329,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[20] [system.tsunami.fake_ata1] type=IsaFake @@ -321,6 +338,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[21] [system.tsunami.fake_pnp_addr] type=IsaFake @@ -329,6 +347,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[10] [system.tsunami.fake_pnp_read0] type=IsaFake @@ -337,6 +356,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[12] [system.tsunami.fake_pnp_read1] type=IsaFake @@ -345,6 +365,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[13] [system.tsunami.fake_pnp_read2] type=IsaFake @@ -353,6 +374,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[14] [system.tsunami.fake_pnp_read3] type=IsaFake @@ -361,6 +383,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[15] [system.tsunami.fake_pnp_read4] type=IsaFake @@ -369,6 +392,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[16] [system.tsunami.fake_pnp_read5] type=IsaFake @@ -377,6 +401,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[17] [system.tsunami.fake_pnp_read6] type=IsaFake @@ -385,6 +410,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[18] [system.tsunami.fake_pnp_read7] type=IsaFake @@ -393,6 +419,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[19] [system.tsunami.fake_pnp_write] type=IsaFake @@ -401,6 +428,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[11] [system.tsunami.fake_ppc] type=IsaFake @@ -409,6 +437,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[8] [system.tsunami.fake_sm_chip] type=IsaFake @@ -417,6 +446,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[3] [system.tsunami.fake_uart1] type=IsaFake @@ -425,6 +455,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[4] [system.tsunami.fake_uart2] type=IsaFake @@ -433,6 +464,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[5] [system.tsunami.fake_uart3] type=IsaFake @@ -441,6 +473,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[6] [system.tsunami.fake_uart4] type=IsaFake @@ -449,6 +482,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[7] [system.tsunami.fb] type=BadDevice @@ -457,6 +491,7 @@ pio_addr=8804615848912 pio_latency=2 platform=system.tsunami system=system +pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController @@ -470,6 +505,9 @@ pci_func=0 pio_latency=2 platform=system.tsunami system=system +config=system.iobus.port[28] +dma=system.iobus.port[27] +pio=system.iobus.port[26] [system.tsunami.ide.configdata] type=PciConfigData @@ -515,6 +553,7 @@ platform=system.tsunami system=system time=1136073600 tsunami=system.tsunami +pio=system.iobus.port[23] [system.tsunami.pchip] type=TsunamiPChip @@ -523,6 +562,7 @@ pio_latency=2 platform=system.tsunami system=system tsunami=system.tsunami +pio=system.iobus.port[2] [system.tsunami.pciconfig] type=PciConfigAll @@ -531,6 +571,7 @@ pio_latency=1 platform=system.tsunami size=16777216 system=system +pio=system.iobus.default [system.tsunami.uart] type=Uart8250 @@ -539,6 +580,7 @@ pio_latency=2 platform=system.tsunami sim_console=system.sim_console system=system +pio=system.iobus.port[24] [trace] bufsize=0 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt index 8b48b8a92..c7715aeac 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1433278 # Simulator instruction rate (inst/s) -host_mem_usage 194568 # Number of bytes of host memory used -host_seconds 44.14 # Real time elapsed on the host -host_tick_rate 80562367 # Simulator tick rate (ticks/s) +host_inst_rate 1382023 # Simulator instruction rate (inst/s) +host_mem_usage 194588 # Number of bytes of host memory used +host_seconds 45.78 # Real time elapsed on the host +host_tick_rate 77681401 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks sim_insts 63264995 # Number of instructions simulated sim_seconds 1.778030 # Number of seconds simulated diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout index d503ac399..c8330eef2 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 17 2006 23:41:21 -M5 started Thu Aug 17 23:50:27 2006 +M5 compiled Sep 5 2006 15:32:34 +M5 started Tue Sep 5 15:43:12 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Exiting @ tick 3556060806 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index 2ee207b2e..7c93a82a1 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -67,6 +67,8 @@ delay=0 queue_size_a=16 queue_size_b=16 write_ack=false +side_a=system.iobus.port[0] +side_b=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU @@ -87,6 +89,8 @@ profile=0 simulate_stalls=false system=system width=1 +dcache_port=system.membus.port[3] +icache_port=system.membus.port[2] [system.cpu.dtb] type=AlphaDTB @@ -141,16 +145,20 @@ cpu=system.cpu [system.iobus] type=Bus bus_id=0 +default=system.tsunami.pciconfig.pio +port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ide.dma system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.dma system.tsunami.ethernet.config [system.membus] type=Bus bus_id=1 +port=system.bridge.side_b system.physmem.port system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= latency=1 range=0:134217727 +port=system.membus.port[1] [system.sim_console] type=SimConsole @@ -189,6 +197,7 @@ pio_latency=2 platform=system.tsunami system=system tsunami=system.tsunami +pio=system.iobus.port[1] [system.tsunami.console] type=AlphaConsole @@ -199,6 +208,7 @@ pio_latency=2 platform=system.tsunami sim_console=system.sim_console system=system +pio=system.iobus.port[25] [system.tsunami.etherint] type=NSGigEInt @@ -234,6 +244,9 @@ system=system tx_delay=2000 tx_fifo_size=524288 tx_thread=false +config=system.iobus.port[31] +dma=system.iobus.port[30] +pio=system.iobus.port[29] [system.tsunami.ethernet.configdata] type=PciConfigData @@ -277,6 +290,7 @@ pio_latency=2 pio_size=393216 platform=system.tsunami system=system +pio=system.iobus.port[9] [system.tsunami.fake_ata0] type=IsaFake @@ -285,6 +299,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[20] [system.tsunami.fake_ata1] type=IsaFake @@ -293,6 +308,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[21] [system.tsunami.fake_pnp_addr] type=IsaFake @@ -301,6 +317,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[10] [system.tsunami.fake_pnp_read0] type=IsaFake @@ -309,6 +326,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[12] [system.tsunami.fake_pnp_read1] type=IsaFake @@ -317,6 +335,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[13] [system.tsunami.fake_pnp_read2] type=IsaFake @@ -325,6 +344,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[14] [system.tsunami.fake_pnp_read3] type=IsaFake @@ -333,6 +353,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[15] [system.tsunami.fake_pnp_read4] type=IsaFake @@ -341,6 +362,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[16] [system.tsunami.fake_pnp_read5] type=IsaFake @@ -349,6 +371,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[17] [system.tsunami.fake_pnp_read6] type=IsaFake @@ -357,6 +380,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[18] [system.tsunami.fake_pnp_read7] type=IsaFake @@ -365,6 +389,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[19] [system.tsunami.fake_pnp_write] type=IsaFake @@ -373,6 +398,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[11] [system.tsunami.fake_ppc] type=IsaFake @@ -381,6 +407,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[8] [system.tsunami.fake_sm_chip] type=IsaFake @@ -389,6 +416,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[3] [system.tsunami.fake_uart1] type=IsaFake @@ -397,6 +425,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[4] [system.tsunami.fake_uart2] type=IsaFake @@ -405,6 +434,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[5] [system.tsunami.fake_uart3] type=IsaFake @@ -413,6 +443,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[6] [system.tsunami.fake_uart4] type=IsaFake @@ -421,6 +452,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[7] [system.tsunami.fb] type=BadDevice @@ -429,6 +461,7 @@ pio_addr=8804615848912 pio_latency=2 platform=system.tsunami system=system +pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController @@ -442,6 +475,9 @@ pci_func=0 pio_latency=2 platform=system.tsunami system=system +config=system.iobus.port[28] +dma=system.iobus.port[27] +pio=system.iobus.port[26] [system.tsunami.ide.configdata] type=PciConfigData @@ -487,6 +523,7 @@ platform=system.tsunami system=system time=1136073600 tsunami=system.tsunami +pio=system.iobus.port[23] [system.tsunami.pchip] type=TsunamiPChip @@ -495,6 +532,7 @@ pio_latency=2 platform=system.tsunami system=system tsunami=system.tsunami +pio=system.iobus.port[2] [system.tsunami.pciconfig] type=PciConfigAll @@ -503,6 +541,7 @@ pio_latency=1 platform=system.tsunami size=16777216 system=system +pio=system.iobus.default [system.tsunami.uart] type=Uart8250 @@ -511,6 +550,7 @@ pio_latency=2 platform=system.tsunami sim_console=system.sim_console system=system +pio=system.iobus.port[24] [trace] bufsize=0 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt index a4b2a851b..3a7dc1cd4 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1371456 # Simulator instruction rate (inst/s) -host_mem_usage 194364 # Number of bytes of host memory used -host_seconds 43.70 # Real time elapsed on the host -host_tick_rate 79947218 # Simulator tick rate (ticks/s) +host_inst_rate 1346129 # Simulator instruction rate (inst/s) +host_mem_usage 194392 # Number of bytes of host memory used +host_seconds 44.52 # Real time elapsed on the host +host_tick_rate 78470813 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks sim_insts 59929520 # Number of instructions simulated sim_seconds 1.746773 # Number of seconds simulated @@ -138,7 +138,7 @@ system.tsunami.ethernet.coalescedRxOrn <err: div-0> # av system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.coalescedTxIdle no value # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout index 372fa2960..c04cd5050 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 17 2006 23:41:21 -M5 started Thu Aug 17 23:41:25 2006 +M5 compiled Sep 5 2006 15:32:34 +M5 started Tue Sep 5 15:42:26 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Exiting @ tick 3493545624 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 430daba54..ae7a71c8c 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -67,6 +67,8 @@ delay=0 queue_size_a=16 queue_size_b=16 write_ack=false +side_a=system.iobus.port[0] +side_b=system.membus.port[0] [system.cpu0] type=TimingSimpleCPU @@ -85,6 +87,8 @@ max_loads_any_thread=0 mem=system.physmem profile=0 system=system +dcache_port=system.membus.port[3] +icache_port=system.membus.port[2] [system.cpu0.dtb] type=AlphaDTB @@ -111,6 +115,8 @@ max_loads_any_thread=0 mem=system.physmem profile=0 system=system +dcache_port=system.membus.port[5] +icache_port=system.membus.port[4] [system.cpu1.dtb] type=AlphaDTB @@ -165,16 +171,20 @@ cpu=system.cpu0 [system.iobus] type=Bus bus_id=0 +default=system.tsunami.pciconfig.pio +port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ide.dma system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.dma system.tsunami.ethernet.config [system.membus] type=Bus bus_id=1 +port=system.bridge.side_b system.physmem.port system.cpu0.icache_port system.cpu0.dcache_port system.cpu1.icache_port system.cpu1.dcache_port [system.physmem] type=PhysicalMemory file= latency=1 range=0:134217727 +port=system.membus.port[1] [system.sim_console] type=SimConsole @@ -213,6 +223,7 @@ pio_latency=2 platform=system.tsunami system=system tsunami=system.tsunami +pio=system.iobus.port[1] [system.tsunami.console] type=AlphaConsole @@ -223,6 +234,7 @@ pio_latency=2 platform=system.tsunami sim_console=system.sim_console system=system +pio=system.iobus.port[25] [system.tsunami.etherint] type=NSGigEInt @@ -258,6 +270,9 @@ system=system tx_delay=2000 tx_fifo_size=524288 tx_thread=false +config=system.iobus.port[31] +dma=system.iobus.port[30] +pio=system.iobus.port[29] [system.tsunami.ethernet.configdata] type=PciConfigData @@ -301,6 +316,7 @@ pio_latency=2 pio_size=393216 platform=system.tsunami system=system +pio=system.iobus.port[9] [system.tsunami.fake_ata0] type=IsaFake @@ -309,6 +325,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[20] [system.tsunami.fake_ata1] type=IsaFake @@ -317,6 +334,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[21] [system.tsunami.fake_pnp_addr] type=IsaFake @@ -325,6 +343,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[10] [system.tsunami.fake_pnp_read0] type=IsaFake @@ -333,6 +352,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[12] [system.tsunami.fake_pnp_read1] type=IsaFake @@ -341,6 +361,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[13] [system.tsunami.fake_pnp_read2] type=IsaFake @@ -349,6 +370,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[14] [system.tsunami.fake_pnp_read3] type=IsaFake @@ -357,6 +379,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[15] [system.tsunami.fake_pnp_read4] type=IsaFake @@ -365,6 +388,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[16] [system.tsunami.fake_pnp_read5] type=IsaFake @@ -373,6 +397,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[17] [system.tsunami.fake_pnp_read6] type=IsaFake @@ -381,6 +406,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[18] [system.tsunami.fake_pnp_read7] type=IsaFake @@ -389,6 +415,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[19] [system.tsunami.fake_pnp_write] type=IsaFake @@ -397,6 +424,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[11] [system.tsunami.fake_ppc] type=IsaFake @@ -405,6 +433,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[8] [system.tsunami.fake_sm_chip] type=IsaFake @@ -413,6 +442,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[3] [system.tsunami.fake_uart1] type=IsaFake @@ -421,6 +451,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[4] [system.tsunami.fake_uart2] type=IsaFake @@ -429,6 +460,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[5] [system.tsunami.fake_uart3] type=IsaFake @@ -437,6 +469,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[6] [system.tsunami.fake_uart4] type=IsaFake @@ -445,6 +478,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[7] [system.tsunami.fb] type=BadDevice @@ -453,6 +487,7 @@ pio_addr=8804615848912 pio_latency=2 platform=system.tsunami system=system +pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController @@ -466,6 +501,9 @@ pci_func=0 pio_latency=2 platform=system.tsunami system=system +config=system.iobus.port[28] +dma=system.iobus.port[27] +pio=system.iobus.port[26] [system.tsunami.ide.configdata] type=PciConfigData @@ -511,6 +549,7 @@ platform=system.tsunami system=system time=1136073600 tsunami=system.tsunami +pio=system.iobus.port[23] [system.tsunami.pchip] type=TsunamiPChip @@ -519,6 +558,7 @@ pio_latency=2 platform=system.tsunami system=system tsunami=system.tsunami +pio=system.iobus.port[2] [system.tsunami.pciconfig] type=PciConfigAll @@ -527,6 +567,7 @@ pio_latency=1 platform=system.tsunami size=16777216 system=system +pio=system.iobus.default [system.tsunami.uart] type=Uart8250 @@ -535,6 +576,7 @@ pio_latency=2 platform=system.tsunami sim_console=system.sim_console system=system +pio=system.iobus.port[24] [trace] bufsize=0 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt index 1dc674569..666766e20 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 845052 # Simulator instruction rate (inst/s) -host_mem_usage 194484 # Number of bytes of host memory used -host_seconds 74.66 # Real time elapsed on the host -host_tick_rate 47409778 # Simulator tick rate (ticks/s) +host_inst_rate 804715 # Simulator instruction rate (inst/s) +host_mem_usage 194628 # Number of bytes of host memory used +host_seconds 78.40 # Real time elapsed on the host +host_tick_rate 45146741 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks sim_insts 63088076 # Number of instructions simulated sim_seconds 1.769718 # Number of seconds simulated diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout index 47e826dde..33c194686 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 17 2006 23:41:21 -M5 started Thu Aug 17 23:51:44 2006 +M5 compiled Sep 5 2006 15:32:34 +M5 started Tue Sep 5 15:45:11 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Exiting @ tick 3539435029 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 371899028..e07b58838 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -67,6 +67,8 @@ delay=0 queue_size_a=16 queue_size_b=16 write_ack=false +side_a=system.iobus.port[0] +side_b=system.membus.port[0] [system.cpu] type=TimingSimpleCPU @@ -85,6 +87,8 @@ max_loads_any_thread=0 mem=system.physmem profile=0 system=system +dcache_port=system.membus.port[3] +icache_port=system.membus.port[2] [system.cpu.dtb] type=AlphaDTB @@ -139,16 +143,20 @@ cpu=system.cpu [system.iobus] type=Bus bus_id=0 +default=system.tsunami.pciconfig.pio +port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ide.dma system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.dma system.tsunami.ethernet.config [system.membus] type=Bus bus_id=1 +port=system.bridge.side_b system.physmem.port system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= latency=1 range=0:134217727 +port=system.membus.port[1] [system.sim_console] type=SimConsole @@ -187,6 +195,7 @@ pio_latency=2 platform=system.tsunami system=system tsunami=system.tsunami +pio=system.iobus.port[1] [system.tsunami.console] type=AlphaConsole @@ -197,6 +206,7 @@ pio_latency=2 platform=system.tsunami sim_console=system.sim_console system=system +pio=system.iobus.port[25] [system.tsunami.etherint] type=NSGigEInt @@ -232,6 +242,9 @@ system=system tx_delay=2000 tx_fifo_size=524288 tx_thread=false +config=system.iobus.port[31] +dma=system.iobus.port[30] +pio=system.iobus.port[29] [system.tsunami.ethernet.configdata] type=PciConfigData @@ -275,6 +288,7 @@ pio_latency=2 pio_size=393216 platform=system.tsunami system=system +pio=system.iobus.port[9] [system.tsunami.fake_ata0] type=IsaFake @@ -283,6 +297,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[20] [system.tsunami.fake_ata1] type=IsaFake @@ -291,6 +306,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[21] [system.tsunami.fake_pnp_addr] type=IsaFake @@ -299,6 +315,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[10] [system.tsunami.fake_pnp_read0] type=IsaFake @@ -307,6 +324,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[12] [system.tsunami.fake_pnp_read1] type=IsaFake @@ -315,6 +333,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[13] [system.tsunami.fake_pnp_read2] type=IsaFake @@ -323,6 +342,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[14] [system.tsunami.fake_pnp_read3] type=IsaFake @@ -331,6 +351,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[15] [system.tsunami.fake_pnp_read4] type=IsaFake @@ -339,6 +360,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[16] [system.tsunami.fake_pnp_read5] type=IsaFake @@ -347,6 +369,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[17] [system.tsunami.fake_pnp_read6] type=IsaFake @@ -355,6 +378,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[18] [system.tsunami.fake_pnp_read7] type=IsaFake @@ -363,6 +387,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[19] [system.tsunami.fake_pnp_write] type=IsaFake @@ -371,6 +396,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[11] [system.tsunami.fake_ppc] type=IsaFake @@ -379,6 +405,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[8] [system.tsunami.fake_sm_chip] type=IsaFake @@ -387,6 +414,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[3] [system.tsunami.fake_uart1] type=IsaFake @@ -395,6 +423,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[4] [system.tsunami.fake_uart2] type=IsaFake @@ -403,6 +432,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[5] [system.tsunami.fake_uart3] type=IsaFake @@ -411,6 +441,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[6] [system.tsunami.fake_uart4] type=IsaFake @@ -419,6 +450,7 @@ pio_latency=2 pio_size=8 platform=system.tsunami system=system +pio=system.iobus.port[7] [system.tsunami.fb] type=BadDevice @@ -427,6 +459,7 @@ pio_addr=8804615848912 pio_latency=2 platform=system.tsunami system=system +pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController @@ -440,6 +473,9 @@ pci_func=0 pio_latency=2 platform=system.tsunami system=system +config=system.iobus.port[28] +dma=system.iobus.port[27] +pio=system.iobus.port[26] [system.tsunami.ide.configdata] type=PciConfigData @@ -485,6 +521,7 @@ platform=system.tsunami system=system time=1136073600 tsunami=system.tsunami +pio=system.iobus.port[23] [system.tsunami.pchip] type=TsunamiPChip @@ -493,6 +530,7 @@ pio_latency=2 platform=system.tsunami system=system tsunami=system.tsunami +pio=system.iobus.port[2] [system.tsunami.pciconfig] type=PciConfigAll @@ -501,6 +539,7 @@ pio_latency=1 platform=system.tsunami size=16777216 system=system +pio=system.iobus.default [system.tsunami.uart] type=Uart8250 @@ -509,6 +548,7 @@ pio_latency=2 platform=system.tsunami sim_console=system.sim_console system=system +pio=system.iobus.port[24] [trace] bufsize=0 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt index 5e5ce79af..0adb4cc31 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 859270 # Simulator instruction rate (inst/s) -host_mem_usage 194168 # Number of bytes of host memory used -host_seconds 69.73 # Real time elapsed on the host -host_tick_rate 50283954 # Simulator tick rate (ticks/s) +host_inst_rate 835908 # Simulator instruction rate (inst/s) +host_mem_usage 194192 # Number of bytes of host memory used +host_seconds 71.68 # Real time elapsed on the host +host_tick_rate 48916813 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks sim_insts 59915182 # Number of instructions simulated sim_seconds 1.753109 # Number of seconds simulated @@ -138,7 +138,7 @@ system.tsunami.ethernet.coalescedRxOrn <err: div-0> # av system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.coalescedTxIdle no value # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr index 4741dd710..6204251a5 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr @@ -1,4 +1,4 @@ 0: system.tsunami.io.rtc: Real-time clock set to Sun Jan 1 00:00:00 2006 -Listening for console connection on port 3457 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001 +Listening for console connection on port 3456 +0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout index 3ad24fa97..2739943d2 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 17 2006 23:41:21 -M5 started Thu Aug 17 23:41:25 2006 +M5 compiled Sep 5 2006 15:32:34 +M5 started Tue Sep 5 15:43:59 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing Exiting @ tick 3506218170 because m5_exit instruction encountered diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini index 4f9d886f0..a4b103732 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini @@ -68,6 +68,8 @@ simulate_stalls=false system=system width=1 workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] [system.cpu.workload] type=EioProcess @@ -79,12 +81,14 @@ system=system [system.membus] type=Bus bus_id=0 +port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory file= latency=1 range=0:134217727 +port=system.membus.port[0] [trace] bufsize=0 diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt index 508b7b1e3..0132ecf1b 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1431500 # Simulator instruction rate (inst/s) -host_mem_usage 146556 # Number of bytes of host memory used -host_seconds 0.35 # Real time elapsed on the host -host_tick_rate 1429839 # Simulator tick rate (ticks/s) +host_inst_rate 1397534 # Simulator instruction rate (inst/s) +host_mem_usage 147632 # Number of bytes of host memory used +host_seconds 0.36 # Real time elapsed on the host +host_tick_rate 1395943 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout index 20413a23c..d3edcdc0a 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout @@ -7,8 +7,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 18 2006 00:06:43 -M5 started Fri Aug 18 00:12:49 2006 +M5 compiled Sep 5 2006 15:28:48 +M5 started Tue Sep 5 15:42:20 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic Exiting @ tick 499999 because a thread reached the max instruction count diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini index 0352c1b88..27568ad50 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -66,6 +66,8 @@ max_loads_any_thread=0 mem=system.cpu.dcache system=system workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache @@ -104,6 +106,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] [system.cpu.icache] type=BaseCache @@ -142,6 +146,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] [system.cpu.l2cache] type=BaseCache @@ -180,10 +186,13 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus bus_id=0 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] type=EioProcess @@ -195,12 +204,14 @@ system=system [system.membus] type=Bus bus_id=0 +port=system.physmem.port system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory file= latency=1 range=0:134217727 +port=system.membus.port[0] [trace] bufsize=0 diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt index 17e8cb668..6339e48b7 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 310464 # Simulator instruction rate (inst/s) -host_mem_usage 159200 # Number of bytes of host memory used -host_seconds 1.61 # Real time elapsed on the host -host_tick_rate 423570 # Simulator tick rate (ticks/s) +host_inst_rate 620120 # Simulator instruction rate (inst/s) +host_mem_usage 159196 # Number of bytes of host memory used +host_seconds 0.81 # Real time elapsed on the host +host_tick_rate 845850 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout index bb4db9d7d..158dcfe2b 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout @@ -7,8 +7,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 21 2006 14:18:48 -M5 started Mon Aug 21 14:19:29 2006 +M5 compiled Sep 5 2006 15:28:48 +M5 started Tue Sep 5 15:42:20 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing Exiting @ tick 682354 because a thread reached the max instruction count |