Moved some constants from isa_traits.hh to the reg file headers.

--HG--
extra : convert_revision : 378b2d9791e6282539900a2261ad2275d726b4be

7 files changed, 83 insertions, 55 deletions

diff --git a/src/arch/sparc/floatregfile.hh b/src/arch/sparc/floatregfile.hh
index 9d760c9ff..72803a5e0 100644
--- a/src/arch/sparc/floatregfile.hh
+++ b/src/arch/sparc/floatregfile.hh
@@ -38,10 +38,15 @@
 
 #include <string>
 
+class Checkpoint;
+
 namespace SparcISA
 {
     std::string getFloatRegName(RegIndex);
 
+    const int NumFloatArchRegs = 64;
+    const int NumFloatRegs = 64;
+
     typedef float float32_t;
     typedef double float64_t;
     //FIXME long double refers to a 10 byte float, rather than a
diff --git a/src/arch/sparc/intregfile.cc b/src/arch/sparc/intregfile.cc
index 358368e5f..6250b1810 100644
--- a/src/arch/sparc/intregfile.cc
+++ b/src/arch/sparc/intregfile.cc
@@ -42,7 +42,7 @@ class Checkpoint;
 
 string SparcISA::getIntRegName(RegIndex index)
 {
-    static std::string intRegName[NumIntRegs] =
+    static std::string intRegName[NumIntArchRegs] =
         {"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
          "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
          "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
@@ -78,30 +78,29 @@ IntRegFile::IntRegFile()
 IntReg IntRegFile::readReg(int intReg)
 {
     IntReg val;
-    if(intReg < NumRegularIntRegs)
+    if(intReg < NumIntArchRegs)
         val = regView[intReg >> FrameOffsetBits][intReg & FrameOffsetMask];
-    else if((intReg -= NumRegularIntRegs) < NumMicroIntRegs)
+    else if((intReg -= NumIntArchRegs) < NumMicroIntRegs)
         val = microRegs[intReg];
     else
-        panic("Tried to read non-existant integer register %d, %d\n", NumRegularIntRegs + NumMicroIntRegs + intReg, intReg);
+        panic("Tried to read non-existant integer register %d, %d\n", NumIntArchRegs + NumMicroIntRegs + intReg, intReg);
 
     DPRINTF(Sparc, "Read register %d = 0x%x\n", intReg, val);
     return val;
 }
 
-Fault IntRegFile::setReg(int intReg, const IntReg &val)
+void IntRegFile::setReg(int intReg, const IntReg &val)
 {
     if(intReg)
     {
         DPRINTF(Sparc, "Wrote register %d = 0x%x\n", intReg, val);
-        if(intReg < NumRegularIntRegs)
+        if(intReg < NumIntArchRegs)
             regView[intReg >> FrameOffsetBits][intReg & FrameOffsetMask] = val;
-        else if((intReg -= NumRegularIntRegs) < NumMicroIntRegs)
+        else if((intReg -= NumIntArchRegs) < NumMicroIntRegs)
             microRegs[intReg] = val;
         else
             panic("Tried to set non-existant integer register\n");
     }
-    return NoFault;
 }
 
 //This doesn't effect the actual CWP register.
diff --git a/src/arch/sparc/intregfile.hh b/src/arch/sparc/intregfile.hh
index 223e3b34c..59f767e8e 100644
--- a/src/arch/sparc/intregfile.hh
+++ b/src/arch/sparc/intregfile.hh
@@ -32,12 +32,13 @@
 #ifndef __ARCH_SPARC_INTREGFILE_HH__
 #define __ARCH_SPARC_INTREGFILE_HH__
 
-#include "arch/sparc/faults.hh"
 #include "arch/sparc/isa_traits.hh"
 #include "arch/sparc/types.hh"
 
 #include <string>
 
+class Checkpoint;
+
 namespace SparcISA
 {
     class RegFile;
@@ -45,6 +46,9 @@ namespace SparcISA
     //This function translates integer register file indices into names
     std::string getIntRegName(RegIndex);
 
+    const int NumIntArchRegs = 32;
+    const int NumIntRegs = MaxGL * 8 + NWindows * 16 + NumMicroIntRegs;
+
     class IntRegFile
     {
       private:
@@ -85,7 +89,7 @@ namespace SparcISA
 
         IntReg readReg(int intReg);
 
-        Fault setReg(int intReg, const IntReg &val);
+        void setReg(int intReg, const IntReg &val);
 
         void serialize(std::ostream &os);
 
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 1433ba3f8..008f45bcd 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -32,16 +32,9 @@
 #define __ARCH_SPARC_ISA_TRAITS_HH__
 
 #include "arch/sparc/types.hh"
-#include "base/misc.hh"
+#include "arch/sparc/sparc_traits.hh"
 #include "config/full_system.hh"
-#include "sim/host.hh"
 
-class ThreadContext;
-class FastCPU;
-//class FullCPU;
-class Checkpoint;
-
-class StaticInst;
 class StaticInstPtr;
 
 namespace BigEndianGuest {}
@@ -63,32 +56,12 @@ namespace SparcISA
     // SPARC NOP (sethi %(hi(0), g0)
     const MachInst NoopMachInst = 0x01000000;
 
-    const int NumRegularIntRegs = 32;
-    const int NumMicroIntRegs = 1;
-    const int NumIntRegs =
-        NumRegularIntRegs +
-        NumMicroIntRegs;
-    const int NumFloatRegs = 64;
-    const int NumMiscRegs = 40;
-
     // These enumerate all the registers for dependence tracking.
     enum DependenceTags {
-        // 0..31 are the integer regs 0..31
-        // 32..95 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
-        FP_Base_DepTag = NumIntRegs,
-        Ctrl_Base_DepTag = NumIntRegs + NumMicroIntRegs + NumFloatRegs,
+        FP_Base_DepTag = 33,
+        Ctrl_Base_DepTag = 97,
     };
 
-
-    // MAXTL - maximum trap level
-    const int MaxPTL = 2;
-    const int MaxTL  = 6;
-    const int MaxGL  = 3;
-    const int MaxPGL = 2;
-
-    // NWINDOWS - number of register windows, can be 3 to 32
-    const int NWindows = 8;
-
     // semantically meaningful register indices
     const int ZeroReg = 0;	// architecturally meaningful
     // the rest of these depend on the ABI
@@ -120,19 +93,7 @@ namespace SparcISA
 
     const int BranchPredAddrShiftAmt = 2;
 
-    const int MachineBytes = 8;
-    const int WordBytes = 4;
-    const int HalfwordBytes = 2;
-    const int ByteBytes = 1;
-
-    void serialize(std::ostream & os);
-
-    void unserialize(Checkpoint *cp, const std::string &section);
-
     StaticInstPtr decodeInst(ExtMachInst);
-
-    // return a no-op instruction... used for instruction fetch faults
-    extern const MachInst NoopMachInst;
 }
 
 #endif // __ARCH_SPARC_ISA_TRAITS_HH__
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index a60288984..9bbe9a5a0 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -50,7 +50,7 @@ class Checkpoint;
 string SparcISA::getMiscRegName(RegIndex index)
 {
     static::string miscRegName[NumMiscRegs] =
-        {"y", "ccr", "asi", "tick", "pc", "fprs", "pcr", "pic",
+        {"y", "ccr", "asi", "tick", "fprs", "pcr", "pic",
          "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
          "stick", "stick_cmpr",
          "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh
index f74943256..3093b56e6 100644
--- a/src/arch/sparc/miscregfile.hh
+++ b/src/arch/sparc/miscregfile.hh
@@ -42,7 +42,6 @@
 
 namespace SparcISA
 {
-
     //These functions map register indices to names
     std::string getMiscRegName(RegIndex);
 
@@ -92,9 +91,14 @@ namespace SparcISA
         MISCREG_HSTICK_CMPR,
 
         /** Floating Point Status Register */
-        MISCREG_FSR
+        MISCREG_FSR,
+
+        MISCREG_NUMMISCREGS
     };
 
+    const int NumMiscArchRegs = MISCREG_NUMMISCREGS;
+    const int NumMiscRegs = MISCREG_NUMMISCREGS;
+
     // The control registers, broken out into fields
     class MiscRegFile
     {
diff --git a/src/arch/sparc/sparc_traits.hh b/src/arch/sparc/sparc_traits.hh
new file mode 100644
index 000000000..a3d29ea8a
--- /dev/null
+++ b/src/arch/sparc/sparc_traits.hh
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_SPARC_SPARC_TRAITS_HH__
+#define __ARCH_SPARC_SPARC_TRAITS_HH__
+
+namespace SparcISA
+{
+    // Max trap levels
+    const int MaxPTL = 2;
+    const int MaxTL  = 6;
+    const int MaxGL  = 3;
+    const int MaxPGL = 2;
+
+    // Number of register windows, can legally be 3 to 32
+    const int NWindows = 8;
+    const int NumMicroIntRegs = 1;
+
+//    const int NumRegularIntRegs = MaxGL * 8 + NWindows * 16;
+//    const int NumMicroIntRegs = 1;
+//    const int NumIntRegs =
+//	NumRegularIntRegs +
+//	NumMicroIntRegs;
+//    const int NumFloatRegs = 64;
+//    const int NumMiscRegs = 40;
+}
+
+#endif // __ARCH_SPARC_ISA_TRAITS_HH__