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| author | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-19 21:26:46 -0400 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-19 21:26:46 -0400 |
| commit | 780aa0a0ebb765781a31d0fb58257b1efb1f324a (patch) | |
| tree | ae6dbaca9ea90d3fa7ed3b16c633229a7f995dd0 | |
| parent | cc1feb9f6ddf9d0a58365ffa9f7ae948bf19901d (diff) | |
| download | gem5-780aa0a0ebb765781a31d0fb58257b1efb1f324a.tar.xz | |
Fix corner case on assertion.
I need to move over to using the fixPacket function so I don't have to make the same changes everywhere.
Still a functional access bug someplace I need to track down in timing mode.
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
Fix corner case on assertion
tests/configs/memtest.py:
Updated memtester with uncacheable addresses and functional accesses
--HG--
extra : convert_revision : e6fa851621700ff9227b83cc5cac20af4fc8444f
| -rw-r--r-- | src/mem/cache/base_cache.cc | 2 | ||||
| -rw-r--r-- | src/mem/cache/cache_impl.hh | 4 | ||||
| -rw-r--r-- | tests/configs/memtest.py | 6 |
3 files changed, 6 insertions, 6 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc index 936a9c1fa..e0301a757 100644 --- a/src/mem/cache/base_cache.cc +++ b/src/mem/cache/base_cache.cc @@ -132,7 +132,7 @@ BaseCache::CachePort::recvFunctional(Packet *pkt) pkt_data = pkt->getPtr<uint8_t>() + offset; write_data = target->getPtr<uint8_t>(); data_size = pkt->getSize() - offset; - assert(data_size > pkt->getSize()); + assert(data_size >= pkt->getSize()); if (data_size > target->getSize()) data_size = target->getSize(); } diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index d8afcb009..ea30dbba6 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -585,7 +585,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update, pkt_data = pkt->getPtr<uint8_t>() + offset; write_data = target->getPtr<uint8_t>(); data_size = pkt->getSize() - offset; - assert(data_size > pkt->getSize()); + assert(data_size >= pkt->getSize()); if (data_size > target->getSize()) data_size = target->getSize(); } @@ -620,7 +620,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update, pkt_data = pkt->getPtr<uint8_t>() + offset; write_data = write->getPtr<uint8_t>(); data_size = pkt->getSize() - offset; - assert(data_size > pkt->getSize()); + assert(data_size >= pkt->getSize()); if (data_size > write->getSize()) data_size = write->getSize(); } diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py index 116e71af6..2b990418c 100644 --- a/tests/configs/memtest.py +++ b/tests/configs/memtest.py @@ -53,7 +53,7 @@ class L2(BaseCache): #MAX CORES IS 8 with the fals sharing method nb_cores = 8 -cpus = [ MemTest(max_loads=1e12, percent_uncacheable=0, progress_interval=1000) for i in xrange(nb_cores) ] +cpus = [ MemTest(atomic=False, max_loads=1e12, percent_uncacheable=10, progress_interval=1000) for i in xrange(nb_cores) ] # system simulated system = System(cpu = cpus, funcmem = PhysicalMemory(), @@ -90,6 +90,6 @@ system.physmem.port = system.membus.port root = Root( system = system ) root.system.mem_mode = 'timing' -#root.trace.flags="Cache CachePort Bus" -#root.trace.cycle=3810800 +#root.trace.flags="Cache CachePort MemoryAccess" +#root.trace.cycle=1 |