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| author | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-01-29 20:29:14 -0800 |
|---|---|---|
| committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-01-29 20:29:14 -0800 |
| commit | 7f03dce012d53c08a129a6835b69b19d7cd2b340 (patch) | |
| tree | b9114c9fe7d06d65347612c9a4f664a0b6a3fac5 | |
| parent | 43e4f59e4f8a055aad856b6b0dd9df6d422c815d (diff) | |
| download | gem5-7f03dce012d53c08a129a6835b69b19d7cd2b340.tar.xz | |
ruby: fix out_port declaration
| -rw-r--r-- | src/mem/protocol/MESI_CMP_directory-dma.sm | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/protocol/MESI_CMP_directory-dma.sm b/src/mem/protocol/MESI_CMP_directory-dma.sm index 143c465ef..a565c8721 100644 --- a/src/mem/protocol/MESI_CMP_directory-dma.sm +++ b/src/mem/protocol/MESI_CMP_directory-dma.sm @@ -35,7 +35,7 @@ machine(DMA, "DMA Controller") cur_state := state; } - out_port(reqToDirectory_out, DMARequestMsg, reqToDirectory, desc="..."); + out_port(reqToDirectory_out, RequestMsg, reqToDirectory, desc="..."); in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") { if (dmaRequestQueue_in.isReady()) { |