CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPU

Making the CheckerCPU a runtime time option requires the code to be compatible
with ISAs other than ARM.  This patch adds the appropriate function
stubs to allow compilation.

13 files changed, 95 insertions, 5 deletions

diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index f1199b9b6..1d18c8d39 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -600,6 +600,13 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
     translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
 }
 
+Fault
+TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
+{
+    panic("Not implemented\n");
+    return NoFault;
+}
+
 } // namespace AlphaISA
 
 AlphaISA::TLB *
diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index 1d4b6c6f8..4e56100c7 100644
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -144,6 +144,10 @@ class TLB : public BaseTLB
     Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
     void translateTiming(RequestPtr req, ThreadContext *tc,
                          Translation *translation, Mode mode);
+    /**
+     * translateFunctional stub function for future CheckerCPU support
+     */
+    Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
 };
 
 } // namespace AlphaISA
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index cd6d47d1e..49ff2caba 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -339,6 +339,13 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
     translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
 }
 
+Fault
+TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
+{
+    panic("Not implemented\n");
+    return NoFault;
+}
+
 
 MipsISA::PTE &
 TLB::index(bool advance)
diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index 834431536..e949d16d9 100644
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -114,6 +114,11 @@ class TLB : public BaseTLB
     void translateTiming(RequestPtr req, ThreadContext *tc,
             Translation *translation, Mode mode);
 
+    /** Function stub for CheckerCPU compilation issues. MIPS does not
+     *  support the Checker model at the moment.
+     */
+    Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
+
   private:
     Fault translateInst(RequestPtr req, ThreadContext *tc);
     Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
diff --git a/src/arch/power/tlb.cc b/src/arch/power/tlb.cc
index 9f535e9e5..de828a625 100644
--- a/src/arch/power/tlb.cc
+++ b/src/arch/power/tlb.cc
@@ -326,6 +326,13 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
     translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
 }
 
+Fault
+TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
+{
+    panic("Not implemented\n");
+    return NoFault;
+}
+
 PowerISA::PTE &
 TLB::index(bool advance)
 {
diff --git a/src/arch/power/tlb.hh b/src/arch/power/tlb.hh
index 590477b6a..3cf2a3706 100644
--- a/src/arch/power/tlb.hh
+++ b/src/arch/power/tlb.hh
@@ -160,6 +160,10 @@ class TLB : public BaseTLB
     Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
     void translateTiming(RequestPtr req, ThreadContext *tc,
                          Translation *translation, Mode mode);
+    /** Stub function for CheckerCPU compilation support.  Power ISA not
+     *  supported by Checker at the moment
+     */
+    Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
 
     // Checkpointing
     void serialize(std::ostream &os);
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index a6179e0f8..37f1479b0 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -841,6 +841,13 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
     translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
 }
 
+Fault
+TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
+{
+    panic("Not implemented\n");
+    return NoFault;
+}
+
 Tick
 TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
 {
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index cefa38175..89a049a8b 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -164,6 +164,10 @@ class TLB : public BaseTLB
     Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
     void translateTiming(RequestPtr req, ThreadContext *tc,
             Translation *translation, Mode mode);
+    /** Stub function for compilation support with CheckerCPU. SPARC ISA
+     *  does not support the Checker model at the moment
+     */
+    Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
     Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
     Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
     void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 456f03208..b7d0b828c 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -405,6 +405,13 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
         translation->finish(fault, req, tc, mode);
 }
 
+Fault
+TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
+{
+    panic("Not implemented\n");
+    return NoFault;
+}
+
 Walker *
 TLB::getWalker()
 {
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index a943683af..078b8b8d6 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -114,6 +114,10 @@ namespace X86ISA
         Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
         void translateTiming(RequestPtr req, ThreadContext *tc,
                 Translation *translation, Mode mode);
+        /** Stub function for compilation support of CheckerCPU. x86 ISA does
+         *  not support Checker model at the moment
+         */
+        Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
 
         TlbEntry * insert(Addr vpn, TlbEntry &entry);
 
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index c3d3a379e..afc453f87 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -311,6 +311,20 @@ class CheckerCPU : public BaseCPU
         int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
         return thread->setMiscReg(reg_idx, val);
     }
+
+#if THE_ISA == MIPS_ISA
+    uint64_t readRegOtherThread(int misc_reg)
+    {
+        panic("MIPS MT not defined for CheckerCPU.\n");
+        return 0;
+    }
+
+    void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val)
+    {
+        panic("MIPS MT not defined for CheckerCPU.\n");
+    }
+#endif
+
     /////////////////////////////////////////
 
     void recordPCChange(const TheISA::PCState &val)
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 4f3fa34d2..167c3531f 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -44,6 +44,7 @@
 #include <list>
 #include <string>
 
+#include "arch/isa_traits.hh"
 #include "arch/vtophys.hh"
 #include "base/refcnt.hh"
 #include "config/the_isa.hh"
@@ -201,9 +202,9 @@ Checker<Impl>::verify(DynInstPtr &completed_inst)
 
         // maintain $r0 semantics
         thread->setIntReg(ZeroReg, 0);
-#ifdef TARGET_ALPHA
-        thread->setFloatRegDouble(ZeroReg, 0.0);
-#endif // TARGET_ALPHA
+#if THE_ISA == ALPHA_ISA
+        thread->setFloatReg(ZeroReg, 0.0);
+#endif
 
         // Check if any recent PC changes match up with anything we
         // expect to happen.  This is mostly to check if traps or
@@ -320,7 +321,9 @@ Checker<Impl>::verify(DynInstPtr &completed_inst)
                         thread->pcState(pcState);
                         instPtr = thread->decoder.decode(newMachInst,
                                                          pcState.instAddr());
-                        machInst = newMachInst;
+#if THE_ISA != X86_ISA
+                            machInst = newMachInst;
+#endif
                     } else {
                         fetchDone = false;
                         fetchOffset += sizeof(TheISA::MachInst);
@@ -476,7 +479,11 @@ Checker<Impl>::validateInst(DynInstPtr &inst)
         }
     }
 
-    MachInst mi = static_cast<MachInst>(inst->staticInst->machInst);
+
+    MachInst mi;
+#if THE_ISA != X86_ISA
+    mi = static_cast<MachInst>(inst->staticInst->machInst);
+#endif
 
     if (mi != machInst) {
         panic("%lli: Binary instructions do not match! Inst: %#x, "
diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh
index 0f9b1028e..aaf7d6ede 100644
--- a/src/cpu/inorder/thread_context.hh
+++ b/src/cpu/inorder/thread_context.hh
@@ -40,6 +40,7 @@
 #include "arch/kernel_stats.hh"
 
 class EndQuiesceEvent;
+class CheckerCPU;
 namespace Kernel {
     class Statistics;
 };
@@ -76,6 +77,12 @@ class InOrderThreadContext : public ThreadContext
     /** @TODO: PERF: Should we bind this to a pointer in constructor? */
     TheISA::TLB *getDTBPtr() { return cpu->getDTBPtr(); }
 
+    /** Currently InOrder model does not support CheckerCPU, this is
+     *  merely here for supporting compilation of gem5 with the Checker
+     *  as a runtime option
+     */
+    CheckerCPU *getCheckerCpuPtr() { return NULL; }
+
     Decoder *getDecoderPtr() { return cpu->getDecoderPtr(); }
 
     System *getSystemPtr() { return cpu->system; }
@@ -215,6 +222,12 @@ class InOrderThreadContext : public ThreadContext
     void pcState(const TheISA::PCState &val)
     { cpu->pcState(val, thread->threadId()); }
 
+    /** Needs to be implemented for future CheckerCPU support.
+     *  See O3CPU for examples on how to integrate Checker.
+     */
+    void pcStateNoRecord(const TheISA::PCState &val)
+    {}
+
     Addr instAddr()
     { return cpu->instAddr(thread->threadId()); }