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authorGabe Black <gblack@eecs.umich.edu>2007-10-02 22:21:38 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-10-02 22:21:38 -0700
commita56c651980921d210f2c48f84ce5d3445fc38475 (patch)
tree9638492e690d36d6e644eb5f73c37e26fc3adc23
parent4049c9f76afd17c983eed923940eb7338229561d (diff)
downloadgem5-a56c651980921d210f2c48f84ce5d3445fc38475.tar.xz
Predecoder: Clear out predecoder state on an ITLB fault.
--HG-- extra : convert_revision : 68f8ff778dbd28ade5070edf5a7d662e7bf0045a
-rw-r--r--src/arch/alpha/predecoder.hh3
-rw-r--r--src/arch/mips/predecoder.hh3
-rw-r--r--src/arch/sparc/predecoder.hh3
-rw-r--r--src/arch/x86/predecoder.cc4
-rw-r--r--src/arch/x86/predecoder.hh7
-rw-r--r--src/cpu/simple/base.cc1
6 files changed, 18 insertions, 3 deletions
diff --git a/src/arch/alpha/predecoder.hh b/src/arch/alpha/predecoder.hh
index 4887de856..7a6bb3c02 100644
--- a/src/arch/alpha/predecoder.hh
+++ b/src/arch/alpha/predecoder.hh
@@ -65,6 +65,9 @@ namespace AlphaISA
{
}
+ void reset()
+ {}
+
//Use this to give data to the predecoder. This should be used
//when there is control flow.
void moreBytes(Addr pc, Addr fetchPC, MachInst inst)
diff --git a/src/arch/mips/predecoder.hh b/src/arch/mips/predecoder.hh
index e310dded4..17da15f3f 100644
--- a/src/arch/mips/predecoder.hh
+++ b/src/arch/mips/predecoder.hh
@@ -64,6 +64,9 @@ namespace MipsISA
{
}
+ void reset()
+ {}
+
//Use this to give data to the predecoder. This should be used
//when there is control flow.
void moreBytes(Addr pc, Addr fetchPC, MachInst inst)
diff --git a/src/arch/sparc/predecoder.hh b/src/arch/sparc/predecoder.hh
index d990c3256..13ce5c1b6 100644
--- a/src/arch/sparc/predecoder.hh
+++ b/src/arch/sparc/predecoder.hh
@@ -65,6 +65,9 @@ namespace SparcISA
{
}
+ void reset()
+ {}
+
//Use this to give data to the predecoder. This should be used
//when there is control flow.
void moreBytes(Addr pc, Addr fetchPC, MachInst inst)
diff --git a/src/arch/x86/predecoder.cc b/src/arch/x86/predecoder.cc
index 7f8bc7abc..62899e65a 100644
--- a/src/arch/x86/predecoder.cc
+++ b/src/arch/x86/predecoder.cc
@@ -62,7 +62,7 @@
namespace X86ISA
{
- void Predecoder::reset()
+ void Predecoder::doReset()
{
origPC = basePC + offset;
DPRINTF(Predecoder, "Setting origPC to %#x\n", origPC);
@@ -96,7 +96,7 @@ namespace X86ISA
switch(state)
{
case ResetState:
- reset();
+ doReset();
state = PrefixState;
case PrefixState:
state = doPrefixState(nextByte);
diff --git a/src/arch/x86/predecoder.hh b/src/arch/x86/predecoder.hh
index 450ebd79b..6e41e8134 100644
--- a/src/arch/x86/predecoder.hh
+++ b/src/arch/x86/predecoder.hh
@@ -134,7 +134,7 @@ namespace X86ISA
outOfBytes = true;
}
- void reset();
+ void doReset();
//State machine state
protected:
@@ -182,6 +182,11 @@ namespace X86ISA
emi.mode.submode = SixtyFourBitMode;
}
+ void reset()
+ {
+ state = ResetState;
+ }
+
ThreadContext * getTC()
{
return tc;
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 9fc1d1dd9..f3b34880e 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -463,6 +463,7 @@ BaseSimpleCPU::advancePC(Fault fault)
fetchOffset = 0;
if (fault != NoFault) {
curMacroStaticInst = StaticInst::nullStaticInstPtr;
+ predecoder.reset();
fault->invoke(tc);
thread->setMicroPC(0);
thread->setNextMicroPC(1);