diff options
| author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-09-01 17:12:43 -0700 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-09-01 17:12:43 -0700 |
| commit | abe18be544014bee31d586bf8b26ab5b622b70b7 (patch) | |
| tree | ad4059302f30b79257cb50cb8e51c5da38c6418c | |
| parent | edeb8f39a7c3cbcf428743aca3017fa42865b04a (diff) | |
| parent | d8501ec17c590a0c6f5be92e121381667ca726b6 (diff) | |
| download | gem5-abe18be544014bee31d586bf8b26ab5b622b70b7.tar.xz | |
Merge zizzer.eecs.umich.edu:/bk/newmem
into vm1.(none):/home/stever/bk/newmem-head
--HG--
extra : convert_revision : 8b0fbb6b1ea38d01d048381f18fd95ab63c4c0f1
29 files changed, 5769 insertions, 176 deletions
diff --git a/build_opts/ALPHA_SE b/build_opts/ALPHA_SE index 3fedc22ca..a08271723 100644 --- a/build_opts/ALPHA_SE +++ b/build_opts/ALPHA_SE @@ -1,2 +1,3 @@ FULL_SYSTEM = 0 SS_COMPATIBLE_FP = 1 +CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU' diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh index 72e38ae3e..4f439b8df 100644 --- a/src/arch/alpha/isa_traits.hh +++ b/src/arch/alpha/isa_traits.hh @@ -42,7 +42,6 @@ class StaticInstPtr; namespace AlphaISA { - using namespace LittleEndianGuest; // These enumerate all the registers for dependence tracking. @@ -60,12 +59,14 @@ namespace AlphaISA StaticInstPtr decodeInst(ExtMachInst); + // Alpha Does NOT have a delay slot + #define ISA_HAS_DELAY_SLOT 0 + const Addr PageShift = 13; const Addr PageBytes = ULL(1) << PageShift; const Addr PageMask = ~(PageBytes - 1); const Addr PageOffset = PageBytes - 1; - #if FULL_SYSTEM //////////////////////////////////////////////////////////////////////// diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh index fd484e315..f85fc5bea 100644 --- a/src/arch/mips/isa_traits.hh +++ b/src/arch/mips/isa_traits.hh @@ -47,6 +47,9 @@ namespace MipsISA StaticInstPtr decodeInst(ExtMachInst); + // MIPS DOES a delay slot + #define ISA_HAS_DELAY_SLOT 1 + const Addr PageShift = 13; const Addr PageBytes = ULL(1) << PageShift; const Addr PageMask = ~(PageBytes - 1); diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh index 7f830eb28..6d5aa4251 100644 --- a/src/arch/sparc/isa_traits.hh +++ b/src/arch/sparc/isa_traits.hh @@ -57,6 +57,9 @@ namespace SparcISA //This makes sure the big endian versions of certain functions are used. using namespace BigEndianGuest; + // Alpha Does NOT have a delay slot + #define ISA_HAS_DELAY_SLOT 1 + //TODO this needs to be a SPARC Noop // Alpha UNOP (ldq_u r31,0(r0)) const MachInst NoopMachInst = 0x2ffe0000; diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 40611abe6..3158aa9cf 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -291,18 +291,18 @@ class BaseDynInst : public FastAlloc, public RefCounted /** Returns whether the instruction was predicted taken or not. */ bool predTaken() -#if THE_ISA == ALPHA_ISA - { return predPC != (PC + sizeof(MachInst)); } -#else +#if ISA_HAS_DELAY_SLOT { return predPC != (nextPC + sizeof(MachInst)); } +#else + { return predPC != (PC + sizeof(MachInst)); } #endif /** Returns whether the instruction mispredicted. */ bool mispredicted() -#if THE_ISA == ALPHA_ISA - { return predPC != nextPC; } -#else +#if ISA_HAS_DELAY_SLOT { return predPC != nextNPC; } +#else + { return predPC != nextPC; } #endif // // Instruction types. Forward checks to StaticInst object. diff --git a/src/cpu/o3/bpred_unit_impl.hh b/src/cpu/o3/bpred_unit_impl.hh index e4e656632..477c8e4cb 100644 --- a/src/cpu/o3/bpred_unit_impl.hh +++ b/src/cpu/o3/bpred_unit_impl.hh @@ -29,6 +29,7 @@ */ #include "arch/types.hh" +#include "arch/isa_traits.hh" #include "base/trace.hh" #include "base/traceflags.hh" #include "cpu/o3/bpred_unit.hh" @@ -197,10 +198,10 @@ BPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC, unsigned tid) ++BTBLookups; if (inst->isCall()) { -#if THE_ISA == ALPHA_ISA - Addr ras_pc = PC + sizeof(MachInst); // Next PC -#else +#if ISA_HAS_DELAY_SLOT Addr ras_pc = PC + (2 * sizeof(MachInst)); // Next Next PC +#else + Addr ras_pc = PC + sizeof(MachInst); // Next PC #endif RAS[tid].push(ras_pc); @@ -209,8 +210,8 @@ BPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC, unsigned tid) predict_record.wasCall = true; DPRINTF(Fetch, "BranchPred: [tid:%i]: Instruction %#x was a call" - ", adding %#x to the RAS.\n", - tid, inst->readPC(), ras_pc); + ", adding %#x to the RAS index: %i.\n", + tid, inst->readPC(), ras_pc, RAS[tid].topIdx()); } if (BTB.valid(PC, tid)) { @@ -283,7 +284,6 @@ BPredUnit<Impl>::squash(const InstSeqNum &squashed_sn, unsigned tid) RAS[tid].restore(pred_hist.front().RASIndex, pred_hist.front().RASTarget); - } else if (pred_hist.front().wasCall) { DPRINTF(Fetch, "BranchPred: [tid:%i]: Removing speculative entry " "added to the RAS.\n",tid); diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index f200f5f18..34f487e2c 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -722,7 +722,7 @@ DefaultCommit<Impl>::commit() // then use one older sequence number. InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; -#if THE_ISA != ALPHA_ISA +#if ISA_HAS_DELAY_SLOT InstSeqNum bdelay_done_seq_num; bool squash_bdelay_slot; @@ -748,7 +748,7 @@ DefaultCommit<Impl>::commit() if (fromIEW->includeSquashInst[tid] == true) { squashed_inst--; -#if THE_ISA != ALPHA_ISA +#if ISA_HAS_DELAY_SLOT bdelay_done_seq_num--; #endif } @@ -756,13 +756,13 @@ DefaultCommit<Impl>::commit() // number as the youngest instruction in the ROB. youngestSeqNum[tid] = squashed_inst; -#if THE_ISA == ALPHA_ISA - rob->squash(squashed_inst, tid); - toIEW->commitInfo[tid].squashDelaySlot = true; -#else +#if ISA_HAS_DELAY_SLOT rob->squash(bdelay_done_seq_num, tid); toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot; toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num; +#else + rob->squash(squashed_inst, tid); + toIEW->commitInfo[tid].squashDelaySlot = true; #endif changedROBNumEntries[tid] = true; @@ -800,7 +800,7 @@ DefaultCommit<Impl>::commit() // Try to commit any instructions. commitInsts(); } else { -#if THE_ISA != ALPHA_ISA +#if ISA_HAS_DELAY_SLOT skidInsert(); #endif } @@ -906,11 +906,11 @@ DefaultCommit<Impl>::commitInsts() } PC[tid] = nextPC[tid]; -#if THE_ISA == ALPHA_ISA - nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst); -#else +#if ISA_HAS_DELAY_SLOT nextPC[tid] = nextNPC[tid]; nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst); +#else + nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst); #endif #if FULL_SYSTEM @@ -1115,10 +1115,7 @@ DefaultCommit<Impl>::getInsts() { DPRINTF(Commit, "Getting instructions from Rename stage.\n"); -#if THE_ISA == ALPHA_ISA - // Read any renamed instructions and place them into the ROB. - int insts_to_process = std::min((int)renameWidth, fromRename->size); -#else +#if ISA_HAS_DELAY_SLOT // Read any renamed instructions and place them into the ROB. int insts_to_process = std::min((int)renameWidth, (int)(fromRename->size + skidBuffer.size())); @@ -1127,15 +1124,16 @@ DefaultCommit<Impl>::getInsts() DPRINTF(Commit, "%i insts available to process. Rename Insts:%i " "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size, skidBuffer.size()); +#else + // Read any renamed instructions and place them into the ROB. + int insts_to_process = std::min((int)renameWidth, fromRename->size); #endif for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { DynInstPtr inst; -#if THE_ISA == ALPHA_ISA - inst = fromRename->insts[inst_num]; -#else +#if ISA_HAS_DELAY_SLOT // Get insts from skidBuffer or from Rename if (skidBuffer.size() > 0) { DPRINTF(Commit, "Grabbing skidbuffer inst.\n"); @@ -1145,6 +1143,8 @@ DefaultCommit<Impl>::getInsts() DPRINTF(Commit, "Grabbing rename inst.\n"); inst = fromRename->insts[rename_idx++]; } +#else + inst = fromRename->insts[inst_num]; #endif int tid = inst->threadNumber; @@ -1167,7 +1167,7 @@ DefaultCommit<Impl>::getInsts() } } -#if THE_ISA != ALPHA_ISA +#if ISA_HAS_DELAY_SLOT if (rename_idx < fromRename->size) { DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n"); diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index af032132e..19ab7f4c5 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -181,7 +181,6 @@ FullO3CPU<Impl>::FullO3CPU(Params *params) params->activity), globalSeqNum(1), - #if FULL_SYSTEM system(params->system), physmem(system->physmem), @@ -322,6 +321,11 @@ FullO3CPU<Impl>::FullO3CPU(Params *params) lastActivatedCycle = -1; + // Give renameMap & rename stage access to the freeList; + //for (int i=0; i < numThreads; i++) { + //globalSeqNum[i] = 1; + //} + contextSwitch = false; } @@ -627,7 +631,7 @@ FullO3CPU<Impl>::insertThread(unsigned tid) //Set PC/NPC/NNPC setPC(src_tc->readPC(), tid); setNextPC(src_tc->readNextPC(), tid); -#if THE_ISA != ALPHA_ISA +#if ISA_HAS_DELAY_SLOT setNextNPC(src_tc->readNextNPC(), tid); #endif @@ -1197,7 +1201,7 @@ FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid, while (inst_it != end_it) { assert(!instList.empty()); -#if THE_ISA != ALPHA_ISA +#if ISA_HAS_DELAY_SLOT if(!squash_delay_slot && delay_slot_seq_num >= (*inst_it)->seqNum) { break; diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 7e18571f1..dcdcd1fe6 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -598,7 +598,7 @@ class FullO3CPU : public BaseO3CPU } /** The global sequence number counter. */ - InstSeqNum globalSeqNum; + InstSeqNum globalSeqNum;//[Impl::MaxThreads]; /** Pointer to the checker, which can dynamically verify * instruction results at run time. This can be set to NULL if it diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh index 160845378..80b6cc4c9 100644 --- a/src/cpu/o3/decode_impl.hh +++ b/src/cpu/o3/decode_impl.hh @@ -282,12 +282,7 @@ DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid) toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum; toFetch->decodeInfo[tid].squash = true; toFetch->decodeInfo[tid].nextPC = inst->branchTarget(); -#if THE_ISA == ALPHA_ISA - toFetch->decodeInfo[tid].branchTaken = - inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst)); - - InstSeqNum squash_seq_num = inst->seqNum; -#else +#if ISA_HAS_DELAY_SLOT toFetch->decodeInfo[tid].branchTaken = inst->readNextNPC() != (inst->readNextPC() + sizeof(TheISA::MachInst)); @@ -295,6 +290,11 @@ DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid) squashAfterDelaySlot[tid] = false; InstSeqNum squash_seq_num = bdelayDoneSeqNum[tid]; +#else + toFetch->decodeInfo[tid].branchTaken = + inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst)); + + InstSeqNum squash_seq_num = inst->seqNum; #endif // Might have to tell fetch to unblock. @@ -317,7 +317,7 @@ DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid) // insts in them. while (!insts[tid].empty()) { -#if THE_ISA != ALPHA_ISA +#if ISA_HAS_DELAY_SLOT if (insts[tid].front()->seqNum <= squash_seq_num) { DPRINTF(Decode, "[tid:%i]: Cannot remove incoming decode " "instructions before delay slot [sn:%i]. %i insts" @@ -331,7 +331,7 @@ DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid) while (!skidBuffer[tid].empty()) { -#if THE_ISA != ALPHA_ISA +#if ISA_HAS_DELAY_SLOT if (skidBuffer[tid].front()->seqNum <= squash_seq_num) { DPRINTF(Decode, "[tid:%i]: Cannot remove skidBuffer " "instructions before delay slot [sn:%i]. %i insts" @@ -765,7 +765,7 @@ DefaultDecode<Impl>::decodeInsts(unsigned tid) // Might want to set some sort of boolean and just do // a check at the end -#if THE_ISA == ALPHA_ISA +#if !ISA_HAS_DELAY_SLOT squash(inst, inst->threadNumber); inst->setPredTarg(inst->branchTarget()); break; diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 25be9d455..bf9a73902 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -339,7 +339,7 @@ DefaultFetch<Impl>::initStage() for (int tid = 0; tid < numThreads; tid++) { PC[tid] = cpu->readPC(tid); nextPC[tid] = cpu->readNextPC(tid); -#if THE_ISA != ALPHA_ISA +#if ISA_HAS_DELAY_SLOT nextNPC[tid] = cpu->readNextNPC(tid); #endif } @@ -429,7 +429,7 @@ DefaultFetch<Impl>::takeOverFrom() stalls[i].commit = 0; PC[i] = cpu->readPC(i); nextPC[i] = cpu->readNextPC(i); -#if THE_ISA != ALPHA_ISA +#if ISA_HAS_DELAY_SLOT nextNPC[i] = cpu->readNextNPC(i); delaySlotInfo[i].branchSeqNum = -1; delaySlotInfo[i].numInsts = 0; @@ -492,22 +492,20 @@ DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC, bool predict_taken; if (!inst->isControl()) { -#if THE_ISA == ALPHA_ISA - next_PC = next_PC + instSize; - inst->setPredTarg(next_PC); -#else +#if ISA_HAS_DELAY_SLOT Addr cur_PC = next_PC; next_PC = cur_PC + instSize; //next_NPC; next_NPC = cur_PC + (2 * instSize);//next_NPC + instSize; inst->setPredTarg(next_NPC); +#else + next_PC = next_PC + instSize; + inst->setPredTarg(next_PC); #endif return false; } int tid = inst->threadNumber; -#if THE_ISA == ALPHA_ISA - predict_taken = branchPred.predict(inst, next_PC, tid); -#else +#if ISA_HAS_DELAY_SLOT Addr pred_PC = next_PC; predict_taken = branchPred.predict(inst, pred_PC, tid); @@ -539,6 +537,8 @@ DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC, next_NPC = next_NPC + instSize; } +#else + predict_taken = branchPred.predict(inst, next_PC, tid); #endif ++fetchedBranches; @@ -692,7 +692,7 @@ DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC, doSquash(new_PC, tid); -#if THE_ISA != ALPHA_ISA +#if ISA_HAS_DELAY_SLOT if (seq_num <= delaySlotInfo[tid].branchSeqNum) { delaySlotInfo[tid].numInsts = 0; delaySlotInfo[tid].targetAddr = 0; @@ -780,10 +780,7 @@ DefaultFetch<Impl>::squash(const Addr &new_PC, const InstSeqNum &seq_num, doSquash(new_PC, tid); -#if THE_ISA == ALPHA_ISA - // Tell the CPU to remove any instructions that are not in the ROB. - cpu->removeInstsNotInROB(tid, true, 0); -#else +#if ISA_HAS_DELAY_SLOT if (seq_num <= delaySlotInfo[tid].branchSeqNum) { delaySlotInfo[tid].numInsts = 0; delaySlotInfo[tid].targetAddr = 0; @@ -792,6 +789,9 @@ DefaultFetch<Impl>::squash(const Addr &new_PC, const InstSeqNum &seq_num, // Tell the CPU to remove any instructions that are not in the ROB. cpu->removeInstsNotInROB(tid, squash_delay_slot, seq_num); +#else + // Tell the CPU to remove any instructions that are not in the ROB. + cpu->removeInstsNotInROB(tid, true, 0); #endif } @@ -901,10 +901,10 @@ DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid) DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash " "from commit.\n",tid); -#if THE_ISA == ALPHA_ISA - InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum; +#if ISA_HAS_DELAY_SLOT + InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum; #else - InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum; + InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum; #endif // In any case, squash. squash(fromCommit->commitInfo[tid].nextPC, @@ -958,10 +958,10 @@ DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid) if (fetchStatus[tid] != Squashing) { -#if THE_ISA == ALPHA_ISA - InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum; -#else +#if ISA_HAS_DELAY_SLOT InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].bdelayDoneSeqNum; +#else + InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum; #endif // Squash unless we're already squashing squashFromDecode(fromDecode->decodeInfo[tid].nextPC, @@ -1162,7 +1162,7 @@ DefaultFetch<Impl>::fetch(bool &status_change) offset += instSize; -#if THE_ISA != ALPHA_ISA +#if ISA_HAS_DELAY_SLOT if (predicted_branch) { delaySlotInfo[tid].branchSeqNum = inst_seq; @@ -1205,11 +1205,7 @@ DefaultFetch<Impl>::fetch(bool &status_change) // Now that fetching is completed, update the PC to signify what the next // cycle will be. if (fault == NoFault) { -#if THE_ISA == ALPHA_ISA - DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC); - PC[tid] = next_PC; - nextPC[tid] = next_PC + instSize; -#else +#if ISA_HAS_DELAY_SLOT if (delaySlotInfo[tid].targetReady && delaySlotInfo[tid].numInsts == 0) { // Set PC to target @@ -1225,6 +1221,10 @@ DefaultFetch<Impl>::fetch(bool &status_change) } DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, PC[tid]); +#else + DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC); + PC[tid] = next_PC; + nextPC[tid] = next_PC + instSize; #endif } else { // We shouldn't be in an icache miss and also have a fault (an ITB diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh index cdc36c6c3..e9b24a6d4 100644 --- a/src/cpu/o3/iew_impl.hh +++ b/src/cpu/o3/iew_impl.hh @@ -427,10 +427,10 @@ DefaultIEW<Impl>::squash(unsigned tid) instQueue.squash(tid); // Tell the LDSTQ to start squashing. -#if THE_ISA == ALPHA_ISA - ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); -#else +#if ISA_HAS_DELAY_SLOT ldstQueue.squash(fromCommit->commitInfo[tid].bdelayDoneSeqNum, tid); +#else + ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); #endif updatedQueues = true; @@ -439,7 +439,7 @@ DefaultIEW<Impl>::squash(unsigned tid) tid, fromCommit->commitInfo[tid].bdelayDoneSeqNum); while (!skidBuffer[tid].empty()) { -#if THE_ISA != ALPHA_ISA +#if ISA_HAS_DELAY_SLOT if (skidBuffer[tid].front()->seqNum <= fromCommit->commitInfo[tid].bdelayDoneSeqNum) { DPRINTF(IEW, "[tid:%i]: Cannot remove skidbuffer instructions " @@ -479,11 +479,7 @@ DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid) toCommit->mispredPC[tid] = inst->readPC(); toCommit->branchMispredict[tid] = true; -#if THE_ISA == ALPHA_ISA - toCommit->branchTaken[tid] = inst->readNextPC() != - (inst->readPC() + sizeof(TheISA::MachInst)); - toCommit->nextPC[tid] = inst->readNextPC(); -#else +#if ISA_HAS_DELAY_SLOT bool branch_taken = inst->readNextNPC() != (inst->readNextPC() + sizeof(TheISA::MachInst)); @@ -496,6 +492,10 @@ DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid) } else { toCommit->nextPC[tid] = inst->readNextNPC(); } +#else + toCommit->branchTaken[tid] = inst->readNextPC() != + (inst->readPC() + sizeof(TheISA::MachInst)); + toCommit->nextPC[tid] = inst->readNextPC(); #endif toCommit->includeSquashInst[tid] = false; @@ -860,7 +860,7 @@ DefaultIEW<Impl>::sortInsts() { int insts_from_rename = fromRename->size; #ifdef DEBUG -#if THE_ISA == ALPHA_ISA +#if !ISA_HAS_DELAY_SLOT for (int i = 0; i < numThreads; i++) assert(insts[i].empty()); #endif @@ -878,8 +878,7 @@ DefaultIEW<Impl>::emptyRenameInsts(unsigned tid) "[sn:%i].\n", tid, bdelayDoneSeqNum[tid]); while (!insts[tid].empty()) { - -#if THE_ISA != ALPHA_ISA +#if ISA_HAS_DELAY_SLOT if (insts[tid].front()->seqNum <= bdelayDoneSeqNum[tid]) { DPRINTF(IEW, "[tid:%i]: Done removing, cannot remove instruction" " that occurs at or before delay slot [sn:%i].\n", @@ -1316,12 +1315,12 @@ DefaultIEW<Impl>::executeInsts() fetchRedirect[tid] = true; DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); -#if THE_ISA == ALPHA_ISA +#if ISA_HAS_DELAY_SLOT DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n", - inst->nextPC); + inst->nextNPC); #else DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n", - inst->nextNPC); + inst->nextPC); #endif // If incorrect, then signal the ROB that it must be squashed. squashDueToBranch(inst, tid); diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh index e7991662b..47634f645 100644 --- a/src/cpu/o3/inst_queue_impl.hh +++ b/src/cpu/o3/inst_queue_impl.hh @@ -991,10 +991,10 @@ InstructionQueue<Impl>::squash(unsigned tid) // Read instruction sequence number of last instruction out of the // time buffer. -#if THE_ISA == ALPHA_ISA - squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; -#else +#if ISA_HAS_DELAY_SLOT squashedSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum; +#else + squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; #endif // Call doSquash if there are insts in the IQ diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh index 892eb12cf..782c0fe5f 100644 --- a/src/cpu/o3/rename_impl.hh +++ b/src/cpu/o3/rename_impl.hh @@ -355,9 +355,7 @@ DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid) // "insts[tid].clear();" or "skidBuffer[tid].clear()" since there is // a possible delay slot inst for different architectures // insts[tid].clear(); -#if THE_ISA == ALPHA_ISA - insts[tid].clear(); -#else +#if ISA_HAS_DELAY_SLOT DPRINTF(Rename, "[tid:%i] Squashing incoming decode instructions until " "[sn:%i].\n",tid, squash_seq_num); ListIt ilist_it = insts[tid].begin(); @@ -369,14 +367,14 @@ DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid) } ilist_it++; } +#else + insts[tid].clear(); #endif // Clear the skid buffer in case it has any data in it. // See comments above. // skidBuffer[tid].clear(); -#if THE_ISA == ALPHA_ISA - skidBuffer[tid].clear(); -#else +#if ISA_HAS_DELAY_SLOT DPRINTF(Rename, "[tid:%i] Squashing incoming skidbuffer instructions " "until [sn:%i].\n", tid, squash_seq_num); ListIt slist_it = skidBuffer[tid].begin(); @@ -388,6 +386,8 @@ DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid) } slist_it++; } +#else + skidBuffer[tid].clear(); #endif doSquash(squash_seq_num, tid); } @@ -743,7 +743,7 @@ DefaultRename<Impl>::sortInsts() { int insts_from_decode = fromDecode->size; #ifdef DEBUG -#if THE_ISA == ALPHA_ISA +#if !ISA_HAS_DELAY_SLOT for (int i=0; i < numThreads; i++) assert(insts[i].empty()); #endif @@ -1182,10 +1182,10 @@ DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid) DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " "commit.\n", tid); -#if THE_ISA == ALPHA_ISA - InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum; -#else +#if ISA_HAS_DELAY_SLOT InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].bdelayDoneSeqNum; +#else + InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum; #endif squash(squashed_seq_num, tid); diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 801c96c88..22a210115 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -358,12 +358,12 @@ Fault BaseSimpleCPU::setupFetchRequest(Request *req) { // set up memory request for instruction fetch -#if THE_ISA == ALPHA_ISA - DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(), - thread->readNextPC()); -#else +#if ISA_HAS_DELAY_SLOT DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",thread->readPC(), thread->readNextPC(),thread->readNextNPC()); +#else + DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(), + thread->readNextPC()); #endif req->setVirt(0, thread->readPC() & ~3, sizeof(MachInst), @@ -450,12 +450,12 @@ BaseSimpleCPU::advancePC(Fault fault) else { // go to the next instruction thread->setPC(thread->readNextPC()); -#if THE_ISA == ALPHA_ISA - thread->setNextPC(thread->readNextPC() + sizeof(MachInst)); -#else +#if ISA_HAS_DELAY_SLOT thread->setNextPC(thread->readNextNPC()); thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst)); assert(thread->readNextPC() != thread->readNextNPC()); +#else + thread->setNextPC(thread->readNextPC() + sizeof(MachInst)); #endif } diff --git a/tests/SConscript b/tests/SConscript index b538ec557..1228e78d2 100644 --- a/tests/SConscript +++ b/tests/SConscript @@ -207,7 +207,7 @@ if env['FULL_SYSTEM']: 'tsunami-simple-atomic-dual', 'tsunami-simple-timing-dual'] else: - configs += ['simple-atomic', 'simple-timing'] + configs += ['simple-atomic', 'simple-timing', 'o3-timing'] cwd = os.getcwd() os.chdir(str(Dir('.').srcdir)) diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py new file mode 100644 index 000000000..227e1ba21 --- /dev/null +++ b/tests/configs/o3-timing.py @@ -0,0 +1,52 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Steve Reinhardt + +import m5 +from m5.objects import * +m5.AddToPath('../configs/common') +from FullO3Config import * + +class MyCache(BaseCache): + assoc = 2 + block_size = 64 + latency = 1 + mshrs = 10 + tgts_per_mshr = 5 + +cpu = DetailedO3CPU() +cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), + MyCache(size = '2MB')) +cpu.mem = cpu.dcache + +system = System(cpu = cpu, + physmem = PhysicalMemory(), + membus = Bus()) +system.physmem.port = system.membus.port +cpu.connectMemPorts(system.membus) + +root = Root(system = system) diff --git a/tests/diff-out b/tests/diff-out index 5ebe97dd7..1308eccfb 100755 --- a/tests/diff-out +++ b/tests/diff-out @@ -398,8 +398,8 @@ if ($added_stats) } cleanup(); -# Exit code is 0 if no stats error, 1 otherwise -$status = ($max_err_mag == 0.0) ? 0 : 1; +# Exit code is 0 if some stats found & no stats error, 1 otherwise +$status = ($#key_stats >= 0 && $max_err_mag == 0.0) ? 0 : 1; exit $status; sub cleanup diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini new file mode 100644 index 000000000..2b85e53f6 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -0,0 +1,406 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=DerivO3CPU +children=dcache fuPool icache l2cache toL2Bus workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +choiceCtrBits=2 +choicePredictorSize=8192 +clock=1 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.cpu.dcache +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +predType=tournament +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +squashWidth=8 +system=system +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList0 +count=6 +opList=system.cpu.fuPool.FUList0.opList0 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList4.opList0 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList5.opList0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 +count=1 +opList=system.cpu.fuPool.FUList7.opList0 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out new file mode 100644 index 000000000..f491a3081 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out @@ -0,0 +1,403 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +env= +system=system + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +opClass=IntAlu +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList0] +type=FUDesc +opList=system.cpu.fuPool.FUList0.opList0 +count=6 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +opClass=IntMult +opLat=3 +issueLat=1 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +opClass=IntDiv +opLat=20 +issueLat=19 + +[system.cpu.fuPool.FUList1] +type=FUDesc +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 +count=2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +opClass=FloatAdd +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +opClass=FloatCmp +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +opClass=FloatCvt +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2] +type=FUDesc +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 +count=4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +opClass=FloatMult +opLat=4 +issueLat=1 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +opClass=FloatDiv +opLat=12 +issueLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +opClass=FloatSqrt +opLat=24 +issueLat=24 + +[system.cpu.fuPool.FUList3] +type=FUDesc +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +count=2 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList4] +type=FUDesc +opList=system.cpu.fuPool.FUList4.opList0 +count=0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +opList=system.cpu.fuPool.FUList5.opList0 +count=0 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +count=4 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +opClass=IprAccess +opLat=3 +issueLat=3 + +[system.cpu.fuPool.FUList7] +type=FUDesc +opList=system.cpu.fuPool.FUList7.opList0 +count=1 + +[system.cpu.fuPool] +type=FUPool +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu] +type=DerivO3CPU +clock=1 +numThreads=1 +activity=0 +workload=system.cpu.workload +mem=system.cpu.dcache +checker=null +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +cachePorts=200 +decodeToFetchDelay=1 +renameToFetchDelay=1 +iewToFetchDelay=1 +commitToFetchDelay=1 +fetchWidth=8 +renameToDecodeDelay=1 +iewToDecodeDelay=1 +commitToDecodeDelay=1 +fetchToDecodeDelay=1 +decodeWidth=8 +iewToRenameDelay=1 +commitToRenameDelay=1 +decodeToRenameDelay=1 +renameWidth=8 +commitToIEWDelay=1 +renameToIEWDelay=2 +issueToExecuteDelay=1 +dispatchWidth=8 +issueWidth=8 +wbWidth=8 +wbDepth=1 +fuPool=system.cpu.fuPool +iewToCommitDelay=1 +renameToROBDelay=1 +commitWidth=8 +squashWidth=8 +trapLatency=13 +backComSize=5 +forwardComSize=5 +predType=tournament +localPredictorSize=2048 +localCtrBits=2 +localHistoryTableSize=2048 +localHistoryBits=11 +globalPredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +choicePredictorSize=8192 +choiceCtrBits=2 +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +LQEntries=32 +SQEntries=32 +LFSTSize=1024 +SSITSize=1024 +numPhysIntRegs=256 +numPhysFloatRegs=256 +numIQEntries=64 +numROBEntries=192 +smtNumFetchingThreads=1 +smtFetchPolicy=SingleThread +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtROBPolicy=Partitioned +smtROBThreshold=100 +smtCommitPolicy=RoundRobin +instShiftAmt=2 +defer_registration=false +function_trace=false +function_trace_start=0 + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt new file mode 100644 index 000000000..3814e38d1 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -0,0 +1,1974 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 542 # Number of BTB hits +global.BPredUnit.BTBLookups 1938 # Number of BTB lookups +global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted +global.BPredUnit.lookups 2256 # Number of BP lookups +global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. +host_inst_rate 34296 # Simulator instruction rate (inst/s) +host_mem_usage 160076 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host +host_tick_rate 41824 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 5623 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 6870 # Number of ticks simulated +system.cpu.commit.COM:branches 862 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 6116 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 3908 6389.80% + 1 1064 1739.70% + 2 389 636.04% + 3 210 343.36% + 4 153 250.16% + 5 93 152.06% + 6 76 124.26% + 7 149 243.62% + 8 74 120.99% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 5640 # Number of instructions committed +system.cpu.commit.COM:loads 979 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 1791 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit +system.cpu.committedInsts 5623 # Number of Instructions Simulated +system.cpu.committedInsts_total 5623 # Number of Instructions Simulated +system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses +system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 2048 # number of overall hits +system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses +system.cpu.dcache.overall_misses 311 # number of overall misses +system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use +system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched +system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 6871 +system.cpu.fetch.rateDist.min_value 0 + 0 4549 6620.58% + 1 174 253.24% + 2 186 270.70% + 3 157 228.50% + 4 211 307.09% + 5 153 222.68% + 6 171 248.87% + 7 105 152.82% + 8 1165 1695.53% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses +system.cpu.icache.demand_misses 327 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 1255 # number of overall hits +system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses +system.cpu.icache.overall_misses 327 # number of overall misses +system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use +system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.iew.EXEC:branches 1206 # Number of branches executed +system.cpu.iew.EXEC:insts 7969 # Number of executed instructions +system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed +system.cpu.iew.EXEC:nop 37 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate +system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed +system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute +system.cpu.iew.EXEC:stores 989 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 5438 # num instructions consuming a value +system.cpu.iew.WB:count 7722 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 4049 # num instructions producing a value +system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle +system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads +system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:(null).samples 0 +system.cpu.iq.IQ:residence:(null).min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:(null).max_value 0 +system.cpu.iq.IQ:residence:(null).end_dist + +system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntAlu.samples 0 +system.cpu.iq.IQ:residence:IntAlu.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntAlu.max_value 0 +system.cpu.iq.IQ:residence:IntAlu.end_dist + +system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntMult.samples 0 +system.cpu.iq.IQ:residence:IntMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntMult.max_value 0 +system.cpu.iq.IQ:residence:IntMult.end_dist + +system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntDiv.samples 0 +system.cpu.iq.IQ:residence:IntDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntDiv.max_value 0 +system.cpu.iq.IQ:residence:IntDiv.end_dist + +system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatAdd.samples 0 +system.cpu.iq.IQ:residence:FloatAdd.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatAdd.max_value 0 +system.cpu.iq.IQ:residence:FloatAdd.end_dist + +system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCmp.samples 0 +system.cpu.iq.IQ:residence:FloatCmp.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCmp.max_value 0 +system.cpu.iq.IQ:residence:FloatCmp.end_dist + +system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCvt.samples 0 +system.cpu.iq.IQ:residence:FloatCvt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCvt.max_value 0 +system.cpu.iq.IQ:residence:FloatCvt.end_dist + +system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatMult.samples 0 +system.cpu.iq.IQ:residence:FloatMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatMult.max_value 0 +system.cpu.iq.IQ:residence:FloatMult.end_dist + +system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatDiv.samples 0 +system.cpu.iq.IQ:residence:FloatDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatDiv.max_value 0 +system.cpu.iq.IQ:residence:FloatDiv.end_dist + +system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatSqrt.samples 0 +system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 +system.cpu.iq.IQ:residence:FloatSqrt.end_dist + +system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemRead.samples 0 +system.cpu.iq.IQ:residence:MemRead.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemRead.max_value 0 +system.cpu.iq.IQ:residence:MemRead.end_dist + +system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemWrite.samples 0 +system.cpu.iq.IQ:residence:MemWrite.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemWrite.max_value 0 +system.cpu.iq.IQ:residence:MemWrite.end_dist + +system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IprAccess.samples 0 +system.cpu.iq.IQ:residence:IprAccess.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IprAccess.max_value 0 +system.cpu.iq.IQ:residence:IprAccess.end_dist + +system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:InstPrefetch.samples 0 +system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 +system.cpu.iq.IQ:residence:InstPrefetch.end_dist + +system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:(null)_delay.samples 0 +system.cpu.iq.ISSUE:(null)_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:(null)_delay.max_value 0 +system.cpu.iq.ISSUE:(null)_delay.end_dist + +system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntAlu_delay.samples 0 +system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 +system.cpu.iq.ISSUE:IntAlu_delay.end_dist + +system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntMult_delay.samples 0 +system.cpu.iq.ISSUE:IntMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntMult_delay.max_value 0 +system.cpu.iq.ISSUE:IntMult_delay.end_dist + +system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntDiv_delay.samples 0 +system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 +system.cpu.iq.ISSUE:IntDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 +system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 +system.cpu.iq.ISSUE:FloatAdd_delay.end_dist + +system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 +system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCmp_delay.end_dist + +system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 +system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCvt_delay.end_dist + +system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatMult_delay.samples 0 +system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 +system.cpu.iq.ISSUE:FloatMult_delay.end_dist + +system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 +system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 +system.cpu.iq.ISSUE:FloatDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist + +system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemRead_delay.samples 0 +system.cpu.iq.ISSUE:MemRead_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemRead_delay.max_value 0 +system.cpu.iq.ISSUE:MemRead_delay.end_dist + +system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemWrite_delay.samples 0 +system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 +system.cpu.iq.ISSUE:MemWrite_delay.end_dist + +system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IprAccess_delay.samples 0 +system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 +system.cpu.iq.ISSUE:IprAccess_delay.end_dist + +system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist + +system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + (null) 2 0.02% # Type of FU issued + IntAlu 5594 66.69% # Type of FU issued + IntMult 1 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 1757 20.95% # Type of FU issued + MemWrite 1032 12.30% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + (null) 0 0.00% # attempts to use FU when none available + IntAlu 1 0.87% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 76 66.09% # attempts to use FU when none available + MemWrite 38 33.04% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 3753 5462.09% + 1 894 1301.12% + 2 723 1052.25% + 3 614 893.61% + 4 451 656.38% + 5 279 406.05% + 6 104 151.36% + 7 41 59.67% + 8 12 17.46% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate +system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.numCycles 6871 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed +system.cpu.workload.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr new file mode 100644 index 000000000..8893caac8 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr @@ -0,0 +1,3 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 +warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout new file mode 100644 index 000000000..907b15392 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -0,0 +1,13 @@ +Hello world! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Sep 1 2006 16:10:44 +M5 started Fri Sep 1 16:23:41 2006 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing +Exiting @ tick 6870 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini new file mode 100644 index 000000000..388ddf7b6 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -0,0 +1,406 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=DerivO3CPU +children=dcache fuPool icache l2cache toL2Bus workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +choiceCtrBits=2 +choicePredictorSize=8192 +clock=1 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.cpu.dcache +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +predType=tournament +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +squashWidth=8 +system=system +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList0 +count=6 +opList=system.cpu.fuPool.FUList0.opList0 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList4.opList0 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList5.opList0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 +count=1 +opList=system.cpu.fuPool.FUList7.opList0 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +env= +executable=tests/test-progs/hello/bin/alpha/tru64/hello +input=cin +output=cout +system=system + +[system.membus] +type=Bus +bus_id=0 + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 + +[trace] +bufsize=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out new file mode 100644 index 000000000..474ea3523 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out @@ -0,0 +1,403 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/alpha/tru64/hello +input=cin +output=cout +env= +system=system + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +opClass=IntAlu +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList0] +type=FUDesc +opList=system.cpu.fuPool.FUList0.opList0 +count=6 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +opClass=IntMult +opLat=3 +issueLat=1 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +opClass=IntDiv +opLat=20 +issueLat=19 + +[system.cpu.fuPool.FUList1] +type=FUDesc +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 +count=2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +opClass=FloatAdd +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +opClass=FloatCmp +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +opClass=FloatCvt +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2] +type=FUDesc +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 +count=4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +opClass=FloatMult +opLat=4 +issueLat=1 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +opClass=FloatDiv +opLat=12 +issueLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +opClass=FloatSqrt +opLat=24 +issueLat=24 + +[system.cpu.fuPool.FUList3] +type=FUDesc +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +count=2 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList4] +type=FUDesc +opList=system.cpu.fuPool.FUList4.opList0 +count=0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +opList=system.cpu.fuPool.FUList5.opList0 +count=0 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +count=4 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +opClass=IprAccess +opLat=3 +issueLat=3 + +[system.cpu.fuPool.FUList7] +type=FUDesc +opList=system.cpu.fuPool.FUList7.opList0 +count=1 + +[system.cpu.fuPool] +type=FUPool +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu] +type=DerivO3CPU +clock=1 +numThreads=1 +activity=0 +workload=system.cpu.workload +mem=system.cpu.dcache +checker=null +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +cachePorts=200 +decodeToFetchDelay=1 +renameToFetchDelay=1 +iewToFetchDelay=1 +commitToFetchDelay=1 +fetchWidth=8 +renameToDecodeDelay=1 +iewToDecodeDelay=1 +commitToDecodeDelay=1 +fetchToDecodeDelay=1 +decodeWidth=8 +iewToRenameDelay=1 +commitToRenameDelay=1 +decodeToRenameDelay=1 +renameWidth=8 +commitToIEWDelay=1 +renameToIEWDelay=2 +issueToExecuteDelay=1 +dispatchWidth=8 +issueWidth=8 +wbWidth=8 +wbDepth=1 +fuPool=system.cpu.fuPool +iewToCommitDelay=1 +renameToROBDelay=1 +commitWidth=8 +squashWidth=8 +trapLatency=13 +backComSize=5 +forwardComSize=5 +predType=tournament +localPredictorSize=2048 +localCtrBits=2 +localHistoryTableSize=2048 +localHistoryBits=11 +globalPredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +choicePredictorSize=8192 +choiceCtrBits=2 +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +LQEntries=32 +SQEntries=32 +LFSTSize=1024 +SSITSize=1024 +numPhysIntRegs=256 +numPhysFloatRegs=256 +numIQEntries=64 +numROBEntries=192 +smtNumFetchingThreads=1 +smtFetchPolicy=SingleThread +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtROBPolicy=Partitioned +smtROBThreshold=100 +smtCommitPolicy=RoundRobin +instShiftAmt=2 +defer_registration=false +function_trace=false +function_trace_start=0 + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[trace] +flags= +start=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt new file mode 100644 index 000000000..5c59263ac --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -0,0 +1,1972 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 155 # Number of BTB hits +global.BPredUnit.BTBLookups 711 # Number of BTB lookups +global.BPredUnit.RASInCorrect 37 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 222 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 441 # Number of conditional branches predicted +global.BPredUnit.lookups 888 # Number of BP lookups +global.BPredUnit.usedRAS 160 # Number of times the RAS was used to get a target. +host_inst_rate 22611 # Simulator instruction rate (inst/s) +host_mem_usage 159596 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host +host_tick_rate 27259 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 9 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 675 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 369 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 2387 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 2886 # Number of ticks simulated +system.cpu.commit.COM:branches 396 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 40 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 2646 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 1713 6473.92% + 1 239 903.25% + 2 322 1216.93% + 3 139 525.32% + 4 78 294.78% + 5 67 253.21% + 6 27 102.04% + 7 21 79.37% + 8 40 151.17% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 2576 # Number of instructions committed +system.cpu.commit.COM:loads 415 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 709 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 138 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 1258 # The number of squashed insts skipped by commit +system.cpu.committedInsts 2387 # Number of Instructions Simulated +system.cpu.committedInsts_total 2387 # Number of Instructions Simulated +system.cpu.cpi 1.209049 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.209049 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 535 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 470 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 195 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.121495 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 65 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 4 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 122 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.114019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3.017241 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.208333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 236 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 175 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.197279 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 58 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 34 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 53 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 1.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 8.305882 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 2 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 3 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 829 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3.008130 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2.058824 # average overall mshr miss latency +system.cpu.dcache.demand_hits 706 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 370 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.148372 # miss rate for demand accesses +system.cpu.dcache.demand_misses 123 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 38 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 175 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.102533 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 829 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3.008130 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2.058824 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 706 # number of overall hits +system.cpu.dcache.overall_miss_latency 370 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.148372 # miss rate for overall accesses +system.cpu.dcache.overall_misses 123 # number of overall misses +system.cpu.dcache.overall_mshr_hits 38 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 175 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.102533 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 54.161413 # Cycle average of tags in use +system.cpu.dcache.total_refs 706 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 82 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 90 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 156 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 4646 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 1691 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 873 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 240 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 315 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 888 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 740 # Number of cache lines fetched +system.cpu.fetch.Cycles 1663 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 77 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 5518 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 235 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.307586 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 740 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 315 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.911327 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 2887 +system.cpu.fetch.rateDist.min_value 0 + 0 1965 6806.37% + 1 36 124.70% + 2 79 273.64% + 3 66 228.61% + 4 125 432.98% + 5 60 207.83% + 6 40 138.55% + 7 42 145.48% + 8 474 1641.84% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 740 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2.989474 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 550 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 568 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.256757 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 190 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 378 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.255405 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 189 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 2.910053 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 740 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2.989474 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency +system.cpu.icache.demand_hits 550 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 568 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.256757 # miss rate for demand accesses +system.cpu.icache.demand_misses 190 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 1 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 378 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.255405 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 189 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 740 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2.989474 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 550 # number of overall hits +system.cpu.icache.overall_miss_latency 568 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.256757 # miss rate for overall accesses +system.cpu.icache.overall_misses 190 # number of overall misses +system.cpu.icache.overall_mshr_hits 1 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 378 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.255405 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 189 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.sampled_refs 189 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 115.538968 # Cycle average of tags in use +system.cpu.icache.total_refs 550 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.iew.EXEC:branches 533 # Number of branches executed +system.cpu.iew.EXEC:insts 3123 # Number of executed instructions +system.cpu.iew.EXEC:loads 578 # Number of load instructions executed +system.cpu.iew.EXEC:nop 247 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.081746 # Inst execution rate +system.cpu.iew.EXEC:refs 914 # number of memory reference insts executed +system.cpu.iew.EXEC:squashedInsts 148 # Number of squashed instructions skipped in execute +system.cpu.iew.EXEC:stores 336 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.WB:consumers 1801 # num instructions consuming a value +system.cpu.iew.WB:count 3070 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.791227 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 1425 # num instructions producing a value +system.cpu.iew.WB:rate 1.063388 # insts written-back per cycle +system.cpu.iew.WB:sent 3076 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 159 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 675 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 7 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 127 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 369 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 3835 # Number of instructions dispatched to IQ +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 240 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 2 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 30 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 260 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 75 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 106 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.827096 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.827096 # IPC: Total IPC of All Threads +system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:(null).samples 0 +system.cpu.iq.IQ:residence:(null).min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:(null).max_value 0 +system.cpu.iq.IQ:residence:(null).end_dist + +system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntAlu.samples 0 +system.cpu.iq.IQ:residence:IntAlu.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntAlu.max_value 0 +system.cpu.iq.IQ:residence:IntAlu.end_dist + +system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntMult.samples 0 +system.cpu.iq.IQ:residence:IntMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntMult.max_value 0 +system.cpu.iq.IQ:residence:IntMult.end_dist + +system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IntDiv.samples 0 +system.cpu.iq.IQ:residence:IntDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IntDiv.max_value 0 +system.cpu.iq.IQ:residence:IntDiv.end_dist + +system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatAdd.samples 0 +system.cpu.iq.IQ:residence:FloatAdd.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatAdd.max_value 0 +system.cpu.iq.IQ:residence:FloatAdd.end_dist + +system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCmp.samples 0 +system.cpu.iq.IQ:residence:FloatCmp.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCmp.max_value 0 +system.cpu.iq.IQ:residence:FloatCmp.end_dist + +system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatCvt.samples 0 +system.cpu.iq.IQ:residence:FloatCvt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatCvt.max_value 0 +system.cpu.iq.IQ:residence:FloatCvt.end_dist + +system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatMult.samples 0 +system.cpu.iq.IQ:residence:FloatMult.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatMult.max_value 0 +system.cpu.iq.IQ:residence:FloatMult.end_dist + +system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatDiv.samples 0 +system.cpu.iq.IQ:residence:FloatDiv.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatDiv.max_value 0 +system.cpu.iq.IQ:residence:FloatDiv.end_dist + +system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:FloatSqrt.samples 0 +system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 +system.cpu.iq.IQ:residence:FloatSqrt.end_dist + +system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemRead.samples 0 +system.cpu.iq.IQ:residence:MemRead.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemRead.max_value 0 +system.cpu.iq.IQ:residence:MemRead.end_dist + +system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:MemWrite.samples 0 +system.cpu.iq.IQ:residence:MemWrite.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:MemWrite.max_value 0 +system.cpu.iq.IQ:residence:MemWrite.end_dist + +system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:IprAccess.samples 0 +system.cpu.iq.IQ:residence:IprAccess.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:IprAccess.max_value 0 +system.cpu.iq.IQ:residence:IprAccess.end_dist + +system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue +system.cpu.iq.IQ:residence:InstPrefetch.samples 0 +system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 +system.cpu.iq.IQ:residence:InstPrefetch.end_dist + +system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:(null)_delay.samples 0 +system.cpu.iq.ISSUE:(null)_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:(null)_delay.max_value 0 +system.cpu.iq.ISSUE:(null)_delay.end_dist + +system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntAlu_delay.samples 0 +system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 +system.cpu.iq.ISSUE:IntAlu_delay.end_dist + +system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntMult_delay.samples 0 +system.cpu.iq.ISSUE:IntMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntMult_delay.max_value 0 +system.cpu.iq.ISSUE:IntMult_delay.end_dist + +system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IntDiv_delay.samples 0 +system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 +system.cpu.iq.ISSUE:IntDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 +system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 +system.cpu.iq.ISSUE:FloatAdd_delay.end_dist + +system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 +system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCmp_delay.end_dist + +system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 +system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatCvt_delay.end_dist + +system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatMult_delay.samples 0 +system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 +system.cpu.iq.ISSUE:FloatMult_delay.end_dist + +system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 +system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 +system.cpu.iq.ISSUE:FloatDiv_delay.end_dist + +system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 +system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist + +system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemRead_delay.samples 0 +system.cpu.iq.ISSUE:MemRead_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemRead_delay.max_value 0 +system.cpu.iq.ISSUE:MemRead_delay.end_dist + +system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:MemWrite_delay.samples 0 +system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 +system.cpu.iq.ISSUE:MemWrite_delay.end_dist + +system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:IprAccess_delay.samples 0 +system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 +system.cpu.iq.ISSUE:IprAccess_delay.end_dist + +system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue +system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 + 0 0 + 2 0 + 4 0 + 6 0 + 8 0 + 10 0 + 12 0 + 14 0 + 16 0 + 18 0 + 20 0 + 22 0 + 24 0 + 26 0 + 28 0 + 30 0 + 32 0 + 34 0 + 36 0 + 38 0 + 40 0 + 42 0 + 44 0 + 46 0 + 48 0 + 50 0 + 52 0 + 54 0 + 56 0 + 58 0 + 60 0 + 62 0 + 64 0 + 66 0 + 68 0 + 70 0 + 72 0 + 74 0 + 76 0 + 78 0 + 80 0 + 82 0 + 84 0 + 86 0 + 88 0 + 90 0 + 92 0 + 94 0 + 96 0 + 98 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 +system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist + +system.cpu.iq.ISSUE:FU_type_0 3271 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + (null) 0 0.00% # Type of FU issued + IntAlu 2317 70.83% # Type of FU issued + IntMult 1 0.03% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 0 0.00% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 609 18.62% # Type of FU issued + MemWrite 344 10.52% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 40 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.012229 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + (null) 0 0.00% # attempts to use FU when none available + IntAlu 5 12.50% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 12 30.00% # attempts to use FU when none available + MemWrite 23 57.50% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 2887 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 1603 5552.48% + 1 434 1503.29% + 2 301 1042.60% + 3 220 762.04% + 4 167 578.46% + 5 94 325.60% + 6 46 159.33% + 7 15 51.96% + 8 7 24.25% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.133010 # Inst issue rate +system.cpu.iq.iqInstsAdded 3581 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 3271 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 7 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 1067 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 477 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 274 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2.018248 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 553 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 274 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 274 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 274 # number of ReadReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 274 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2.018248 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 553 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 274 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 274 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 274 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 274 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2.018248 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 0 # number of overall hits +system.cpu.l2cache.overall_miss_latency 553 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 274 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 274 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 274 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.sampled_refs 274 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 169.795289 # Cycle average of tags in use +system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.numCycles 2887 # number of cpu cycles simulated +system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 1780 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 4975 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 4400 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 3144 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 785 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 240 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 8 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1376 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 74 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 10 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 62 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 8 # count of temporary serializing insts renamed +system.cpu.workload.PROG:num_syscalls 4 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr new file mode 100644 index 000000000..688d89868 --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr @@ -0,0 +1,4 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 +warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff8 +warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout new file mode 100644 index 000000000..04a06d3ab --- /dev/null +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout @@ -0,0 +1,13 @@ +Hello world! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Sep 1 2006 16:10:44 +M5 started Fri Sep 1 16:23:45 2006 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing +Exiting @ tick 2886 because target called exit() diff --git a/util/regress b/util/regress index 27880d527..4d07f81a9 100755 --- a/util/regress +++ b/util/regress @@ -32,39 +32,20 @@ import os import optparse import datetime -# -# Regression invocation: -# -# regress \ -# --workdir poolfs \ -# --scons-opts 'BATCH=yes USE_MYSQL=no -j 30 -Q' \ -# --recurse - progname = os.path.basename(sys.argv[0]) optparser = optparse.OptionParser() optparser.add_option('-v', '--verbose', dest='verbose', action='store_true', default=False, help='echo commands before executing') -optparser.add_option('--scratch', dest='scratch', action='store_true', - default=False, - help='rebuld from scratch') optparser.add_option('--builds', dest='builds', default='ALPHA_SE,ALPHA_FS,MIPS_SE,SPARC_SE', help='comma-separated list of builds to test') optparser.add_option('--variants', dest='variants', default='opt', help='comma-separated list of build variants to test') -optparser.add_option('--workdir', dest='workdir', - help='directory for checked-out source trees') optparser.add_option('--scons-opts', dest='scons_opts', default='', help='scons options') -optparser.add_option('--no-pull', dest='pull', action='store_false', - default=True, - help="don't pull changes from repository") -optparser.add_option('--recurse', dest='recurse', action='store_true', - default=False, - help='call recursively to get summary up front') (options, tests) = optparser.parse_args() @@ -73,9 +54,6 @@ optparser.add_option('--recurse', dest='recurse', action='store_true', builds = options.builds.split(',') variants = options.variants.split(',') -# Repositories to clone/update -repos = ['m5'] - # Call os.system() and raise exception if return status is non-zero def system(cmd): if options.verbose: @@ -93,56 +71,11 @@ def shellquote(s): s = "'%s'" % s return s -# The '--recurse' option invokes scons once to perform any necessary -# rebuilds/test runs with the (possibly verbose) output placed in a -# log file, then (if the buld was successful) returns scons to print a -# summary of the results. -if options.recurse: - sys.argv.remove('--recurse') # avoid infinite recursion... - timestr = datetime.datetime.now().isoformat('-')[:19] - logfile = '%s-%s' % (progname, timestr) - # quote args for shell - qargs = [shellquote(a) for a in sys.argv] - # always run the sub-job in verbose mode - qargs.append('-v') - cmd = '%s > %s 2>&1' % (' '.join(qargs), logfile) - try: - system(cmd) - except OSError, exc: - print "Error: recursive invocation failed, aborting." - print exc - print "=======================" - os.system('cat %s' % logfile) - sys.exit(1) - # recursive call succeeded... re-run to generate summary - # don't *re*-build from scratch now - options.scratch = False - # no need to re-pull since the recursive call shoudl have done that - options.pull = False - print "Recursive invocation successful, see %s for output." % logfile - try: - if options.workdir: - if options.verbose: - print 'cd', options.workdir - os.chdir(options.workdir) - - if options.scratch: - for dir in repos: - system('rm -rf %s' % dir) - system('bk clone /bk/%s' % dir) - elif options.pull: - for dir in repos: - system('cd %s; bk pull' % dir) - if not tests: print "No tests specified." sys.exit(1) - if options.verbose: - print 'cd m5' - os.chdir('m5') - if 'all' in tests: targets = ['build/%s/tests/%s' % (build, variant) for build in builds |