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author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-06-02 12:58:12 -0500 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-06-02 12:58:12 -0500 |
commit | b504b44b2f3dec833f725ee3cb343e7bcbda0a05 (patch) | |
tree | 3497b2b28c3e107f8479460eef7893672b91da71 | |
parent | 943b77b9bbb7d7057c18f1f0eb9789c0082f872f (diff) | |
download | gem5-b504b44b2f3dec833f725ee3cb343e7bcbda0a05.tar.xz |
CPU: Reset fetch offset after a exception
-rw-r--r-- | src/cpu/simple/base.cc | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index d15b84bd6..7a063d9d7 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -1,4 +1,16 @@ /* + * Copyright (c) 2010 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2002-2005 The Regents of The University of Michigan * All rights reserved. * @@ -346,6 +358,7 @@ BaseSimpleCPU::checkForInterrupts() if (interrupt != NoFault) { predecoder.reset(); + fetchOffset = 0; interrupts->updateIntrInfo(tc); interrupt->invoke(tc); } |