Build options are set via a build_options file in the

build directory instead of being inferred from the name
of the build directory.
Options are passed to C++ via config/*.hh files instead of
via the command line.  Build option flags are now always
defined to 0 or 1, so checks must use '#if' rather than
'#ifdef'.

SConscript:
    MySQL detection moved to SConstruct.
    Add config/*.hh files (via ConfigFile builder).
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/isa_traits.hh:
base/fast_alloc.hh:
base/statistics.cc:
base/statistics.hh:
base/stats/events.cc:
base/stats/events.hh:
cpu/base.cc:
cpu/base.hh:
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/o3/alpha_cpu.hh:
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/alpha_params.hh:
cpu/o3/commit_impl.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/fetch_impl.hh:
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
cpu/o3/regfile.hh:
cpu/o3/rename_impl.hh:
cpu/o3/rob_impl.hh:
cpu/ozone/cpu.hh:
cpu/pc_event.cc:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
sim/process.cc:
sim/process.hh:
    Convert compile flags from def/undef to 0/1.
    Set via #include config/*.hh instead of command line.
arch/alpha/isa_desc:
    Convert compile flags from def/undef to 0/1.
    Set via #include config/*.hh instead of command line.
    Revamp fenv.h support... most of the ugliness is hidden
    in base/fenv.hh now.
base/mysql.hh:
    Fix typo in #ifndef guard.
build/SConstruct:
    Build options are set via a build_options file in the
    build directory instead of being inferred from the name
    of the build directory.
    Options are passed to C++ via config/*.hh files instead of
    via the command line.
python/SConscript:
    Generate m5_build_env directly from scons options
    instead of indirectly via CPPDEFINES.
python/m5/convert.py:
    Allow '0' and '1' for booleans.
    Rewrite toBool to use dict.
base/fenv.hh:
    Revamp <fenv.h> support to make it a compile option
    (so we can test w/o it even if it's present) and to
    make isa_desc cleaner.

--HG--
extra : convert_revision : 8f97dc11185bef5e1865b3269c7341df8525c9ad

43 files changed, 360 insertions, 296 deletions

diff --git a/SConscript b/SConscript
index 13a0fe0df..518b8a0f3 100644
--- a/SConscript
+++ b/SConscript
@@ -366,18 +366,11 @@ if env['FULL_SYSTEM']:
 else:
     sources += syscall_emulation_sources
 
-extra_libraries = []
-env.Append(LIBS=['z'])
-if isdir('/usr/lib64/mysql') or isdir('/usr/lib/mysql') or \
-   isdir('/usr/local/lib/mysql'):
-    print 'Compiling with MySQL support!'
-    env.Append(LIBPATH=['/usr/lib64/mysql', '/usr/local/lib/mysql/',
-                        '/usr/lib/mysql'])
-    env.Append(CPPPATH=['/usr/local/include/mysql', '/usr/include/mysql'])
+if env['USE_MYSQL']:
     sources += mysql_sources
-    env.Append(CPPDEFINES = 'USE_MYSQL')
-    env.Append(CPPDEFINES = 'STATS_BINNING')
-    env.Append(LIBS=['mysqlclient'])
+
+for opt in env.ExportOptions:
+    env.ConfigFile(opt)
 
 ###################################################
 #
@@ -421,7 +414,6 @@ def make_objs(sources, env):
     date_obj = env.Object('base/date.cc')
     env.Depends(date_obj, objs)
     objs.append(date_obj)
-    objs.extend(extra_libraries)
     return objs
 
 ###################################################
diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc
index 906f60668..39c9397ea 100644
--- a/arch/alpha/alpha_memory.cc
+++ b/arch/alpha/alpha_memory.cc
@@ -34,6 +34,7 @@
 #include "base/inifile.hh"
 #include "base/str.hh"
 #include "base/trace.hh"
+#include "config/alpha_tlaser.hh"
 #include "cpu/exec_context.hh"
 #include "sim/builder.hh"
 
@@ -107,7 +108,7 @@ AlphaTLB::checkCacheability(MemReqPtr &req)
      */
 
 
-#ifdef ALPHA_TLASER
+#if ALPHA_TLASER
     if (req->paddr & PAddrUncachedBit39) {
 #else
     if (req->paddr & PAddrUncachedBit43) {
@@ -129,7 +130,7 @@ AlphaTLB::checkCacheability(MemReqPtr &req)
             // mark request as uncacheable
             req->flags |= UNCACHEABLE;
 
-#ifndef ALPHA_TLASER
+#if !ALPHA_TLASER
             // Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
             req->paddr &= PAddrUncachedMask;
 #endif
@@ -323,7 +324,7 @@ AlphaITB::translate(MemReqPtr &req) const
 
         // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
         // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
-#ifdef ALPHA_TLASER
+#if ALPHA_TLASER
         if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
             VAddrSpaceEV5(req->vaddr) == 2) {
 #else
@@ -339,7 +340,7 @@ AlphaITB::translate(MemReqPtr &req) const
 
             req->paddr = req->vaddr & PAddrImplMask;
 
-#ifndef ALPHA_TLASER
+#if !ALPHA_TLASER
             // sign extend the physical address properly
             if (req->paddr & PAddrUncachedBit40)
                 req->paddr |= ULL(0xf0000000000);
@@ -529,7 +530,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
         }
 
         // Check for "superpage" mapping
-#ifdef ALPHA_TLASER
+#if ALPHA_TLASER
         if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
             VAddrSpaceEV5(req->vaddr) == 2) {
 #else
@@ -547,7 +548,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
 
             req->paddr = req->vaddr & PAddrImplMask;
 
-#ifndef ALPHA_TLASER
+#if !ALPHA_TLASER
             // sign extend the physical address properly
             if (req->paddr & PAddrUncachedBit40)
                 req->paddr |= ULL(0xf0000000000);
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index 4ae688330..125affd03 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -32,6 +32,7 @@
 #include "base/kgdb.h"
 #include "base/remote_gdb.hh"
 #include "base/stats/events.hh"
+#include "config/full_system.hh"
 #include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/fast/cpu.hh"
@@ -39,7 +40,7 @@
 #include "sim/debug.hh"
 #include "sim/sim_events.hh"
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 
 using namespace EV5;
 
diff --git a/arch/alpha/ev5.hh b/arch/alpha/ev5.hh
index a5a76b5bd..5173b364f 100644
--- a/arch/alpha/ev5.hh
+++ b/arch/alpha/ev5.hh
@@ -29,9 +29,11 @@
 #ifndef __ARCH_ALPHA_EV5_HH__
 #define __ARCH_ALPHA_EV5_HH__
 
+#include "config/alpha_tlaser.hh"
+
 namespace EV5 {
 
-#ifdef ALPHA_TLASER
+#if ALPHA_TLASER
 const uint64_t AsnMask = ULL(0x7f);
 #else
 const uint64_t AsnMask = ULL(0xff);
@@ -46,7 +48,7 @@ inline Addr VAddrOffset(Addr a) { return a & AlphaISA::PageOffset; }
 inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; }
 inline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; }
 
-#ifdef ALPHA_TLASER
+#if ALPHA_TLASER
 inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); }
 const int PAddrImplBits = 40;
 #else
@@ -60,7 +62,7 @@ const Addr PAddrUncachedBit43 = ULL(0x80000000000);
 const Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35>
 inline Addr Phys2K0Seg(Addr addr)
 {
-#ifndef ALPHA_TLASER
+#if !ALPHA_TLASER
     if (addr & PAddrUncachedBit43) {
         addr &= PAddrUncachedMask;
         addr |= PAddrUncachedBit40;
diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index 12b2a4822..60ffbfd54 100644
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -45,30 +45,29 @@ output header {{
 #include <iostream>
 #include <iomanip>
 
+#include "config/ss_compatible_fp.hh"
 #include "cpu/static_inst.hh"
 #include "mem/mem_req.hh"  // some constructors use MemReq flags
 }};
 
 output decoder {{
 #include "base/cprintf.hh"
+#include "base/fenv.hh"
 #include "base/loader/symtab.hh"
+#include "config/ss_compatible_fp.hh"
 #include "cpu/exec_context.hh"  // for Jump::branchTarget()
 
 #include <math.h>
-#if defined(linux)
-#include <fenv.h>
-#endif
 }};
 
 output exec {{
 #include <math.h>
-#if defined(linux)
-#include <fenv.h>
-#endif
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 #include "arch/alpha/pseudo_inst.hh"
 #endif
+#include "base/fenv.hh"
+#include "config/ss_compatible_fp.hh"
 #include "cpu/base.hh"
 #include "cpu/exetrace.hh"
 #include "sim/sim_exit.hh"
@@ -542,7 +541,7 @@ output exec {{
     /// instruction in full-system mode.
     /// @retval Full-system mode: No_Fault if FP is enabled, Fen_Fault
     /// if not.  Non-full-system mode: always returns No_Fault.
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
     {
 	Fault fault = No_Fault;	// dummy... this ipr access should not fault
@@ -593,9 +592,8 @@ output header {{
 	};
 
       protected:
-#if defined(linux)
+	/// Map Alpha rounding mode to C99 constants from <fenv.h>.
 	static const int alphaToC99RoundingMode[];
-#endif
 
 	/// Map enum RoundingMode values to disassembly suffixes.
 	static const char *roundingModeSuffix[];
@@ -620,9 +618,7 @@ output header {{
 	    }
 	}
 
-#if defined(linux)
 	int getC99RoundingMode(uint64_t fpcr_val) const;
-#endif
 
 	// This differs from the AlphaStaticInst version only in
 	// printing suffixes for non-default rounding & trapping modes.
@@ -650,7 +646,6 @@ def template FloatingPointDecode {{
 }};
 
 output decoder {{
-#if defined(linux)
     int
     AlphaFP::getC99RoundingMode(uint64_t fpcr_val) const
     {
@@ -661,7 +656,6 @@ output decoder {{
 	    return alphaToC99RoundingMode[roundingMode];
 	}
     }
-#endif
 
     std::string
     AlphaFP::generateDisassembly(Addr pc, const SymbolTable *symtab) const
@@ -705,14 +699,12 @@ output decoder {{
 	return ss.str();
     }
 
-#if defined(linux)
     const int AlphaFP::alphaToC99RoundingMode[] = {
 	FE_TOWARDZERO,	// Chopped
 	FE_DOWNWARD,	// Minus_Infinity
 	FE_TONEAREST,	// Normal
 	FE_UPWARD	// Dynamic in inst, Plus_Infinity in FPCR
     };
-#endif
 
     const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" };
     // mark invalid trapping modes, but don't fail on them, because
@@ -738,14 +730,11 @@ def format FloatingPointOperate(code, *opt_args) {{
     exec_output = BasicExecute.subst(fast_iop)
 
     gen_code_prefix = r'''
-#if defined(linux)
     fesetround(getC99RoundingMode(xc->readFpcr()));
-#endif
 '''
+
     gen_code_suffix = r'''
-#if defined(linux)
     fesetround(FE_TONEAREST);
-#endif
 '''
 
     gen_iop = InstObjParams(name, Name + 'General', 'AlphaFP',
@@ -2080,7 +2069,7 @@ decode OPCODE default Unknown::unknown() {
 		    1: decode INTIMM {
 			// return EV5 for FULL_SYSTEM and EV6 otherwise
 			1: implver({{
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 			     Rc = 1;
 #else
 			     Rc = 2;
@@ -2090,7 +2079,7 @@ decode OPCODE default Unknown::unknown() {
 		}
 	    }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 	    // The mysterious 11.25...
 	    0x25: WarnUnimpl::eleven25();
 #endif
@@ -2310,7 +2299,7 @@ decode OPCODE default Unknown::unknown() {
 	0xb: decode FA {
 	    31: decode FP_TYPEFUNC {
 		format FloatingPointOperate {
-#ifdef SS_COMPATIBLE_FP
+#if SS_COMPATIBLE_FP
 		    0x0b: sqrts({{
 			if (Fb < 0.0)
 			    fault = Arithmetic_Fault;
@@ -2350,7 +2339,7 @@ decode OPCODE default Unknown::unknown() {
 	// and source type.
 	0: decode FP_TYPEFUNC {
 	    format FloatingPointOperate {
-#ifdef SS_COMPATIBLE_FP
+#if SS_COMPATIBLE_FP
 		0x00: adds({{ Fc = Fa + Fb; }});
 		0x01: subs({{ Fc = Fa - Fb; }});
 		0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp);
@@ -2484,7 +2473,7 @@ decode OPCODE default Unknown::unknown() {
 
 	format BasicOperate {
 	    0xc000: rpcc({{
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
         /* Rb is a fake dependency so here is a fun way to get
          * the parser to understand that.
          */
@@ -2517,7 +2506,7 @@ decode OPCODE default Unknown::unknown() {
 	    0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
 	}
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 	format BasicOperate {
 	    0xe000: rc({{
 		Ra = xc->readIntrFlag();
@@ -2536,7 +2525,7 @@ decode OPCODE default Unknown::unknown() {
 #endif
     }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     0x00: CallPal::call_pal({{
 	if (!palValid ||
 	    (palPriv
@@ -2574,7 +2563,7 @@ decode OPCODE default Unknown::unknown() {
     }
 #endif
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     format HwLoadStore {
 	0x1b: decode HW_LDST_QUAD {
 	    0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index 6c0c09b7a..cc6d81478 100644
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -31,6 +31,7 @@
 
 #include "arch/alpha/faults.hh"
 #include "base/misc.hh"
+#include "config/full_system.hh"
 #include "sim/host.hh"
 
 class FastCPU;
@@ -131,7 +132,7 @@ static const Addr PageBytes = ULL(1) << PageShift;
 static const Addr PageMask = ~(PageBytes - 1);
 static const Addr PageOffset = PageBytes - 1;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 
     typedef uint64_t InternalProcReg;
 
@@ -164,7 +165,7 @@ static const Addr PageOffset = PageBytes - 1;
         MiscRegFile miscRegs;		// control register file
         Addr pc;			// program counter
         Addr npc;			// next-cycle program counter
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
         IntReg palregs[NumIntRegs];	// PAL shadow registers
         InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
         int intrflag;			// interrupt flag
@@ -291,7 +292,7 @@ const int ArgumentReg2 = TheISA::ArgumentReg2;
 const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
 const int MaxAddr = (Addr)-1;
 
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
 class SyscallReturn {
         public:
            template <class T>
@@ -328,7 +329,7 @@ class SyscallReturn {
 #endif
 
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 typedef TheISA::InternalProcReg InternalProcReg;
 const int NumInternalProcRegs  = TheISA::NumInternalProcRegs;
 const int NumInterruptLevels = TheISA::NumInterruptLevels;
diff --git a/base/fast_alloc.hh b/base/fast_alloc.hh
index 9e7fa99d1..54e35f8e0 100644
--- a/base/fast_alloc.hh
+++ b/base/fast_alloc.hh
@@ -68,7 +68,9 @@
 // (by bucket).
 // #define FAST_ALLOC_STATS
 
-#ifdef NO_FAST_ALLOC
+#include "config/no_fast_alloc.hh"
+
+#if NO_FAST_ALLOC
 
 class FastAlloc {
 };
diff --git a/base/fenv.hh b/base/fenv.hh
new file mode 100644
index 000000000..3234f5dd3
--- /dev/null
+++ b/base/fenv.hh
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __BASE_FENV_HH__
+#define __BASE_FENV_HH__
+
+#include "config/use_fenv.hh"
+
+#if USE_FENV
+
+#include <fenv.h>
+
+#else
+
+// Dummy definitions to allow code to compile w/o a real <fenv.h>.
+
+#define FE_TONEAREST    0
+#define FE_DOWNWARD     0
+#define FE_UPWARD       0
+#define FE_TOWARDZERO   0
+
+inline int fesetround(int rounding_mode) { return 0; }
+
+#endif // USE_FENV
+
+
+#endif // __BASE_FENV_HH__
diff --git a/base/mysql.hh b/base/mysql.hh
index e16558dd3..2278d42e7 100644
--- a/base/mysql.hh
+++ b/base/mysql.hh
@@ -26,8 +26,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __BASE_MYQSL_HH__
-#define __BASE_MYQSL_HH__
+#ifndef __BASE_MYSQL_HH__
+#define __BASE_MYSQL_HH__
 
 #define TO_BE_INCLUDED_LATER 0
 
@@ -417,4 +417,4 @@ class Statement
 
 /* namespace MySQL */ }
 
-#endif // __BASE_MYQSL_HH__
+#endif // __BASE_MYSQL_HH__
diff --git a/base/statistics.cc b/base/statistics.cc
index 4368f1bcf..eaefd5f15 100644
--- a/base/statistics.cc
+++ b/base/statistics.cc
@@ -42,6 +42,7 @@
 #include "base/time.hh"
 #include "base/trace.hh"
 #include "base/stats/statdb.hh"
+#include "config/stats_binning.hh"
 
 using namespace std;
 
@@ -285,7 +286,7 @@ check()
 
     Database::stats().sort(StatData::less);
 
-#if defined(STATS_BINNING)
+#if STATS_BINNING
     if (MainBin::curBin() == NULL) {
         static MainBin mainBin("main bin");
         mainBin.activate();
diff --git a/base/statistics.hh b/base/statistics.hh
index c4acd9c23..c46744cac 100644
--- a/base/statistics.hh
+++ b/base/statistics.hh
@@ -62,6 +62,7 @@
 #include "base/stats/flags.hh"
 #include "base/stats/visit.hh"
 #include "base/stats/types.hh"
+#include "config/stats_binning.hh"
 #include "sim/host.hh"
 
 class Callback;
@@ -2184,7 +2185,7 @@ class SumNode : public Node
  * binned.  If the typedef is NoBin, nothing is binned.  If it is
  * MainBin, then all stats are binned under that Bin.
  */
-#if defined(STATS_BINNING)
+#if STATS_BINNING
 typedef MainBin DefaultBin;
 #else
 typedef NoBin DefaultBin;
diff --git a/base/stats/events.cc b/base/stats/events.cc
index 8c3303a69..3191aec13 100644
--- a/base/stats/events.cc
+++ b/base/stats/events.cc
@@ -28,11 +28,12 @@
 
 #include <vector>
 
-#ifdef USE_MYSQL
+#include "base/stats/events.hh"
+
+#if USE_MYSQL
 #include "base/cprintf.hh"
 #include "base/misc.hh"
 #include "base/mysql.hh"
-#include "base/stats/events.hh"
 #include "base/stats/mysql.hh"
 #include "base/stats/mysql_run.hh"
 #include "base/str.hh"
@@ -51,7 +52,7 @@ Tick EventStart = ULL(0x7fffffffffffffff);
 
 ObjectMatch event_ignore;
 
-#ifdef USE_MYSQL
+#if USE_MYSQL
 class InsertEvent
 {
   private:
diff --git a/base/stats/events.hh b/base/stats/events.hh
index 8b3212bed..2a23240b4 100644
--- a/base/stats/events.hh
+++ b/base/stats/events.hh
@@ -32,12 +32,13 @@
 #include <string>
 
 #include "base/trace.hh"
+#include "config/use_mysql.hh"
 
 namespace Stats {
 
 extern Tick EventStart;
 
-#ifdef USE_MYSQL
+#if USE_MYSQL
 void __event(const std::string &stat);
 bool MySqlConnected();
 #endif
@@ -52,7 +53,7 @@ recordEvent(const std::string &stat)
 
     DPRINTF(StatEvents, "Statistics Event: %s\n", stat);
 
-#ifdef USE_MYSQL
+#if USE_MYSQL
     if (!MySqlConnected())
         return;
 
diff --git a/build/SConstruct b/build/SConstruct
index b03a81c52..c091f4795 100644
--- a/build/SConstruct
+++ b/build/SConstruct
@@ -45,11 +45,9 @@
 import sys
 import os
 
-# Check for recent-enough Python version
-(major, minor) = sys.version_info[:2]
-if major < 2 or (major == 2 and minor < 3):
-    print "Error: M5 requires Python 2.3 or later."
-    sys.exit(1)
+# Check for recent-enough Python and SCons versions
+EnsurePythonVersion(2,3)
+EnsureSConsVersion(0,96)
 
 # The absolute path to the current directory (where this file lives).
 ROOT = Dir('.').abspath
@@ -61,95 +59,16 @@ EXT_SRCDIR = os.path.join(ROOT, 'ext')
 # Check for 'm5' and 'ext' links, die if they don't exist.
 if not os.path.isdir(SRCDIR):
     print "Error: '%s' must be a link to the M5 source tree." % SRCDIR
-    sys.exit(1)
+    Exit(1)
 
 if not os.path.isdir('ext'):
     print "Error: '%s' must be a link to the M5 external source tree." \
           % EXT_SRCDIR
-    sys.exit(1)
+    Exit(1)
 
 # tell python where to find m5 python code
 sys.path.append(os.path.join(SRCDIR, 'python'))
 
-
-###################################################
-#
-# Define Configurations
-#
-# The build system infers the build options from the subdirectory name
-# that the simulator is built under.  The subdirectory name must be of
-# the form <CONFIG>[.<OPT>]*, where <CONFIG> is a base configuration
-# (e.g., ALPHA_SE or ALPHA_FS) and OPT is an option (e.g., MYSQL).  The
-# following code defines the standard configurations and options.
-# Additional local configurations and options are read from the file
-# 'local_configs' if it exists.
-#
-# Each base configuration or option is defined in two steps: a
-# function that takes an SCons build environment and modifies it
-# appropriately for that config or option, and an entry in the
-# 'configs_map' or 'options_map' dictionary that maps the directory
-# name string to the function.  (The directory names are all upper
-# case, by convention.)
-#
-###################################################
-
-# Base non-full-system Alpha ISA configuration.
-def AlphaSyscallEmulConfig(env):
-    env.Replace(TARGET_ISA = 'alpha')
-    env.Append(CPPDEFINES = 'SS_COMPATIBLE_FP')
-
-# Base full-system configuration.
-def AlphaFullSysConfig(env):
-    env.Replace(TARGET_ISA = 'alpha')
-    env.Replace(FULL_SYSTEM = True)
-    env.Append(CPPDEFINES = ['FULL_SYSTEM'])
-
-# Base configurations map.
-configs_map = {
-    'ALPHA_SE' : AlphaSyscallEmulConfig,
-    'ALPHA_FS' : AlphaFullSysConfig
-    }
-
-# Disable FastAlloc object allocation.
-def NoFastAllocOpt(env):
-    env.Append(CPPDEFINES = 'NO_FAST_ALLOC')
-
-# Enable efence
-def EfenceOpt(env):
-    env.Append(LIBS=['efence'])
-
-# Configuration options map.
-options_map = {
-    'NO_FAST_ALLOC' : NoFastAllocOpt,
-    'EFENCE' : EfenceOpt
-    }
-
-# The 'local_configs' file can be used to define additional base
-# configurations and/or options without changing this file.
-if os.path.isfile('local_configs'):
-    SConscript('local_configs', exports = ['configs_map', 'options_map'])
-
-# This function parses a directory name of the form <CONFIG>[.<OPT>]*
-# and sets up the build environment appropriately.  Returns True if
-# successful, False if the base config or any of the options were not
-# defined.
-def set_dir_options(dir, env):
-    parts = dir.split('.')
-    config = parts[0]
-    opts = parts[1:]
-    try:
-        configs_map[config](env)
-        map(lambda opt: options_map[opt](env), opts)
-        return True
-    except KeyError, key:
-        print "Config/option '%s' not found." % key
-        return False
-
-# Set the default configuration and binary.  The default target (if
-# scons is invoked at the top level with no command-line targets) is
-# 'ALPHA_SE/m5.debug'.  If scons is invoked in a subdirectory with no
-# command-line targets, the configuration
-
 ###################################################
 #
 # Figure out which configurations to set up.
@@ -202,7 +121,7 @@ else:
     if not launch_dir.startswith(ROOT):
         print "Error: launch dir (%s) not a subdirectory of ROOT (%s)!" \
               (launch_dir, ROOT)
-        sys.exit(1)
+        Exit(1)
     # make launch_dir relative to ROOT (strip ROOT plus slash off front)
     launch_dir = launch_dir[len(ROOT)+1:]
     if len(COMMAND_LINE_TARGETS) != 0:
@@ -227,6 +146,12 @@ for t in my_targets:
     if dir not in build_dirs:
         build_dirs.append(dir)
 
+# Make a first pass to verify that build dirs are valid
+for build_dir in build_dirs:
+    if not os.path.isdir(build_dir):
+        print "Error: build directory", build_dir, "does not exist."
+        Exit(1)
+
 ###################################################
 #
 # Set up the default build environment.  This environment is copied
@@ -234,43 +159,69 @@ for t in my_targets:
 #
 ###################################################
 
-default_env = Environment(ENV = os.environ,  # inherit user's enviroment vars
-                          ROOT = ROOT,
-                          SRCDIR = SRCDIR,
-                          EXT_SRCDIR = EXT_SRCDIR,
-                          CPPDEFINES = [],
-                          FULL_SYSTEM = False,
-                          ALPHA_TLASER = False,
-                          USE_MYSQL = False)
+env = Environment(ENV = os.environ,  # inherit user's environment vars
+                  ROOT = ROOT,
+                  SRCDIR = SRCDIR,
+                  EXT_SRCDIR = EXT_SRCDIR)
 
-default_env.SConsignFile("sconsign")
+env.SConsignFile("sconsign")
 
-# For some reason, the CC and CXX variables don't get passed into the
-# environment correctly.  This is probably some sort of scons bug that
-# will eventually be fixed.
 if os.environ.has_key('CC'):
-    default_env.Replace(CC=os.environ['CC'])
+    env.Replace(CC=os.environ['CC'])
 
 if os.environ.has_key('CXX'):
-    default_env.Replace(CXX=os.environ['CXX'])
+    env.Replace(CXX=os.environ['CXX'])
 
 # M5_EXT is used by isa_parser.py to find the PLY package.
-default_env.Append(ENV = { 'M5_EXT' : EXT_SRCDIR })
+env.Append(ENV = { 'M5_EXT' : EXT_SRCDIR })
 
-default_env.Append(CCFLAGS='-pipe')
-default_env.Append(CCFLAGS='-fno-strict-aliasing')
-default_env.Append(CCFLAGS=Split('-Wall -Wno-sign-compare -Werror -Wundef'))
+# Set up default C++ compiler flags
+env.Append(CCFLAGS='-pipe')
+env.Append(CCFLAGS='-fno-strict-aliasing')
+env.Append(CCFLAGS=Split('-Wall -Wno-sign-compare -Werror -Wundef'))
 if sys.platform == 'cygwin':
     # cygwin has some header file issues...
-    default_env.Append(CCFLAGS=Split("-Wno-uninitialized"))
-default_env.Append(CPPPATH=[os.path.join(EXT_SRCDIR + '/dnet')])
+    env.Append(CCFLAGS=Split("-Wno-uninitialized"))
+env.Append(CPPPATH=[os.path.join(EXT_SRCDIR + '/dnet')])
 
-# libelf build is described in its own SConscript file.  Using a
-# dictionary for exports lets us export "default_env" so the
-# SConscript will see it as "env".  SConscript-global is the build in
-# build/libelf shared among all configs.
-default_env.SConscript('m5/libelf/SConscript-global',
-                       exports={'env' : default_env})
+# Default libraries
+env.Append(LIBS=['z'])
+
+# Platform-specific configuration
+conf = Configure(env)
+
+# Check for <fenv.h> (C99 FP environment control)
+have_fenv = conf.CheckHeader('fenv.h', '<>')
+if not have_fenv:
+    print "Warning: Header file <fenv.h> not found."
+    print "         This host has no IEEE FP rounding mode control."
+
+# Check for mysql
+mysql_config = WhereIs('mysql_config')
+have_mysql = mysql_config != None
+
+env = conf.Finish()
+
+# The source operand is a Value node containing the value of the option.
+def build_config_file(target, source, env, option):
+    f = file(str(target[0]), 'w')
+    print >> f, '#define', option, source[0]
+    f.close()
+    return None
+
+def config_builder(env, option):
+    target = os.path.join('config', option.lower() + '.hh')
+    source = Value(env[option])
+    def my_build_config_file(target, source, env):
+        build_config_file(target, source, env, option)
+    env.Command(target, source, my_build_config_file)
+
+env.Append(BUILDERS = { 'ConfigFile' : config_builder })
+
+# libelf build is described in its own SConscript file.
+# SConscript-global is the build in build/libelf shared among all
+# configs.
+env.SConscript('m5/libelf/SConscript-global', exports = 'env')
 
 ###################################################
 #
@@ -278,21 +229,68 @@ default_env.SConscript('m5/libelf/SConscript-global',
 #
 ###################################################
 
+# rename base env
+base_env = env
+
 for build_dir in build_dirs:
     # Make a copy of the default environment to use for this config.
-    env = default_env.Copy()
-    # Modify 'env' according to the build directory config.
-    print "Configuring options for directory '%s'." % build_dir
-    if not set_dir_options(build_dir, env):
-        print "Skipping directory '%s'." % build_dir
-        continue
-
+    env = base_env.Copy()
+    # Set env according to the build directory config.
+    options_file = os.path.join(build_dir, 'build_options')
+    opts = Options(options_file, ARGUMENTS)
+    opts.AddOptions(
+        EnumOption('TARGET_ISA', 'Target ISA', 'alpha', ('alpha')),
+        BoolOption('FULL_SYSTEM', 'Full-system support', False),
+        BoolOption('ALPHA_TLASER',
+                   'Model Alpha TurboLaser platform (vs. Tsunami)', False),
+        BoolOption('NO_FAST_ALLOC', 'Disable fast object allocator', False),
+        BoolOption('EFENCE', 'Link with Electric Fence malloc debugger',
+                   False),
+        BoolOption('SS_COMPATIBLE_FP',
+                   'Make floating-point results compatible with SimpleScalar',
+                   False),
+        BoolOption('STATS_BINNING', 'Bin statistics by CPU mode', have_mysql),
+        BoolOption('USE_MYSQL', 'Use MySQL for stats output', have_mysql),
+        BoolOption('USE_FENV', 'Use <fenv.h> IEEE mode control', have_fenv)
+        )
+
+    opts.Update(env)
+    opts.Save(options_file, env)
+
+    env.ExportOptions = ['FULL_SYSTEM', 'ALPHA_TLASER', 'USE_FENV', \
+                         'USE_MYSQL', 'NO_FAST_ALLOC', 'SS_COMPATIBLE_FP', \
+                         'STATS_BINNING']
+
+    # Process option settings.
+
+    if not have_fenv and env['USE_FENV']:
+        print "Warning: <fenv.h> not available; " \
+              "forcing USE_FENV to False in", build_dir + "."
+        env['USE_FENV'] = False
+
+    if not env['USE_FENV']:
+        print "Warning: No IEEE FP rounding mode control in", build_dir + "."
+        print "         FP results may deviate slightly", \
+              "and some regression tests may fail."
+
+    if env['EFENCE']:
+        env.Append(LIBS=['efence'])
+
+    if env['USE_MYSQL']:
+        if not have_mysql:
+            print "Warning: MySQL not available; " \
+                  "forcing USE_MYSQL to False in", build_dir + "."
+            env['USE_MYSQL'] = False
+        else:
+            print "Compiling in", build_dir, "with MySQL support."
+            env.ParseConfig(mysql_config + ' --libs')
+            env.ParseConfig(mysql_config + ' --include')
+    
     # The m5/SConscript file sets up the build rules in 'env' according
     # to the configured options.
     SConscript('m5/SConscript', build_dir = build_dir, exports = 'env',
                duplicate=0)
 
-
 ###################################################
 #
 # Let SCons do its thing.  At this point SCons will use the defined
diff --git a/cpu/base.cc b/cpu/base.cc
index 50c777b0d..8d97bc330 100644
--- a/cpu/base.cc
+++ b/cpu/base.cc
@@ -51,7 +51,7 @@ vector<BaseCPU *> BaseCPU::cpuList;
 // been initialized
 int maxThreadsPerCPU = 1;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 BaseCPU::BaseCPU(Params *p)
     : SimObject(p->name), clock(p->clock), checkInterrupts(true),
       params(p), number_of_threads(p->numberOfThreads), system(p->system)
@@ -122,7 +122,7 @@ BaseCPU::BaseCPU(Params *p)
                 p->max_loads_all_threads, *counter);
     }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     memset(interrupts, 0, sizeof(interrupts));
     intstatus = 0;
 #endif
@@ -189,7 +189,7 @@ BaseCPU::registerExecContexts()
 {
     for (int i = 0; i < execContexts.size(); ++i) {
         ExecContext *xc = execContexts[i];
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
         int id = params->cpu_id;
         if (id != -1)
             id += i;
@@ -219,7 +219,7 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
 
         newXC->takeOverFrom(oldXC);
         assert(newXC->cpu_id == oldXC->cpu_id);
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
         system->replaceExecContext(newXC, newXC->cpu_id);
 #else
         assert(newXC->process == oldXC->process);
@@ -227,7 +227,7 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
 #endif
     }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     for (int i = 0; i < NumInterruptLevels; ++i)
         interrupts[i] = oldCPU->interrupts[i];
     intstatus = oldCPU->intstatus;
@@ -235,7 +235,7 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
 }
 
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 void
 BaseCPU::post_interrupt(int int_num, int index)
 {
diff --git a/cpu/base.hh b/cpu/base.hh
index e28f15884..b9617a730 100644
--- a/cpu/base.hh
+++ b/cpu/base.hh
@@ -32,12 +32,13 @@
 #include <vector>
 
 #include "base/statistics.hh"
+#include "config/full_system.hh"
 #include "cpu/sampler/sampler.hh"
 #include "sim/eventq.hh"
 #include "sim/sim_object.hh"
 #include "targetarch/isa_traits.hh"
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 class System;
 #endif
 
@@ -55,7 +56,7 @@ class BaseCPU : public SimObject
     inline Tick cycles(int numCycles) const { return clock * numCycles; }
     inline Tick curCycle() const { return curTick / clock; }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
   protected:
     uint64_t interrupts[NumInterruptLevels];
     uint64_t intstatus;
@@ -109,7 +110,7 @@ class BaseCPU : public SimObject
         Tick clock;
         bool functionTrace;
         Tick functionTraceStart;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
         System *system;
         int cpu_id;
 #endif
@@ -153,7 +154,7 @@ class BaseCPU : public SimObject
      */
     EventQueue **comLoadEventQueue;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     System *system;
 
     /**
diff --git a/cpu/base_dyn_inst.cc b/cpu/base_dyn_inst.cc
index 80eb34fd5..d921bd148 100644
--- a/cpu/base_dyn_inst.cc
+++ b/cpu/base_dyn_inst.cc
@@ -166,7 +166,7 @@ BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
      * Replace the disjoint functional memory with a unified one and remove
      * this hack.
      */
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
     req->paddr = req->vaddr;
 #endif
 
diff --git a/cpu/base_dyn_inst.hh b/cpu/base_dyn_inst.hh
index 3f5f327a6..d29257a52 100644
--- a/cpu/base_dyn_inst.hh
+++ b/cpu/base_dyn_inst.hh
@@ -34,6 +34,7 @@
 
 #include "base/fast_alloc.hh"
 #include "base/trace.hh"
+#include "config/full_system.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/inst_seq.hh"
 #include "cpu/o3/comm.hh"
@@ -467,7 +468,7 @@ BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
      * Replace the disjoint functional memory with a unified one and remove
      * this hack.
      */
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
     req->paddr = req->vaddr;
 #endif
 
@@ -515,7 +516,7 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
      * Replace the disjoint functional memory with a unified one and remove
      * this hack.
      */
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
     req->paddr = req->vaddr;
 #endif
 
diff --git a/cpu/exec_context.cc b/cpu/exec_context.cc
index 52d5c8d1e..91578bdf1 100644
--- a/cpu/exec_context.cc
+++ b/cpu/exec_context.cc
@@ -31,7 +31,7 @@
 #include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 #include "base/cprintf.hh"
 #include "kern/kernel_stats.hh"
 #include "sim/serialize.hh"
@@ -43,7 +43,7 @@
 using namespace std;
 
 // constructor
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
                          AlphaITB *_itb, AlphaDTB *_dtb,
                          FunctionalMemory *_mem)
@@ -78,7 +78,7 @@ ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num,
 
 ExecContext::~ExecContext()
 {
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     delete kernelStats;
 #endif
 }
@@ -89,7 +89,7 @@ ExecContext::takeOverFrom(ExecContext *oldContext)
 {
     // some things should already be set up
     assert(mem == oldContext->mem);
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     assert(system == oldContext->system);
 #else
     assert(process == oldContext->process);
@@ -106,7 +106,7 @@ ExecContext::takeOverFrom(ExecContext *oldContext)
     oldContext->_status = ExecContext::Unallocated;
 }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 void
 ExecContext::execute(const StaticInstBase *inst)
 {
@@ -124,7 +124,7 @@ ExecContext::serialize(ostream &os)
     SERIALIZE_SCALAR(func_exe_inst);
     SERIALIZE_SCALAR(inst);
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     kernelStats->serialize(os);
 #endif
 }
@@ -139,7 +139,7 @@ ExecContext::unserialize(Checkpoint *cp, const std::string &section)
     UNSERIALIZE_SCALAR(func_exe_inst);
     UNSERIALIZE_SCALAR(inst);
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     kernelStats->unserialize(cp, section);
 #endif
 }
@@ -161,7 +161,7 @@ ExecContext::suspend()
     if (status() == Suspended)
         return;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     // Don't change the status from active if there are pending interrupts
     if (cpu->check_interrupts()) {
         assert(status() == Active);
@@ -197,7 +197,7 @@ ExecContext::halt()
 void
 ExecContext::regStats(const string &name)
 {
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     kernelStats->regStats(name + ".kern");
 #endif
 }
@@ -208,7 +208,7 @@ ExecContext::trap(Fault fault)
     //TheISA::trap(fault);    //One possible way to do it...
 
     /** @todo: Going to hack it for now.  Do a true fixup later. */
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     ev5_trap(fault);
 #else
     fatal("fault (%d) detected @ PC 0x%08p", fault, readPC());
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index 5e105c44d..6a17951f9 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -29,6 +29,7 @@
 #ifndef __CPU_EXEC_CONTEXT_HH__
 #define __CPU_EXEC_CONTEXT_HH__
 
+#include "config/full_system.hh"
 #include "mem/functional/functional.hh"
 #include "mem/mem_req.hh"
 #include "sim/host.hh"
@@ -40,7 +41,7 @@ class FunctionalMemory;
 class PhysicalMemory;
 class BaseCPU;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 
 #include "sim/system.hh"
 #include "targetarch/alpha_memory.hh"
@@ -121,7 +122,7 @@ class ExecContext
     // it belongs.  For full-system mode, this is the system CPU ID.
     int cpu_id;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     FunctionalMemory *mem;
     AlphaITB *itb;
     AlphaDTB *dtb;
@@ -176,7 +177,7 @@ class ExecContext
     unsigned storeCondFailures;
 
     // constructor: initialize context from given process structure
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
                 AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem);
 #else
@@ -193,7 +194,7 @@ class ExecContext
     void serialize(std::ostream &os);
     void unserialize(Checkpoint *cp, const std::string &section);
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     bool validInstAddr(Addr addr) { return true; }
     bool validDataAddr(Addr addr) { return true; }
     int getInstAsid() { return regs.instAsid(); }
@@ -253,7 +254,7 @@ class ExecContext
     template <class T>
     Fault read(MemReqPtr &req, T &data)
     {
-#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
+#if FULL_SYSTEM && defined(TARGET_ALPHA)
         if (req->flags & LOCKED) {
             MiscRegFile *cregs = &req->xc->regs.miscRegs;
             cregs->lock_addr = req->paddr;
@@ -270,7 +271,7 @@ class ExecContext
     template <class T>
     Fault write(MemReqPtr &req, T &data)
     {
-#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
+#if FULL_SYSTEM && defined(TARGET_ALPHA)
 
         MiscRegFile *cregs;
 
@@ -404,7 +405,7 @@ class ExecContext
         regs.miscRegs.fpcr = val;
     }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     uint64_t readIpr(int idx, Fault &fault);
     Fault setIpr(int idx, uint64_t val);
     int readIntrFlag() { return regs.intrflag; }
@@ -423,7 +424,7 @@ class ExecContext
 
     void trap(Fault fault);
 
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
     IntReg getSyscallArg(int i)
     {
         return regs.intRegFile[ArgumentReg0 + i];
diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh
index 545165b2b..cba57d189 100644
--- a/cpu/o3/alpha_cpu.hh
+++ b/cpu/o3/alpha_cpu.hh
@@ -44,7 +44,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
   public:
     AlphaFullCPU(Params &params);
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     AlphaITB *itb;
     AlphaDTB *dtb;
 #endif
@@ -52,7 +52,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
   public:
     void regStats();
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     //Note that the interrupt stuff from the base CPU might be somewhat
     //ISA specific (ie NumInterruptLevels).  These functions might not
     //be needed in FullCPU though.
@@ -131,7 +131,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
     // Most of the full system code and syscall emulation is not yet
     // implemented.  These functions do show what the final interface will
     // look like.
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     uint64_t *getIpr();
     uint64_t readIpr(int idx, Fault &fault);
     Fault setIpr(int idx, uint64_t val);
@@ -149,7 +149,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
 #endif
 
 
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
     // Need to change these into regfile calls that directly set a certain
     // register.  Actually, these functions should handle most of this
     // functionality by themselves; should look up the rename and then
@@ -191,7 +191,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
     void copyFromXC();
 
   public:
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     bool palShadowEnabled;
 
     // Not sure this is used anywhere.
@@ -210,7 +210,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
     template <class T>
     Fault read(MemReqPtr &req, T &data)
     {
-#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
+#if FULL_SYSTEM && defined(TARGET_ALPHA)
         if (req->flags & LOCKED) {
             MiscRegFile *cregs = &req->xc->regs.miscRegs;
             cregs->lock_addr = req->paddr;
@@ -233,7 +233,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
     template <class T>
     Fault write(MemReqPtr &req, T &data)
     {
-#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
+#if FULL_SYSTEM && defined(TARGET_ALPHA)
 
         MiscRegFile *cregs;
 
diff --git a/cpu/o3/alpha_cpu_builder.cc b/cpu/o3/alpha_cpu_builder.cc
index 57c567471..3547fb1b5 100644
--- a/cpu/o3/alpha_cpu_builder.cc
+++ b/cpu/o3/alpha_cpu_builder.cc
@@ -45,7 +45,7 @@
 #include "sim/sim_object.hh"
 #include "sim/stats.hh"
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 #include "base/remote_gdb.hh"
 #include "mem/functional/memory_control.hh"
 #include "mem/functional/physical.hh"
@@ -69,7 +69,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
     Param<int> clock;
     Param<int> numThreads;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 SimObjectParam<System *> system;
 Param<int> cpu_id;
 SimObjectParam<AlphaITB *> itb;
@@ -162,7 +162,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
     INIT_PARAM(clock, "clock speed"),
     INIT_PARAM(numThreads, "number of HW thread contexts"),
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     INIT_PARAM(system, "System object"),
     INIT_PARAM(cpu_id, "processor ID"),
     INIT_PARAM(itb, "Instruction translation buffer"),
@@ -273,7 +273,7 @@ CREATE_SIM_OBJECT(DerivAlphaFullCPU)
 {
     DerivAlphaFullCPU *cpu;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     // Full-system only supports a single thread for the moment.
     int actual_num_threads = 1;
 #else
@@ -295,7 +295,7 @@ CREATE_SIM_OBJECT(DerivAlphaFullCPU)
     params.name = getInstanceName();
     params.numberOfThreads = actual_num_threads;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     params.system = system;
     params.cpu_id = cpu_id;
     params.itb = itb;
diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
index 146186e2f..2a764740b 100644
--- a/cpu/o3/alpha_cpu_impl.hh
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -39,7 +39,7 @@
 #include "cpu/o3/alpha_params.hh"
 #include "cpu/o3/comm.hh"
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 #include "arch/alpha/osfpal.hh"
 #include "arch/alpha/isa_traits.hh"
 //#include "arch/alpha/ev5.hh"
@@ -75,7 +75,7 @@ AlphaFullCPU<Impl>::regStats()
     this->commit.regStats();
 }
 
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
 
 // Will probably need to know which thread is calling syscall
 // Will need to pass that information in to the DynInst when it is constructed,
@@ -238,7 +238,7 @@ AlphaFullCPU<Impl>::copyFromXC()
     this->funcExeInst = this->xc->func_exe_inst;
 }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 
 template <class Impl>
 uint64_t *
diff --git a/cpu/o3/alpha_dyn_inst.hh b/cpu/o3/alpha_dyn_inst.hh
index 8a9a681d2..bb90bf21a 100644
--- a/cpu/o3/alpha_dyn_inst.hh
+++ b/cpu/o3/alpha_dyn_inst.hh
@@ -86,7 +86,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
     uint64_t readFpcr();
     void setFpcr(uint64_t val);
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     uint64_t readIpr(int idx, Fault &fault);
     Fault setIpr(int idx, uint64_t val);
     Fault hwrei();
diff --git a/cpu/o3/alpha_dyn_inst_impl.hh b/cpu/o3/alpha_dyn_inst_impl.hh
index 437b113e4..d1ebb812d 100644
--- a/cpu/o3/alpha_dyn_inst_impl.hh
+++ b/cpu/o3/alpha_dyn_inst_impl.hh
@@ -95,7 +95,7 @@ AlphaDynInst<Impl>::setFpcr(uint64_t val)
     this->cpu->setFpcr(val);
 }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 template <class Impl>
 uint64_t
 AlphaDynInst<Impl>::readIpr(int idx, Fault &fault)
diff --git a/cpu/o3/alpha_params.hh b/cpu/o3/alpha_params.hh
index 77e6f3649..79b0937e3 100644
--- a/cpu/o3/alpha_params.hh
+++ b/cpu/o3/alpha_params.hh
@@ -49,7 +49,7 @@ class AlphaSimpleParams : public BaseFullCPU::Params
 {
   public:
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     AlphaITB *itb; AlphaDTB *dtb;
 #else
     std::vector<Process *> workload;
diff --git a/cpu/o3/commit_impl.hh b/cpu/o3/commit_impl.hh
index ac3d83174..dc0986772 100644
--- a/cpu/o3/commit_impl.hh
+++ b/cpu/o3/commit_impl.hh
@@ -186,7 +186,7 @@ SimpleCommit<Impl>::commit()
     // in the IPR.  Look at IPR[EXC_ADDR];
     // hwrei() is what resets the PC to the place where instruction execution
     // beings again.
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     if (//checkInterrupts &&
         cpu->check_interrupts() &&
         !cpu->inPalMode(readCommitPC())) {
@@ -397,7 +397,7 @@ SimpleCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
 
     if (inst_fault != No_Fault && inst_fault != Fake_Mem_Fault) {
         if (!head_inst->isNop()) {
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
             cpu->trap(inst_fault);
 #else // !FULL_SYSTEM
             panic("fault (%d) detected @ PC %08p", inst_fault,
diff --git a/cpu/o3/cpu.cc b/cpu/o3/cpu.cc
index b447439c0..adc7b6bbc 100644
--- a/cpu/o3/cpu.cc
+++ b/cpu/o3/cpu.cc
@@ -26,7 +26,9 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifdef FULL_SYSTEM
+#include "config/full_system.hh"
+
+#if FULL_SYSTEM
 #include "sim/system.hh"
 #else
 #include "sim/process.hh"
@@ -68,7 +70,7 @@ FullO3CPU<Impl>::TickEvent::description()
 //Call constructor to all the pipeline stages here
 template <class Impl>
 FullO3CPU<Impl>::FullO3CPU(Params &params)
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     : BaseFullCPU(params),
 #else
     : BaseFullCPU(params),
@@ -105,7 +107,7 @@ FullO3CPU<Impl>::FullO3CPU(Params &params)
 
       globalSeqNum(1),
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
       system(params.system),
       memCtrl(system->memctrl),
       physmem(system->physmem),
@@ -125,12 +127,12 @@ FullO3CPU<Impl>::FullO3CPU(Params &params)
 {
     _status = Idle;
 
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
     thread.resize(this->number_of_threads);
 #endif
 
     for (int i = 0; i < this->number_of_threads; ++i) {
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
         assert(i == 0);
         system->execContexts[i] =
             new ExecContext(this, i, system, itb, dtb, mem);
@@ -153,7 +155,7 @@ FullO3CPU<Impl>::FullO3CPU(Params &params)
 
     // Note that this is a hack so that my code which still uses xc-> will
     // still work.  I should remove this eventually
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     xc = system->execContexts[0];
 #else
     xc = thread[0];
@@ -246,7 +248,7 @@ FullO3CPU<Impl>::init()
 
         // Need to do a copy of the xc->regs into the CPU's regfile so
         // that it can start properly.
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
         ExecContext *src_xc = system->execContexts[0];
 #else
         ExecContext *src_xc = thread[0];
diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh
index 10f60b5da..75dca5056 100644
--- a/cpu/o3/cpu.hh
+++ b/cpu/o3/cpu.hh
@@ -42,13 +42,14 @@
 
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
+#include "config/full_system.hh"
 #include "cpu/base.hh"
 #include "cpu/o3/comm.hh"
 #include "cpu/o3/cpu_policy.hh"
 #include "cpu/exec_context.hh"
 #include "sim/process.hh"
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 #include "arch/alpha/ev5.hh"
 using namespace EV5;
 #endif
@@ -62,7 +63,7 @@ class BaseFullCPU : public BaseCPU
   public:
     typedef BaseCPU::Params Params;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     BaseFullCPU(Params &params);
 #else
     BaseFullCPU(Params &params);
@@ -143,7 +144,7 @@ class FullO3CPU : public BaseFullCPU
     /** Get the current instruction sequence number, and increment it. */
     InstSeqNum getAndIncrementInstSeq();
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     /** Check if this address is a valid instruction address. */
     bool validInstAddr(Addr addr) { return true; }
 
@@ -325,7 +326,7 @@ class FullO3CPU : public BaseFullCPU
     /** Temporary function to get pointer to exec context. */
     ExecContext *xcBase()
     {
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
         return system->execContexts[0];
 #else
         return thread[0];
@@ -334,7 +335,7 @@ class FullO3CPU : public BaseFullCPU
 
     InstSeqNum globalSeqNum;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     System *system;
 
     MemoryController *memCtrl;
diff --git a/cpu/o3/fetch_impl.hh b/cpu/o3/fetch_impl.hh
index 75b6abb3d..c943fd36a 100644
--- a/cpu/o3/fetch_impl.hh
+++ b/cpu/o3/fetch_impl.hh
@@ -80,7 +80,7 @@ SimpleFetch<Impl>::SimpleFetch(Params &params)
     memReq = new MemReq();
     // Not sure of this parameter.  I think it should be based on the
     // thread number.
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
     memReq->asid = 0;
 #else
     memReq->asid = 0;
@@ -229,7 +229,7 @@ SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
     // of the instructions in the cache line until either the end of the
     // cache line or a predicted taken branch is encountered.
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     // Flag to say whether or not address is physical addr.
     unsigned flags = cpu->inPalMode() ? PHYSICAL : 0;
 #else
@@ -605,7 +605,7 @@ SimpleFetch<Impl>::fetch()
         DPRINTF(Fetch, "Fetch: Blocked, need to handle the trap.\n");
 
         _status = Blocked;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 //        cpu->trap(fault);
         // Send a signal to the ROB indicating that there's a trap from the
         // fetch stage that needs to be handled.  Need to indicate that
diff --git a/cpu/o3/iew.hh b/cpu/o3/iew.hh
index 69cd3799a..af23c6f45 100644
--- a/cpu/o3/iew.hh
+++ b/cpu/o3/iew.hh
@@ -35,6 +35,7 @@
 
 #include <queue>
 
+#include "config/full_system.hh"
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
 #include "cpu/o3/comm.hh"
@@ -169,7 +170,7 @@ class SimpleIEW
 
     LDSTQ ldstQueue;
 
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
   public:
     void lsqWriteback();
 #endif
diff --git a/cpu/o3/iew_impl.hh b/cpu/o3/iew_impl.hh
index 5f0d7b647..b8a2b4dc9 100644
--- a/cpu/o3/iew_impl.hh
+++ b/cpu/o3/iew_impl.hh
@@ -726,7 +726,7 @@ SimpleIEW<Impl>::iew()
     issueToExecQueue.advance();
 }
 
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
 template<class Impl>
 void
 SimpleIEW<Impl>::lsqWriteback()
diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh
index e63b7fcfb..4d47b8f9c 100644
--- a/cpu/o3/regfile.hh
+++ b/cpu/o3/regfile.hh
@@ -33,9 +33,10 @@
 
 #include "arch/alpha/isa_traits.hh"
 #include "base/trace.hh"
+#include "config/full_system.hh"
 #include "cpu/o3/comm.hh"
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 #include "arch/alpha/ev5.hh"
 #include "kern/kernel_stats.hh"
 
@@ -209,7 +210,7 @@ class PhysRegFile
         miscRegs.fpcr = val;
     }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     uint64_t readIpr(int idx, Fault &fault);
     Fault setIpr(int idx, uint64_t val);
     InternalProcReg *getIpr() { return ipr; }
@@ -235,7 +236,7 @@ class PhysRegFile
     /** Next-cycle program counter. */
     Addr npc;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
   private:
     // This is ISA specifc stuff; remove it eventually once ISAImpl is used
     IntReg palregs[NumIntRegs];	// PAL shadow registers
@@ -267,7 +268,7 @@ PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs,
     memset(floatRegFile, 0, sizeof(*floatRegFile));
 }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 
 //Problem:  This code doesn't make sense at the RegFile level because it
 //needs things such as the itb and dtb.  Either put it at the CPU level or
@@ -629,6 +630,6 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
     return No_Fault;
 }
 
-#endif // #ifdef FULL_SYSTEM
+#endif // #if FULL_SYSTEM
 
 #endif // __CPU_O3_CPU_REGFILE_HH__
diff --git a/cpu/o3/rename_impl.hh b/cpu/o3/rename_impl.hh
index 5fd62e911..2068b36ab 100644
--- a/cpu/o3/rename_impl.hh
+++ b/cpu/o3/rename_impl.hh
@@ -28,6 +28,7 @@
 
 #include <list>
 
+#include "config/full_system.hh"
 #include "cpu/o3/rename.hh"
 
 template <class Impl>
@@ -232,7 +233,7 @@ SimpleRename<Impl>::doSquash()
 
     InstSeqNum squashed_seq_num = fromCommit->commitInfo.doneSeqNum;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     assert(!historyBuffer.empty());
 #else
     // After a syscall squashes everything, the history buffer may be empty
@@ -543,7 +544,7 @@ SimpleRename<Impl>::tick()
 
     // Ugly code, revamp all of the tick() functions eventually.
     if (fromCommit->commitInfo.doneSeqNum != 0 && _status != Squashing) {
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
         if (!fromCommit->commitInfo.squash) {
             removeFromHistory(fromCommit->commitInfo.doneSeqNum);
         }
diff --git a/cpu/o3/rob_impl.hh b/cpu/o3/rob_impl.hh
index 51f4afe75..e7a5671d9 100644
--- a/cpu/o3/rob_impl.hh
+++ b/cpu/o3/rob_impl.hh
@@ -29,6 +29,7 @@
 #ifndef __CPU_O3_CPU_ROB_IMPL_HH__
 #define __CPU_O3_CPU_ROB_IMPL_HH__
 
+#include "config/full_system.hh"
 #include "cpu/o3/rob.hh"
 
 template <class Impl>
@@ -209,7 +210,7 @@ ROB<Impl>::doSquash()
         // will never be false.  Normally the squash would never be able
         // to go past the head of the ROB; in this case it might, so it
         // must be handled otherwise it will segfault.
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
         if (squashIt == cpu->instList.begin()) {
             DPRINTF(ROB, "ROB: Reached head of instruction list while "
                     "squashing.\n");
diff --git a/cpu/ozone/cpu.hh b/cpu/ozone/cpu.hh
index 09702c3f9..5af77862a 100644
--- a/cpu/ozone/cpu.hh
+++ b/cpu/ozone/cpu.hh
@@ -30,6 +30,7 @@
 #define __CPU_OOO_CPU_OOO_CPU_HH__
 
 #include "base/statistics.hh"
+#include "config/full_system.hh"
 #include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 #include "encumbered/cpu/full/fu_pool.hh"
@@ -40,7 +41,7 @@
 #include "sim/eventq.hh"
 
 // forward declarations
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 class Processor;
 class AlphaITB;
 class AlphaDTB;
@@ -147,7 +148,7 @@ class OoOCPU : public BaseCPU
         MemInterface *icache_interface;
         MemInterface *dcache_interface;
         int width;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
         AlphaITB *itb;
         AlphaDTB *dtb;
         FunctionalMemory *mem;
@@ -173,7 +174,7 @@ class OoOCPU : public BaseCPU
     void switchOut();
     void takeOverFrom(BaseCPU *oldCPU);
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     Addr dbg_vtophys(Addr addr);
 
     bool interval_stats;
@@ -279,7 +280,7 @@ class OoOCPU : public BaseCPU
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     bool validInstAddr(Addr addr) { return true; }
     bool validDataAddr(Addr addr) { return true; }
     int getInstAsid() { return xc->regs.instAsid(); }
@@ -381,7 +382,7 @@ class OoOCPU : public BaseCPU
     DynInstPtr commitTable[ISA::TotalNumRegs];
 
     // Might need a table of the shadow registers as well.
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     DynInstPtr palShadowTable[ISA::NumIntRegs];
 #endif
 
@@ -510,7 +511,7 @@ class OoOCPU : public BaseCPU
     uint64_t readFpcr() { return xc->readFpcr(); }
     void setFpcr(uint64_t val) { xc->setFpcr(val); }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
     Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
     Fault hwrei() { return xc->hwrei(); }
diff --git a/cpu/pc_event.cc b/cpu/pc_event.cc
index aa6c51466..c3bb3dbe6 100644
--- a/cpu/pc_event.cc
+++ b/cpu/pc_event.cc
@@ -32,6 +32,7 @@
 #include <utility>
 
 #include "base/trace.hh"
+#include "config/full_system.hh"
 #include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/pc_event.hh"
@@ -131,7 +132,7 @@ BreakPCEvent::process(ExecContext *xc)
         delete this;
 }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 extern "C"
 void
 sched_break_pc_sys(System *sys, Addr addr)
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index c5e12990b..1bd5547e7 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -59,7 +59,7 @@
 #include "sim/sim_object.hh"
 #include "sim/stats.hh"
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 #include "base/remote_gdb.hh"
 #include "mem/functional/memory_control.hh"
 #include "mem/functional/physical.hh"
@@ -115,7 +115,7 @@ SimpleCPU::SimpleCPU(Params *p)
       cacheCompletionEvent(this)
 {
     _status = Idle;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     xc = new ExecContext(this, 0, p->system, p->itb, p->dtb, p->mem);
 
     // initialize CPU, including PC
@@ -562,7 +562,7 @@ SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
 }
 
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 Addr
 SimpleCPU::dbg_vtophys(Addr addr)
 {
@@ -608,7 +608,7 @@ SimpleCPU::processCacheCompletion()
     }
 }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 void
 SimpleCPU::post_interrupt(int int_num, int index)
 {
@@ -631,7 +631,7 @@ SimpleCPU::tick()
 
     Fault fault = No_Fault;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     if (checkInterrupts && check_interrupts() && !xc->inPalMode() &&
         status() != IcacheMissComplete) {
         int ipl = 0;
@@ -692,7 +692,7 @@ SimpleCPU::tick()
         // Try to fetch an instruction
 
         // set up memory request for instruction fetch
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 #define IFETCH_FLAGS(pc)	((pc) & 1) ? PHYSICAL : 0
 #else
 #define IFETCH_FLAGS(pc)	0
@@ -744,7 +744,7 @@ SimpleCPU::tick()
         traceData = Trace::getInstRecord(curTick, xc, this, curStaticInst,
                                          xc->regs.pc);
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
         xc->setInst(inst);
 #endif // FULL_SYSTEM
 
@@ -752,7 +752,7 @@ SimpleCPU::tick()
 
         fault = curStaticInst->execute(this, traceData);
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
         if (xc->fnbin)
             xc->execute(curStaticInst.get());
 #endif
@@ -778,7 +778,7 @@ SimpleCPU::tick()
     }	// if (fault == No_Fault)
 
     if (fault != No_Fault) {
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
         xc->ev5_trap(fault);
 #else // !FULL_SYSTEM
         fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc);
@@ -790,7 +790,7 @@ SimpleCPU::tick()
         xc->regs.npc += sizeof(MachInst);
     }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     Addr oldpc;
     do {
         oldpc = xc->regs.pc;
@@ -818,7 +818,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
     Param<Counter> max_loads_any_thread;
     Param<Counter> max_loads_all_threads;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     SimObjectParam<AlphaITB *> itb;
     SimObjectParam<AlphaDTB *> dtb;
     SimObjectParam<FunctionalMemory *> mem;
@@ -850,7 +850,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
     INIT_PARAM(max_loads_all_threads,
                "terminate when all threads have reached this load count"),
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     INIT_PARAM(itb, "Instruction TLB"),
     INIT_PARAM(dtb, "Data TLB"),
     INIT_PARAM(mem, "memory"),
@@ -888,7 +888,7 @@ CREATE_SIM_OBJECT(SimpleCPU)
     params->dcache_interface = (dcache) ? dcache->getInterface() : NULL;
     params->width = width;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     params->itb = itb;
     params->dtb = dtb;
     params->mem = mem;
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index e8394db3f..0f7251237 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -30,6 +30,7 @@
 #define __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__
 
 #include "base/statistics.hh"
+#include "config/full_system.hh"
 #include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/pc_event.hh"
@@ -38,7 +39,7 @@
 #include "sim/eventq.hh"
 
 // forward declarations
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 class Processor;
 class AlphaITB;
 class AlphaDTB;
@@ -130,7 +131,7 @@ class SimpleCPU : public BaseCPU
         MemInterface *icache_interface;
         MemInterface *dcache_interface;
         int width;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
         AlphaITB *itb;
         AlphaDTB *dtb;
         FunctionalMemory *mem;
@@ -148,7 +149,7 @@ class SimpleCPU : public BaseCPU
     void switchOut(Sampler *s);
     void takeOverFrom(BaseCPU *oldCPU);
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     Addr dbg_vtophys(Addr addr);
 
     bool interval_stats;
@@ -323,7 +324,7 @@ class SimpleCPU : public BaseCPU
     uint64_t readFpcr() { return xc->readFpcr(); }
     void setFpcr(uint64_t val) { xc->setFpcr(val); }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
     Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
     Fault hwrei() { return xc->hwrei(); }
diff --git a/python/SConscript b/python/SConscript
index 57b018fea..a34d3f2d5 100644
--- a/python/SConscript
+++ b/python/SConscript
@@ -151,7 +151,7 @@ def MakeDefinesPyFile(target, source, env):
     f = file(str(target[0]), 'w')
     print >>f, "import __main__"
     print >>f, "__main__.m5_build_env = ",
-    print >>f, scons_helper.flatten_defines(env['CPPDEFINES'])
+    print >>f, source[0]
     f.close()
 
 CFileCounter = 0
@@ -196,7 +196,10 @@ for root, dirs, files in os.walk(objpath, topdown=True):
             embedded_py_files.append(os.path.join(root, f))
 
 embedfile_hh = os.path.join(env['SRCDIR'], 'base/embedfile.hh')
-env.Command('defines.py', None, MakeDefinesPyFile)
+
+optionDict = dict([(opt, env[opt]) for opt in env.ExportOptions])
+env.Command('defines.py', Value(optionDict), MakeDefinesPyFile)
+
 env.Command('embedded_py.py', embedded_py_files, MakeEmbeddedPyFile)
 env.Depends('embedded_py.cc', embedfile_hh)
 env.Command('embedded_py.cc',
diff --git a/python/m5/convert.py b/python/m5/convert.py
index 2551459bd..9d9f4efa7 100644
--- a/python/m5/convert.py
+++ b/python/m5/convert.py
@@ -105,17 +105,20 @@ def toInteger(value):
 
     return result
 
+_bool_dict = {
+    'true' : True,   't' : True,  'yes' : True, 'y' : True,  '1' : True,
+    'false' : False, 'f' : False, 'no' : False, 'n' : False, '0' : False
+    }
+
 def toBool(value):
     if not isinstance(value, str):
         raise TypeError, "wrong type '%s' should be str" % type(value)
 
     value = value.lower()
-    if value == "true" or value == "t" or value == "yes" or value == "y":
-        return True
-    elif value == "false" or value == "f" or value == "no" or value == "n":
-        return False
-
-    raise ValueError, "cannot convert '%s' to bool" % value
+    result = _bool_dict.get(value, None)
+    if result == None:
+        raise ValueError, "cannot convert '%s' to bool" % value
+    return result
 
 def toFrequency(value):
     if not isinstance(value, str):
diff --git a/sim/process.cc b/sim/process.cc
index 36ba2c5ec..ee5d347a1 100644
--- a/sim/process.cc
+++ b/sim/process.cc
@@ -36,6 +36,7 @@
 #include "base/loader/object_file.hh"
 #include "base/loader/symtab.hh"
 #include "base/statistics.hh"
+#include "config/full_system.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/smt.hh"
 #include "encumbered/cpu/full/thread.hh"
@@ -58,7 +59,7 @@ using namespace std;
 // when there's no OS: thus there's no resone to use it in FULL_SYSTEM
 // mode when we do have an OS
 //
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 #error "process.cc not compatible with FULL_SYSTEM"
 #endif
 
diff --git a/sim/process.hh b/sim/process.hh
index 96389ff2e..ef54ced78 100644
--- a/sim/process.hh
+++ b/sim/process.hh
@@ -34,7 +34,9 @@
 // when there's no OS: thus there's no reason to use it in FULL_SYSTEM
 // mode when we do have an OS.
 //
-#ifndef FULL_SYSTEM
+#include "config/full_system.hh"
+
+#if !FULL_SYSTEM
 
 #include <vector>