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authorGeoffrey Blake <geoffrey.blake@arm.com>2013-02-15 17:40:10 -0500
committerGeoffrey Blake <geoffrey.blake@arm.com>2013-02-15 17:40:10 -0500
commitca96e7bff1dfaa8e0a6d900feb88c711198b4b2b (patch)
treedde572f60eb0c63c1ff9c78db8efd3fd236fc594
parent8e79c68936f819e9efa05e5085232bd501af2bc7 (diff)
downloadgem5-ca96e7bff1dfaa8e0a6d900feb88c711198b4b2b.tar.xz
cpu: Avoid duplicate entries in tracking structures for writes to misc regs
setMiscReg currently makes a new entry for each write to a misc reg without checking for duplicates, this can cause a triggering of the assert if an instruction get replayed and writes to the same misc regs multiple times. This fix prevents duplicate entries and instead updates the value.
-rw-r--r--src/cpu/o3/dyn_inst.hh12
1 files changed, 11 insertions, 1 deletions
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index c8cdf7a1f..082c1f5d4 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -149,8 +149,18 @@ class BaseO3DynInst : public BaseDynInst<Impl>
void setMiscReg(int misc_reg, const MiscReg &val)
{
/** Writes to misc. registers are recorded and deferred until the
- * commit stage, when updateMiscRegs() is called.
+ * commit stage, when updateMiscRegs() is called. First, check if
+ * the misc reg has been written before and update its value to be
+ * committed instead of making a new entry. If not, make a new
+ * entry and record the write.
*/
+ for (int idx = 0; idx < _numDestMiscRegs; idx++) {
+ if (_destMiscRegIdx[idx] == misc_reg) {
+ _destMiscRegVal[idx] = val;
+ return;
+ }
+ }
+
assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs);
_destMiscRegIdx[_numDestMiscRegs] = misc_reg;
_destMiscRegVal[_numDestMiscRegs] = val;